[SubZero] Fix f64 to/from i64 moves

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 97 matching lines @@
 
 void TargetMIPS32::assignVarStackSlots(VarList &SortedSpilledVariables,
                                        size_t SpillAreaPaddingBytes,
                                        size_t SpillAreaSizeBytes,
                                        size_t GlobalsAndSubsequentPaddingSize) {
   const VariablesMetadata *VMetadata = Func->getVMetadata();
   size_t GlobalsSpaceUsed = SpillAreaPaddingBytes;
   size_t NextStackOffset = SpillAreaPaddingBytes;
   CfgVector<size_t> LocalsSize(Func->getNumNodes());
   const bool SimpleCoalescing = !callsReturnsTwice();
-
   for (Variable *Var : SortedSpilledVariables) {
     size_t Increment = typeWidthInBytesOnStack(Var->getType());
     if (SimpleCoalescing && VMetadata->isTracked(Var)) {
       if (VMetadata->isMultiBlock(Var)) {
         GlobalsSpaceUsed += Increment;
         NextStackOffset = GlobalsSpaceUsed;
       } else {
         SizeT NodeIndex = VMetadata->getLocalUseNode(Var)->getIndex();
         LocalsSize[NodeIndex] += Increment;
         NextStackOffset = SpillAreaPaddingBytes +
@@ skipping 1605 matching lines @@
           } else {
             // Split it into two mtc1 instructions
             if (MovInstr->getSrcSize() == 2) {
               const auto FirstReg =
                   (llvm::cast<Variable>(MovInstr->getSrc(0)))->getRegNum();
               const auto SecondReg =
                   (llvm::cast<Variable>(MovInstr->getSrc(1)))->getRegNum();
               SrcGPRHi = Target->makeReg(IceType_i32, FirstReg);
               SrcGPRLo = Target->makeReg(IceType_i32, SecondReg);
             } else {
+              SrcGPRLo = Target->makeReg(
+                  IceType_i32, RegMIPS32::get64PairFirstRegNum(SRegNum));
               SrcGPRHi = Target->makeReg(
-                  IceType_i32, RegMIPS32::get64PairFirstRegNum(SRegNum));
-              SrcGPRLo = Target->makeReg(
                   IceType_i32, RegMIPS32::get64PairSecondRegNum(SRegNum));
             }
           }
           Variable *DstFPRHi = Target->makeReg(
               IceType_f32, RegMIPS32::get64PairFirstRegNum(DRegNum));
           Variable *DstFPRLo = Target->makeReg(
               IceType_f32, RegMIPS32::get64PairSecondRegNum(DRegNum));
           Target->_mov(DstFPRHi, SrcGPRLo);
           Target->_mov(DstFPRLo, SrcGPRHi);
           Legalized = true;
@@ skipping 11 matching lines @@
       }
       MovInstr->setDeleted();
       return;
     }
   }
 
   if (!Dest->hasReg()) {
     auto *SrcR = llvm::cast<Variable>(Src);
     assert(SrcR->hasReg());
     assert(!SrcR->isRematerializable());
-    int32_t Offset = 0;
-
-    if (MovInstr->getDestHi() != nullptr)
-      Offset = MovInstr->getDestHi()->getStackOffset();
-    else
-      Offset = Dest->getStackOffset();
+    int32_t Offset = Dest->getStackOffset();
 
     // This is a _mov(Mem(), Variable), i.e., a store.
     auto *Base = Target->getPhysicalRegister(Target->getFrameOrStackReg());
 
-    OperandMIPS32Mem *Addr = OperandMIPS32Mem::create(
+    OperandMIPS32Mem *TAddr = OperandMIPS32Mem::create(
         Target->Func, DestTy, Base,
         llvm::cast<ConstantInteger32>(Target->Ctx->getConstantInt32(Offset)));
+    OperandMIPS32Mem *TAddrHi = OperandMIPS32Mem::create(
+        Target->Func, DestTy, Base,
+        llvm::cast<ConstantInteger32>(
+                Target->Ctx->getConstantInt32(Offset + 4)));
+    OperandMIPS32Mem *Addr = legalizeMemOperand(TAddr);
 
     // FP arguments are passed in GP reg if first argument is in GP. In this
     // case type of the SrcR is still FP thus we need to explicitly generate sw
     // instead of swc1.
     const RegNumT RegNum = SrcR->getRegNum();
     const bool IsSrcGPReg = RegMIPS32::isGPRReg(SrcR->getRegNum());
     if (SrcTy == IceType_f32 && IsSrcGPReg) {
       Variable *SrcGPR = Target->makeReg(IceType_i32, RegNum);
       Target->_sw(SrcGPR, Addr);
     } else if (SrcTy == IceType_f64 && IsSrcGPReg) {
       Variable *SrcGPRHi =
           Target->makeReg(IceType_i32, RegMIPS32::get64PairFirstRegNum(RegNum));
       Variable *SrcGPRLo = Target->makeReg(
           IceType_i32, RegMIPS32::get64PairSecondRegNum(RegNum));
-      OperandMIPS32Mem *AddrHi = OperandMIPS32Mem::create(
-          Target->Func, DestTy, Base,
-          llvm::cast<ConstantInteger32>(
-              Target->Ctx->getConstantInt32(Offset + 4)));
-      Target->_sw(SrcGPRLo, Addr);
-      Target->_sw(SrcGPRHi, AddrHi);
+      Target->_sw(SrcGPRHi, Addr);
+      OperandMIPS32Mem *AddrHi = legalizeMemOperand(TAddrHi);
+      Target->_sw(SrcGPRLo, AddrHi);
     } else if (DestTy == IceType_f64 && IsSrcGPReg) {
       const auto FirstReg =
           (llvm::cast<Variable>(MovInstr->getSrc(0)))->getRegNum();
       const auto SecondReg =
           (llvm::cast<Variable>(MovInstr->getSrc(1)))->getRegNum();
-      Variable *SrcGPRHi = Target->makeReg(IceType_i32, SecondReg);
-      Variable *SrcGPRLo = Target->makeReg(IceType_i32, FirstReg);
-      OperandMIPS32Mem *AddrHi = OperandMIPS32Mem::create(
-          Target->Func, DestTy, Base,
-          llvm::cast<ConstantInteger32>(
-              Target->Ctx->getConstantInt32(Offset + 4)));
+      Variable *SrcGPRHi = Target->makeReg(IceType_i32, FirstReg);
+      Variable *SrcGPRLo = Target->makeReg(IceType_i32, SecondReg);
       Target->_sw(SrcGPRLo, Addr);
+      OperandMIPS32Mem *AddrHi = legalizeMemOperand(TAddrHi);
       Target->_sw(SrcGPRHi, AddrHi);
     } else {
       Target->_sw(SrcR, Addr);
     }
 
     Target->Context.insert<InstFakeDef>(Dest);
     Legalized = true;
   } else if (auto *Var = llvm::dyn_cast<Variable>(Src)) {
     if (Var->isRematerializable()) {
       // This is equivalent to an x86 _lea(RematOffset(%esp/%ebp), Variable).
 
       // ExtraOffset is only needed for stack-pointer based frames as we have
       // to account for spill storage.
       const int32_t ExtraOffset = (Var->getRegNum() == Target->getStackReg())
                                       ? Target->getFrameFixedAllocaOffset()
                                       : 0;
 
       const int32_t Offset = Var->getStackOffset() + ExtraOffset;
       Variable *Base = Target->getPhysicalRegister(Var->getRegNum());
       Variable *T = newBaseRegister(Base, Offset, Dest->getRegNum());
       Target->_mov(Dest, T);
       Legalized = true;
     } else {
       if (!Var->hasReg()) {
         // This is a _mov(Variable, Mem()), i.e., a load.
         const int32_t Offset = Var->getStackOffset();
         auto *Base = Target->getPhysicalRegister(Target->getFrameOrStackReg());
-        OperandMIPS32Mem *Addr;
-        Addr = OperandMIPS32Mem::create(
-            Target->Func, DestTy, Base,
-            llvm::cast<ConstantInteger32>(
-                Target->Ctx->getConstantInt32(Offset)));
-        Target->_lw(Dest, Addr);
+        const RegNumT RegNum = Dest->getRegNum();
+        const bool IsDstGPReg = RegMIPS32::isGPRReg(Dest->getRegNum());
+        // If we are moving i64 to a double using stack then the address may
+        // not be aligned to 8-byte boundary as we split i64 into Hi-Lo parts
+        // and store them individually with 4-byte alignment. Load the Hi-Lo
+        // parts in TmpReg and move them to the dest using mtc1.
+        if (DestTy == IceType_f64 && !Utils::IsAligned(Offset, 8)
+            && !IsDstGPReg) {
+          auto *Reg = Target->makeReg(IceType_i32, Target->getReservedTmpReg());
+          const RegNumT RegNum = Dest->getRegNum();
+          Variable *DestLo = Target->makeReg(
+                IceType_f32, RegMIPS32::get64PairFirstRegNum(RegNum));
+          Variable *DestHi = Target->makeReg(
+                IceType_f32, RegMIPS32::get64PairSecondRegNum(RegNum));
+          OperandMIPS32Mem *AddrLo = OperandMIPS32Mem::create(
+                Target->Func, IceType_i32, Base,
+                llvm::cast<ConstantInteger32>(
+                        Target->Ctx->getConstantInt32(Offset)));
+          OperandMIPS32Mem *AddrHi = OperandMIPS32Mem::create(
+                Target->Func, IceType_i32, Base,
+                llvm::cast<ConstantInteger32>(
+                        Target->Ctx->getConstantInt32(Offset + 4)));
+          Target->_lw(Reg, AddrLo);
+          Target->_mov(DestLo, Reg);
+          Target->_lw(Reg, AddrHi);
+          Target->_mov(DestHi, Reg);
+        } else {
+          OperandMIPS32Mem *TAddr = OperandMIPS32Mem::create(
+                Target->Func, DestTy, Base, llvm::cast<ConstantInteger32>(
+                        Target->Ctx->getConstantInt32(Offset)));
+          OperandMIPS32Mem *Addr = legalizeMemOperand(TAddr);
+          OperandMIPS32Mem *TAddrHi = OperandMIPS32Mem::create(
+                Target->Func, DestTy, Base, llvm::cast<ConstantInteger32>(
+                    Target->Ctx->getConstantInt32(Offset + 4)));
+          // FP arguments are passed in GP reg if first argument is in GP.
+          // In this case type of the Dest is still FP thus we need to
+          // explicitly generate lw instead of lwc1.
+          if (DestTy == IceType_f32 && IsDstGPReg) {
+            Variable *DstGPR = Target->makeReg(IceType_i32, RegNum);
+            Target->_lw(DstGPR, Addr);
+          } else if (DestTy == IceType_f64 && IsDstGPReg) {
+            Variable *DstGPRHi = Target->makeReg(
+                IceType_i32, RegMIPS32::get64PairFirstRegNum(RegNum));
+            Variable *DstGPRLo = Target->makeReg(
+                IceType_i32, RegMIPS32::get64PairSecondRegNum(RegNum));
+            Target->_lw(DstGPRHi, Addr);
+           OperandMIPS32Mem *AddrHi = legalizeMemOperand(TAddrHi);
+            Target->_lw(DstGPRLo, AddrHi);
+          } else if (DestTy == IceType_f64 && IsDstGPReg) {
+            const auto FirstReg =
+                (llvm::cast<Variable>(MovInstr->getSrc(0)))->getRegNum();
+            const auto SecondReg =
+                (llvm::cast<Variable>(MovInstr->getSrc(1)))->getRegNum();
+            Variable *DstGPRHi = Target->makeReg(IceType_i32, FirstReg);
+            Variable *DstGPRLo = Target->makeReg(IceType_i32, SecondReg);
+            Target->_lw(DstGPRLo, Addr);
+            OperandMIPS32Mem *AddrHi = legalizeMemOperand(TAddrHi);
+            Target->_lw(DstGPRHi, AddrHi);
+          } else {
+            Target->_lw(Dest, Addr);
+          }
+        }
         Legalized = true;
       }
     }
   }
 
   if (Legalized) {
     if (MovInstr->isDestRedefined()) {
       Target->_set_dest_redefined();
     }
     MovInstr->setDeleted();
@@ skipping 663 matching lines @@
     _mul(T, Src0R, Src1R);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Shl: {
     _sllv(T, Src0R, Src1R);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Lshr: {
-    _srlv(T, Src0R, Src1R);
+    auto *T0R = Src0R;
+    auto *T1R = Src1R;
+    if (Dest->getType() != IceType_i32) {
+      T0R = makeReg(IceType_i32);
+      lowerCast(InstCast::create(Func, InstCast::Zext, T0R, Src0R));
+      T1R = makeReg(IceType_i32);
+      lowerCast(InstCast::create(Func, InstCast::Zext, T1R, Src1R));
+    }
+    _srlv(T, T0R, T1R);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Ashr: {
     _srav(T, Src0R, Src1R);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Udiv: {
     auto *T_Zero = I32Reg(RegMIPS32::Reg_ZERO);
-    _divu(T_Zero, Src0R, Src1R);
-    _teq(Src1R, T_Zero, DivideByZeroTrapCode); // Trap if divide-by-zero
+    auto *T0R = Src0R;
+    auto *T1R = Src1R;
+    if (Dest->getType() != IceType_i32) {
+      T0R = makeReg(IceType_i32);
+      lowerCast(InstCast::create(Func, InstCast::Zext, T0R, Src0R));
+      T1R = makeReg(IceType_i32);
+      lowerCast(InstCast::create(Func, InstCast::Zext, T1R, Src1R));
+    }
+    _divu(T_Zero, T0R, T1R);
+    _teq(T1R, T_Zero, DivideByZeroTrapCode); // Trap if divide-by-zero
     _mflo(T, T_Zero);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Sdiv: {
     auto *T_Zero = I32Reg(RegMIPS32::Reg_ZERO);
     _div(T_Zero, Src0R, Src1R);
     _teq(Src1R, T_Zero, DivideByZeroTrapCode); // Trap if divide-by-zero
     _mflo(T, T_Zero);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Urem: {
     auto *T_Zero = I32Reg(RegMIPS32::Reg_ZERO);
-    _divu(T_Zero, Src0R, Src1R);
-    _teq(Src1R, T_Zero, DivideByZeroTrapCode); // Trap if divide-by-zero
+    auto *T0R = Src0R;
+    auto *T1R = Src1R;
+    if (Dest->getType() != IceType_i32) {
+      T0R = makeReg(IceType_i32);
+      lowerCast(InstCast::create(Func, InstCast::Zext, T0R, Src0R));
+      T1R = makeReg(IceType_i32);
+      lowerCast(InstCast::create(Func, InstCast::Zext, T1R, Src1R));
+    }
+    _divu(T_Zero, T0R, T1R);
+    _teq(T1R, T_Zero, DivideByZeroTrapCode); // Trap if divide-by-zero
     _mfhi(T, T_Zero);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Srem: {
     auto *T_Zero = I32Reg(RegMIPS32::Reg_ZERO);
     _div(T_Zero, Src0R, Src1R);
     _teq(Src1R, T_Zero, DivideByZeroTrapCode); // Trap if divide-by-zero
     _mfhi(T, T_Zero);
     _mov(Dest, T);
@@ skipping 763 matching lines @@
     UnimplementedLoweringError(this, Instr);
     break;
   }
   case InstCast::Sitofp:
   case InstCast::Uitofp: {
     if (llvm::isa<Variable64On32>(Dest)) {
       llvm::report_fatal_error("i64-to-fp should have been prelowered.");
       return;
     }
     if (Src0Ty != IceType_i64) {
+      Variable *Src0R = legalizeToReg(Src0);
+      auto *T0R = Src0R;
+      if (Src0Ty != IceType_i32 && CastKind == InstCast::Uitofp) {
+        T0R = makeReg(IceType_i32);
+        lowerCast(InstCast::create(Func, InstCast::Zext, T0R, Src0R));
+      }
       if (isScalarIntegerType(Src0Ty) && DestTy == IceType_f32) {
-        Variable *Src0R = legalizeToReg(Src0);
         Variable *FTmp1 = makeReg(IceType_f32);
         Variable *FTmp2 = makeReg(IceType_f32);
-        _mtc1(FTmp1, Src0R);
+        _mtc1(FTmp1, T0R);
         _cvt_s_w(FTmp2, FTmp1);
         _mov(Dest, FTmp2);
         return;
       }
       if (isScalarIntegerType(Src0Ty) && DestTy == IceType_f64) {
-        Variable *Src0R = legalizeToReg(Src0);
         Variable *FTmp1 = makeReg(IceType_f64);
         Variable *FTmp2 = makeReg(IceType_f64);
-        _mtc1(FTmp1, Src0R);
+        _mtc1(FTmp1, T0R);
         _cvt_d_w(FTmp2, FTmp1);
         _mov(Dest, FTmp2);
         return;
       }
     }
     UnimplementedLoweringError(this, Instr);
     break;
   }
   case InstCast::Bitcast: {
     Operand *Src0 = Instr->getSrc(0);
@@ skipping 26 matching lines @@
       break;
     case IceType_i32:
     case IceType_f32: {
       Variable *Src0R = legalizeToReg(Src0);
       _mov(Dest, Src0R);
       break;
     }
     case IceType_i64: {
       assert(Src0->getType() == IceType_f64);
       Variable *Src0R = legalizeToReg(Src0);
-      auto *Dest64 = llvm::cast<Variable64On32>(Dest);
-      _mov(Dest64, Src0R);
+      auto *T = llvm::cast<Variable64On32>(Func->makeVariable(IceType_i64));
+      T->initHiLo(Func);
+      T->getHi()->setMustHaveReg();
+      T->getLo()->setMustHaveReg();
+      _mov(T, Src0R);
+      lowerAssign(InstAssign::create(Func, Dest, T));
       break;
     }
     case IceType_f64: {
       assert(Src0->getType() == IceType_i64);
       const uint32_t Mask = 0xFFFFFFFF;
       if (auto *C64 = llvm::dyn_cast<ConstantInteger64>(Src0)) {
         Variable *RegHi, *RegLo;
         const uint64_t Value = C64->getValue();
         uint64_t Upper32Bits = (Value >> INT32_BITS) & Mask;
         uint64_t Lower32Bits = Value & Mask;
@@ skipping 1811 matching lines @@
 TargetHeaderMIPS32::TargetHeaderMIPS32(GlobalContext *Ctx)
     : TargetHeaderLowering(Ctx) {}
 
 void TargetHeaderMIPS32::lower() {
   OstreamLocker L(Ctx);
   Ostream &Str = Ctx->getStrEmit();
   Str << "\t.set\t"
       << "nomicromips\n";
   Str << "\t.set\t"
       << "nomips16\n";
+  Str << "\t.set\t"
+      << "noat\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice