[turbofan][X64] Movzxbl/Movsxbl/Movzxwl/Movsxwl also zero extend to 64bit.

src/compiler/x64/instruction-selector-x64.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <algorithm>
 
 #include "src/base/adapters.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
@@ skipping 1232 matching lines @@
       Node* const value = node->InputAt(0);
       switch (value->opcode()) {
         case IrOpcode::kInt32AddWithOverflow:
         case IrOpcode::kInt32SubWithOverflow:
         case IrOpcode::kInt32MulWithOverflow:
           return true;
         default:
           return false;
       }
     }
+    case IrOpcode::kLoad: {
+      // The movzxbl/movsxbl/movzxwl/movsxwl operations implicitly zero-extend
+      // to 64-bit on x64,
+      // so the zero-extension is a no-op.
+      LoadRepresentation load_rep = LoadRepresentationOf(node->op());
+      ArchOpcode opcode = GetLoadOpcode(load_rep);

[Benedikt Meurer, 2016/10/17 08:20:42]

How about pattern matching the representation instead of the x64 opcode?

+      switch (opcode) {
+        case kX64Movzxbl:
+        case kX64Movsxbl:
+        case kX64Movzxwl:
+        case kX64Movsxwl:
+          return true;
+        default:
+          return false;
+      }
+    }
     default:
       return false;
   }
 }
 
 }  // namespace
 
 void InstructionSelector::VisitChangeUint32ToUint64(Node* node) {
   X64OperandGenerator g(this);
   Node* value = node->InputAt(0);
   if (ZeroExtendsWord32ToWord64(value)) {
     // These 32-bit operations implicitly zero-extend to 64-bit on x64, so the
     // zero-extension is a no-op.
     return EmitIdentity(node);
   }
+

[titzer, 2016/10/17 08:13:35]

Spurious whitespace change.

   Emit(kX64Movl, g.DefineAsRegister(node), g.Use(value));
 }
 
 
 namespace {
 
 void VisitRO(InstructionSelector* selector, Node* node,
              InstructionCode opcode) {
   X64OperandGenerator g(selector);
   selector->Emit(opcode, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
@@ skipping 1055 matching lines @@
 // static
 MachineOperatorBuilder::AlignmentRequirements
 InstructionSelector::AlignmentRequirements() {
   return MachineOperatorBuilder::AlignmentRequirements::
       FullUnalignedAccessSupport();
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8