Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(291)

Side by Side Diff: src/IceTargetLoweringMIPS32.h

Issue 2425673002: [Subzero][MIPS32] Account for variable alloca alignment bytes in addProlog (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Addressed review comments Created 4 years, 2 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/IceInstMIPS32.h ('k') | src/IceTargetLoweringMIPS32.cpp » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
(...skipping 716 matching lines...) Expand 10 before | Expand all | Expand 10 after
727 727
728 public: 728 public:
729 explicit PostLoweringLegalizer(TargetMIPS32 *Target) 729 explicit PostLoweringLegalizer(TargetMIPS32 *Target)
730 : Target(Target), StackOrFrameReg(Target->getPhysicalRegister( 730 : Target(Target), StackOrFrameReg(Target->getPhysicalRegister(
731 Target->getFrameOrStackReg())) {} 731 Target->getFrameOrStackReg())) {}
732 732
733 /// Legalizes Mem. if Mem.Base is a rematerializable variable, 733 /// Legalizes Mem. if Mem.Base is a rematerializable variable,
734 /// Mem.Offset is fixed up. 734 /// Mem.Offset is fixed up.
735 OperandMIPS32Mem *legalizeMemOperand(OperandMIPS32Mem *Mem); 735 OperandMIPS32Mem *legalizeMemOperand(OperandMIPS32Mem *Mem);
736 736
737 /// Legalizes Immediate if larger value overflows range of 16 bits
738 Variable *legalizeImmediate(int32_t Imm);
739
737 /// Legalizes Mov if its Source (or Destination) is a spilled Variable, or 740 /// Legalizes Mov if its Source (or Destination) is a spilled Variable, or
738 /// if its Source is a Rematerializable variable (this form is used in lieu 741 /// if its Source is a Rematerializable variable (this form is used in lieu
739 /// of lea, which is not available in MIPS.) 742 /// of lea, which is not available in MIPS.)
740 /// 743 ///
741 /// Moves to memory become store instructions, and moves from memory, loads. 744 /// Moves to memory become store instructions, and moves from memory, loads.
742 void legalizeMov(InstMIPS32Mov *Mov); 745 void legalizeMov(InstMIPS32Mov *Mov);
743 746
744 private: 747 private:
745 /// Creates a new Base register centered around [Base, +/- Offset]. 748 /// Creates a new Base register centered around [Base, +/- Offset].
746 Variable *newBaseRegister(Variable *Base, int32_t Offset, 749 Variable *newBaseRegister(Variable *Base, int32_t Offset,
747 RegNumT ScratchRegNum); 750 RegNumT ScratchRegNum);
748 751
749 TargetMIPS32 *const Target; 752 TargetMIPS32 *const Target;
750 Variable *const StackOrFrameReg; 753 Variable *const StackOrFrameReg;
751 }; 754 };
752 755
753 bool UsesFramePointer = false; 756 bool UsesFramePointer = false;
754 bool NeedsStackAlignment = false; 757 bool NeedsStackAlignment = false;
755 bool MaybeLeafFunc = true; 758 bool MaybeLeafFunc = true;
756 bool PrologEmitsFixedAllocas = false; 759 bool PrologEmitsFixedAllocas = false;
757 bool VariableAllocaUsed = false; 760 bool VariableAllocaUsed = false;
758 uint32_t MaxOutArgsSizeBytes = 0; 761 uint32_t MaxOutArgsSizeBytes = 0;
759 uint32_t TotalStackSizeBytes = 0; 762 uint32_t TotalStackSizeBytes = 0;
760 uint32_t CurrentAllocaOffset = 0; 763 uint32_t CurrentAllocaOffset = 0;
764 uint32_t VariableAllocaAlignBytes = 0;
761 static SmallBitVector TypeToRegisterSet[RCMIPS32_NUM]; 765 static SmallBitVector TypeToRegisterSet[RCMIPS32_NUM];
762 static SmallBitVector TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; 766 static SmallBitVector TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
763 static SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM]; 767 static SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM];
764 SmallBitVector RegsUsed; 768 SmallBitVector RegsUsed;
765 VarList PhysicalRegisters[IceType_NUM]; 769 VarList PhysicalRegisters[IceType_NUM];
766 VarList PreservedGPRs; 770 VarList PreservedGPRs;
767 static constexpr uint32_t CHAR_BITS = 8; 771 static constexpr uint32_t CHAR_BITS = 8;
768 static constexpr uint32_t INT32_BITS = 32; 772 static constexpr uint32_t INT32_BITS = 32;
769 size_t SpillAreaSizeBytes = 0; 773 size_t SpillAreaSizeBytes = 0;
770 size_t FixedAllocaSizeBytes = 0; 774 size_t FixedAllocaSizeBytes = 0;
(...skipping 106 matching lines...) Expand 10 before | Expand all | Expand 10 after
877 explicit TargetHeaderMIPS32(GlobalContext *Ctx); 881 explicit TargetHeaderMIPS32(GlobalContext *Ctx);
878 882
879 private: 883 private:
880 ~TargetHeaderMIPS32() = default; 884 ~TargetHeaderMIPS32() = default;
881 }; 885 };
882 886
883 } // end of namespace MIPS32 887 } // end of namespace MIPS32
884 } // end of namespace Ice 888 } // end of namespace Ice
885 889
886 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H 890 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H
OLDNEW
« no previous file with comments | « src/IceInstMIPS32.h ('k') | src/IceTargetLoweringMIPS32.cpp » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698