[Subzero][MIPS32] Account for variable alloca alignment bytes in addProlog

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 1360 matching lines @@
                        GlobalsSize, LocalsSlotsAlignmentBytes,
                        &SpillAreaPaddingBytes, &LocalsSlotsPaddingBytes);
   SpillAreaSizeBytes += SpillAreaPaddingBytes + LocalsSlotsPaddingBytes;
   uint32_t GlobalsAndSubsequentPaddingSize =
       GlobalsSize + LocalsSlotsPaddingBytes;
 
   // Adds the out args space to the stack, and align SP if necessary.
   if (!NeedsStackAlignment) {
     SpillAreaSizeBytes += MaxOutArgsSizeBytes * (VariableAllocaUsed ? 0 : 1);
   } else {
-    uint32_t StackOffset = PreservedRegsSizeBytes;
-    uint32_t StackSize = applyStackAlignment(StackOffset + SpillAreaSizeBytes);
-    if (!VariableAllocaUsed)
-      StackSize = applyStackAlignment(StackSize + MaxOutArgsSizeBytes);
-    SpillAreaSizeBytes = StackSize - StackOffset;
+    SpillAreaSizeBytes = applyStackAlignment(
+        SpillAreaSizeBytes +
+        (VariableAllocaUsed ? VariableAllocaAlignBytes : MaxOutArgsSizeBytes));
   }
 
   // Combine fixed alloca with SpillAreaSize.
   SpillAreaSizeBytes += FixedAllocaSizeBytes;
 
   TotalStackSizeBytes = PreservedRegsSizeBytes + SpillAreaSizeBytes;
 
   // Generate "addiu sp, sp, -TotalStackSizeBytes"
   if (TotalStackSizeBytes) {
     // Use the scratch register if needed to legalize the immediate.
@@ skipping 387 matching lines @@
   if (!OperandMIPS32Mem::canHoldOffset(Mem->getType(), SignExt, Offset)) {
     Base = newBaseRegister(Base, Offset, Target->getReservedTmpReg());
     Offset = 0;
   }
 
   return OperandMIPS32Mem::create(
       Target->Func, Mem->getType(), Base,
       llvm::cast<ConstantInteger32>(Target->Ctx->getConstantInt32(Offset)));
 }
 
+Variable *TargetMIPS32::PostLoweringLegalizer::legalizeImmediate(int32_t Imm) {
+  Variable *Reg = nullptr;
+  if (!((std::numeric_limits<int16_t>::min() <= Imm) &&
+        (Imm <= std::numeric_limits<int16_t>::max()))) {
+    const uint32_t UpperBits = (Imm >> 16) & 0xFFFF;
+    const uint32_t LowerBits = Imm & 0xFFFF;
+    Variable *TReg = Target->makeReg(IceType_i32, Target->getReservedTmpReg());
+    Reg = Target->makeReg(IceType_i32, Target->getReservedTmpReg());
+    if (LowerBits) {
+      Target->_lui(TReg, Target->Ctx->getConstantInt32(UpperBits));
+      Target->_ori(Reg, TReg, LowerBits);
+    } else {
+      Target->_lui(Reg, Target->Ctx->getConstantInt32(UpperBits));
+    }
+  }
+  return Reg;
+}
+
 void TargetMIPS32::postLowerLegalization() {
   Func->dump("Before postLowerLegalization");
   assert(hasComputedFrame());
   for (CfgNode *Node : Func->getNodes()) {
     Context.init(Node);
     PostLoweringLegalizer Legalizer(this);
     while (!Context.atEnd()) {
       PostIncrLoweringContext PostIncrement(Context);
       Inst *CurInstr = iteratorToInst(Context.getCur());
       const SizeT NumSrcs = CurInstr->getSrcSize();
@@ skipping 42 matching lines @@
         }
         continue;
       }
       if (llvm::isa<InstMIPS32Ldc1>(CurInstr)) {
         if (auto *LegalMem = Legalizer.legalizeMemOperand(Src0M)) {
           _ldc1(Dst, LegalMem);
           CurInstr->setDeleted();
         }
         continue;
       }
+      if (auto *AddiuInstr = llvm::dyn_cast<InstMIPS32Addiu>(CurInstr)) {
+        if (auto *LegalImm = Legalizer.legalizeImmediate(
+                static_cast<int32_t>(AddiuInstr->getImmediateValue()))) {
+          _addu(Dst, Src0V, LegalImm);
+          CurInstr->setDeleted();
+        }
+        continue;
+      }
     }
   }
 }
 
 Operand *TargetMIPS32::loOperand(Operand *Operand) {
   assert(Operand->getType() == IceType_i64);
   if (auto *Var64On32 = llvm::dyn_cast<Variable64On32>(Operand))
     return Var64On32->getLo();
   if (auto *Const = llvm::dyn_cast<ConstantInteger64>(Operand)) {
     return Ctx->getConstantInt32(static_cast<uint32_t>(Const->getValue()));
@@ skipping 171 matching lines @@
     auto *T = I32Reg();
     _addiu(T, SP, CurrentAllocaOffset);
     _mov(Dest, T);
     CurrentAllocaOffset += Value;
     return;
 
   } else {
     // Non-constant sizes need to be adjusted to the next highest multiple of
     // the required alignment at runtime.
     VariableAllocaUsed = true;
+    VariableAllocaAlignBytes = AlignmentParam;
     Variable *AlignAmount;
     auto *TotalSizeR = legalizeToReg(TotalSize, Legal_Reg);
     auto *T1 = I32Reg();
     auto *T2 = I32Reg();
     auto *T3 = I32Reg();
     auto *T4 = I32Reg();
     auto *T5 = I32Reg();
     _addiu(T1, TotalSizeR, MIPS32_STACK_ALIGNMENT_BYTES - 1);
     _addiu(T2, getZero(), -MIPS32_STACK_ALIGNMENT_BYTES);
     _and(T3, T1, T2);
@@ skipping 3058 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice