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Side by Side Diff: src/IceTargetLoweringMIPS32.cpp

Issue 2425673002: [Subzero][MIPS32] Account for variable alloca alignment bytes in addProlog (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: formatted source code Created 4 years, 2 months ago
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1 // 1 //
2 // The Subzero Code Generator 2 // The Subzero Code Generator
3 // 3 //
4 // This file is distributed under the University of Illinois Open Source 4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details. 5 // License. See LICENSE.TXT for details.
6 // 6 //
7 //===----------------------------------------------------------------------===// 7 //===----------------------------------------------------------------------===//
8 /// 8 ///
9 /// \file 9 /// \file
10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost 10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
(...skipping 1360 matching lines...) Expand 10 before | Expand all | Expand 10 after
1371 GlobalsSize, LocalsSlotsAlignmentBytes, 1371 GlobalsSize, LocalsSlotsAlignmentBytes,
1372 &SpillAreaPaddingBytes, &LocalsSlotsPaddingBytes); 1372 &SpillAreaPaddingBytes, &LocalsSlotsPaddingBytes);
1373 SpillAreaSizeBytes += SpillAreaPaddingBytes + LocalsSlotsPaddingBytes; 1373 SpillAreaSizeBytes += SpillAreaPaddingBytes + LocalsSlotsPaddingBytes;
1374 uint32_t GlobalsAndSubsequentPaddingSize = 1374 uint32_t GlobalsAndSubsequentPaddingSize =
1375 GlobalsSize + LocalsSlotsPaddingBytes; 1375 GlobalsSize + LocalsSlotsPaddingBytes;
1376 1376
1377 // Adds the out args space to the stack, and align SP if necessary. 1377 // Adds the out args space to the stack, and align SP if necessary.
1378 if (!NeedsStackAlignment) { 1378 if (!NeedsStackAlignment) {
1379 SpillAreaSizeBytes += MaxOutArgsSizeBytes * (VariableAllocaUsed ? 0 : 1); 1379 SpillAreaSizeBytes += MaxOutArgsSizeBytes * (VariableAllocaUsed ? 0 : 1);
1380 } else { 1380 } else {
1381 uint32_t StackOffset = PreservedRegsSizeBytes;
1382 uint32_t StackSize = applyStackAlignment(StackOffset + SpillAreaSizeBytes);
1383 if (!VariableAllocaUsed) 1381 if (!VariableAllocaUsed)
Jim Stichnoth 2016/10/17 14:20:46 Maybe this could be simplified/refactored slightly
sagar.thakur 2016/10/18 07:02:21 Done.
1384 StackSize = applyStackAlignment(StackSize + MaxOutArgsSizeBytes); 1382 SpillAreaSizeBytes =
1385 SpillAreaSizeBytes = StackSize - StackOffset; 1383 applyStackAlignment(SpillAreaSizeBytes + MaxOutArgsSizeBytes);
1384 else
1385 SpillAreaSizeBytes =
1386 applyStackAlignment(SpillAreaSizeBytes + VariableAllocaAlignBytes);
1386 } 1387 }
1387 1388
1388 // Combine fixed alloca with SpillAreaSize. 1389 // Combine fixed alloca with SpillAreaSize.
1389 SpillAreaSizeBytes += FixedAllocaSizeBytes; 1390 SpillAreaSizeBytes += FixedAllocaSizeBytes;
1390 1391
1391 TotalStackSizeBytes = PreservedRegsSizeBytes + SpillAreaSizeBytes; 1392 TotalStackSizeBytes = PreservedRegsSizeBytes + SpillAreaSizeBytes;
1392 1393
1393 // Generate "addiu sp, sp, -TotalStackSizeBytes" 1394 // Generate "addiu sp, sp, -TotalStackSizeBytes"
1394 if (TotalStackSizeBytes) { 1395 if (TotalStackSizeBytes) {
1395 // Use the scratch register if needed to legalize the immediate. 1396 // Use the scratch register if needed to legalize the immediate.
(...skipping 387 matching lines...) Expand 10 before | Expand all | Expand 10 after
1783 if (!OperandMIPS32Mem::canHoldOffset(Mem->getType(), SignExt, Offset)) { 1784 if (!OperandMIPS32Mem::canHoldOffset(Mem->getType(), SignExt, Offset)) {
1784 Base = newBaseRegister(Base, Offset, Target->getReservedTmpReg()); 1785 Base = newBaseRegister(Base, Offset, Target->getReservedTmpReg());
1785 Offset = 0; 1786 Offset = 0;
1786 } 1787 }
1787 1788
1788 return OperandMIPS32Mem::create( 1789 return OperandMIPS32Mem::create(
1789 Target->Func, Mem->getType(), Base, 1790 Target->Func, Mem->getType(), Base,
1790 llvm::cast<ConstantInteger32>(Target->Ctx->getConstantInt32(Offset))); 1791 llvm::cast<ConstantInteger32>(Target->Ctx->getConstantInt32(Offset)));
1791 } 1792 }
1792 1793
1794 Variable *TargetMIPS32::PostLoweringLegalizer::legalizeImmidiate(int32_t Imm) {
Jim Stichnoth 2016/10/17 14:20:46 legalizeImmediate
sagar.thakur 2016/10/18 07:02:21 Done.
1795 if ((std::numeric_limits<int16_t>::min() <= Imm) &&
1796 (Imm <= std::numeric_limits<int16_t>::max())) {
1797 return nullptr;
1798 } else {
Jim Stichnoth 2016/10/17 14:20:45 http://llvm.org/docs/CodingStandards.html#don-t-us
sagar.thakur 2016/10/18 07:02:21 Done.
1799 uint32_t UpperBits = (Imm >> 16) & 0xFFFF;
Jim Stichnoth 2016/10/17 14:20:46 const ?
sagar.thakur 2016/10/18 07:02:21 Done.
1800 uint32_t LowerBits = Imm & 0xFFFF;
1801 Variable *TReg = Target->makeReg(IceType_i32, Target->getReservedTmpReg());
1802 Variable *Reg = Target->makeReg(IceType_i32, Target->getReservedTmpReg());
1803 if (LowerBits) {
1804 Target->_lui(TReg, Target->Ctx->getConstantInt32(UpperBits));
1805 Target->_ori(Reg, TReg, LowerBits);
1806 } else {
1807 Target->_lui(Reg, Target->Ctx->getConstantInt32(UpperBits));
1808 }
1809 return Reg;
1810 }
1811 }
1812
1793 void TargetMIPS32::postLowerLegalization() { 1813 void TargetMIPS32::postLowerLegalization() {
1794 Func->dump("Before postLowerLegalization"); 1814 Func->dump("Before postLowerLegalization");
1795 assert(hasComputedFrame()); 1815 assert(hasComputedFrame());
1796 for (CfgNode *Node : Func->getNodes()) { 1816 for (CfgNode *Node : Func->getNodes()) {
1797 Context.init(Node); 1817 Context.init(Node);
1798 PostLoweringLegalizer Legalizer(this); 1818 PostLoweringLegalizer Legalizer(this);
1799 while (!Context.atEnd()) { 1819 while (!Context.atEnd()) {
1800 PostIncrLoweringContext PostIncrement(Context); 1820 PostIncrLoweringContext PostIncrement(Context);
1801 Inst *CurInstr = iteratorToInst(Context.getCur()); 1821 Inst *CurInstr = iteratorToInst(Context.getCur());
1802 const SizeT NumSrcs = CurInstr->getSrcSize(); 1822 const SizeT NumSrcs = CurInstr->getSrcSize();
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1845 } 1865 }
1846 continue; 1866 continue;
1847 } 1867 }
1848 if (llvm::isa<InstMIPS32Ldc1>(CurInstr)) { 1868 if (llvm::isa<InstMIPS32Ldc1>(CurInstr)) {
1849 if (auto *LegalMem = Legalizer.legalizeMemOperand(Src0M)) { 1869 if (auto *LegalMem = Legalizer.legalizeMemOperand(Src0M)) {
1850 _ldc1(Dst, LegalMem); 1870 _ldc1(Dst, LegalMem);
1851 CurInstr->setDeleted(); 1871 CurInstr->setDeleted();
1852 } 1872 }
1853 continue; 1873 continue;
1854 } 1874 }
1875 if (auto *AddiuInstr = llvm::dyn_cast<InstMIPS32Addiu>(CurInstr)) {
1876 if (auto *LegalImm = Legalizer.legalizeImmidiate(
1877 int32_t(AddiuInstr->getImmidiateValue()))) {
Jim Stichnoth 2016/10/17 14:20:46 Use reinterpret_cast<> instead of int32_t() ?
sagar.thakur 2016/10/18 07:02:21 Done. Used static cast because reinterpret cast do
1878 _addu(Dst, Src0V, LegalImm);
1879 CurInstr->setDeleted();
1880 }
1881 continue;
1882 }
1855 } 1883 }
1856 } 1884 }
1857 } 1885 }
1858 1886
1859 Operand *TargetMIPS32::loOperand(Operand *Operand) { 1887 Operand *TargetMIPS32::loOperand(Operand *Operand) {
1860 assert(Operand->getType() == IceType_i64); 1888 assert(Operand->getType() == IceType_i64);
1861 if (auto *Var64On32 = llvm::dyn_cast<Variable64On32>(Operand)) 1889 if (auto *Var64On32 = llvm::dyn_cast<Variable64On32>(Operand))
1862 return Var64On32->getLo(); 1890 return Var64On32->getLo();
1863 if (auto *Const = llvm::dyn_cast<ConstantInteger64>(Operand)) { 1891 if (auto *Const = llvm::dyn_cast<ConstantInteger64>(Operand)) {
1864 return Ctx->getConstantInt32(static_cast<uint32_t>(Const->getValue())); 1892 return Ctx->getConstantInt32(static_cast<uint32_t>(Const->getValue()));
(...skipping 171 matching lines...) Expand 10 before | Expand all | Expand 10 after
2036 auto *T = I32Reg(); 2064 auto *T = I32Reg();
2037 _addiu(T, SP, CurrentAllocaOffset); 2065 _addiu(T, SP, CurrentAllocaOffset);
2038 _mov(Dest, T); 2066 _mov(Dest, T);
2039 CurrentAllocaOffset += Value; 2067 CurrentAllocaOffset += Value;
2040 return; 2068 return;
2041 2069
2042 } else { 2070 } else {
2043 // Non-constant sizes need to be adjusted to the next highest multiple of 2071 // Non-constant sizes need to be adjusted to the next highest multiple of
2044 // the required alignment at runtime. 2072 // the required alignment at runtime.
2045 VariableAllocaUsed = true; 2073 VariableAllocaUsed = true;
2074 VariableAllocaAlignBytes = AlignmentParam;
2046 Variable *AlignAmount; 2075 Variable *AlignAmount;
2047 auto *TotalSizeR = legalizeToReg(TotalSize, Legal_Reg); 2076 auto *TotalSizeR = legalizeToReg(TotalSize, Legal_Reg);
2048 auto *T1 = I32Reg(); 2077 auto *T1 = I32Reg();
2049 auto *T2 = I32Reg(); 2078 auto *T2 = I32Reg();
2050 auto *T3 = I32Reg(); 2079 auto *T3 = I32Reg();
2051 auto *T4 = I32Reg(); 2080 auto *T4 = I32Reg();
2052 auto *T5 = I32Reg(); 2081 auto *T5 = I32Reg();
2053 _addiu(T1, TotalSizeR, MIPS32_STACK_ALIGNMENT_BYTES - 1); 2082 _addiu(T1, TotalSizeR, MIPS32_STACK_ALIGNMENT_BYTES - 1);
2054 _addiu(T2, getZero(), -MIPS32_STACK_ALIGNMENT_BYTES); 2083 _addiu(T2, getZero(), -MIPS32_STACK_ALIGNMENT_BYTES);
2055 _and(T3, T1, T2); 2084 _and(T3, T1, T2);
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5114 Str << "\t.set\t" 5143 Str << "\t.set\t"
5115 << "nomips16\n"; 5144 << "nomips16\n";
5116 } 5145 }
5117 5146
5118 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; 5147 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
5119 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; 5148 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
5120 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; 5149 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
5121 5150
5122 } // end of namespace MIPS32 5151 } // end of namespace MIPS32
5123 } // end of namespace Ice 5152 } // end of namespace Ice
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