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Issue 2420033002: [SubZero] Handle relocatable constants for MIPS (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Addressed review comments Created 4 years, 2 months ago
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1 ; Assembly test for simple arithmetic operations. 1 ; Assembly test for simple arithmetic operations.
2 2
3 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 3 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
4 ; RUN: --target x8632 -i %s --args -O2 \ 4 ; RUN: --target x8632 -i %s --args -O2 \
5 ; RUN: | %if --need=target_X8632 --command FileCheck %s 5 ; RUN: | %if --need=target_X8632 --command FileCheck %s
6 6
7 ; RUN: %if --need=target_ARM32 \ 7 ; RUN: %if --need=target_ARM32 \
8 ; RUN: --command %p2i --filetype=obj --disassemble --target arm32 \ 8 ; RUN: --command %p2i --filetype=obj --disassemble --target arm32 \
9 ; RUN: -i %s --args -O2 \ 9 ; RUN: -i %s --args -O2 \
10 ; RUN: | %if --need=target_ARM32 \ 10 ; RUN: | %if --need=target_ARM32 \
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269 269
270 define internal i32 @ShlReloc(i32 %a) { 270 define internal i32 @ShlReloc(i32 %a) {
271 entry: 271 entry:
272 %opnd = ptrtoint [4 x i8]* @G to i32 272 %opnd = ptrtoint [4 x i8]* @G to i32
273 %result = shl i32 %a, %opnd 273 %result = shl i32 %a, %opnd
274 ret i32 %result 274 ret i32 %result
275 } 275 }
276 ; CHECK-LABEL: ShlReloc 276 ; CHECK-LABEL: ShlReloc
277 ; CHECK: shl {{.*}},cl 277 ; CHECK: shl {{.*}},cl
278 278
279 ; MIPS32-LABEL: ShlReloc
280 ; MIPS32: lui [[REG:.*]],{{.*}} R_MIPS_HI16 G
281 ; MIPS32: addiu [[REG]],[[REG]],{{.*}} R_MIPS_LO16 G
282 ; MIPS32: sllv {{.*}},{{.*}},[[REG]]
283
279 define internal i32 @LshrReloc(i32 %a) { 284 define internal i32 @LshrReloc(i32 %a) {
280 entry: 285 entry:
281 %opnd = ptrtoint [4 x i8]* @G to i32 286 %opnd = ptrtoint [4 x i8]* @G to i32
282 %result = lshr i32 %a, %opnd 287 %result = lshr i32 %a, %opnd
283 ret i32 %result 288 ret i32 %result
284 } 289 }
285 ; CHECK-LABEL: LshrReloc 290 ; CHECK-LABEL: LshrReloc
286 ; CHECK: shr {{.*}},cl 291 ; CHECK: shr {{.*}},cl
287 292
293 ; MIPS32-LABEL: LshrReloc
294 ; MIPS32: lui [[REG:.*]],{{.*}} R_MIPS_HI16 G
295 ; MIPS32: addiu [[REG]],[[REG]],{{.*}} R_MIPS_LO16 G
296 ; MIPS32: srlv {{.*}},{{.*}},[[REG]]
297
288 define internal i32 @AshrReloc(i32 %a) { 298 define internal i32 @AshrReloc(i32 %a) {
289 entry: 299 entry:
290 %opnd = ptrtoint [4 x i8]* @G to i32 300 %opnd = ptrtoint [4 x i8]* @G to i32
291 %result = ashr i32 %a, %opnd 301 %result = ashr i32 %a, %opnd
292 ret i32 %result 302 ret i32 %result
293 } 303 }
294 ; CHECK-LABEL: AshrReloc 304 ; CHECK-LABEL: AshrReloc
295 ; CHECK: sar {{.*}},cl 305 ; CHECK: sar {{.*}},cl
306
307 ; MIPS32-LABEL: AshrReloc
308 ; MIPS32: lui [[REG:.*]],{{.*}} R_MIPS_HI16 G
309 ; MIPS32: addiu [[REG]],[[REG]],{{.*}} R_MIPS_LO16 G
310 ; MIPS32: srav {{.*}},{{.*}},[[REG]]
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