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1 // | 1 // |
2 // The Subzero Code Generator | 2 // The Subzero Code Generator |
3 // | 3 // |
4 // This file is distributed under the University of Illinois Open Source | 4 // This file is distributed under the University of Illinois Open Source |
5 // License. See LICENSE.TXT for details. | 5 // License. See LICENSE.TXT for details. |
6 // | 6 // |
7 //===----------------------------------------------------------------------===// | 7 //===----------------------------------------------------------------------===// |
8 /// | 8 /// |
9 /// \file | 9 /// \file |
10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost | 10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost |
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4840 return From; | 4840 return From; |
4841 } | 4841 } |
4842 | 4842 |
4843 if (llvm::isa<Constant>(From)) { | 4843 if (llvm::isa<Constant>(From)) { |
4844 if (llvm::isa<ConstantUndef>(From)) { | 4844 if (llvm::isa<ConstantUndef>(From)) { |
4845 From = legalizeUndef(From, RegNum); | 4845 From = legalizeUndef(From, RegNum); |
4846 if (isVectorType(Ty)) | 4846 if (isVectorType(Ty)) |
4847 return From; | 4847 return From; |
4848 } | 4848 } |
4849 if (auto *C = llvm::dyn_cast<ConstantRelocatable>(From)) { | 4849 if (auto *C = llvm::dyn_cast<ConstantRelocatable>(From)) { |
4850 (void)C; | |
4851 // TODO(reed kotler): complete this case for proper implementation | |
4852 Variable *Reg = makeReg(Ty, RegNum); | 4850 Variable *Reg = makeReg(Ty, RegNum); |
4853 Context.insert<InstFakeDef>(Reg); | 4851 Variable *TReg = makeReg(Ty, RegNum); |
| 4852 _lui(TReg, C, RO_Hi); |
| 4853 _addiu(Reg, TReg, C, RO_Lo); |
4854 return Reg; | 4854 return Reg; |
4855 } else if (auto *C32 = llvm::dyn_cast<ConstantInteger32>(From)) { | 4855 } else if (auto *C32 = llvm::dyn_cast<ConstantInteger32>(From)) { |
4856 const uint32_t Value = C32->getValue(); | 4856 const uint32_t Value = C32->getValue(); |
4857 // Use addiu if the immediate is a 16bit value. Otherwise load it | 4857 // Use addiu if the immediate is a 16bit value. Otherwise load it |
4858 // using a lui-ori instructions. | 4858 // using a lui-ori instructions. |
4859 Variable *Reg = makeReg(Ty, RegNum); | 4859 Variable *Reg = makeReg(Ty, RegNum); |
4860 if (isInt<16>(int32_t(Value))) { | 4860 if (isInt<16>(int32_t(Value))) { |
4861 Variable *Zero = getPhysicalRegister(RegMIPS32::Reg_ZERO, Ty); | 4861 Variable *Zero = getPhysicalRegister(RegMIPS32::Reg_ZERO, Ty); |
4862 Context.insert<InstFakeDef>(Zero); | 4862 Context.insert<InstFakeDef>(Zero); |
4863 _addiu(Reg, Zero, Value); | 4863 _addiu(Reg, Zero, Value); |
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5000 Str << "\t.set\t" | 5000 Str << "\t.set\t" |
5001 << "nomips16\n"; | 5001 << "nomips16\n"; |
5002 } | 5002 } |
5003 | 5003 |
5004 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; | 5004 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; |
5005 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; | 5005 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; |
5006 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; | 5006 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; |
5007 | 5007 |
5008 } // end of namespace MIPS32 | 5008 } // end of namespace MIPS32 |
5009 } // end of namespace Ice | 5009 } // end of namespace Ice |
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