Thumb2 Backend: 32-bit instruction encoding helper methods

src/arm/constants-arm.h

Index: src/arm/constants-arm.h
diff --git a/src/arm/constants-arm.h b/src/arm/constants-arm.h
index 7b79ccd42fa996c9aa6617ac1fcba88bfe9a98ba..ded3af2ef52133522586323f3431e5f8acf6c257 100644
--- a/src/arm/constants-arm.h
+++ b/src/arm/constants-arm.h
@@ -254,6 +254,159 @@ enum ThumbMode4_5Opcode16 {
 };
 
 
+enum ThumbOpcode32Mode1 {
+  AND_32_IMM = 0,
+  TST_32_IMM = 0,
+  BIC_32_IMM = 1,
+  ORR_32_IMM = 2,
+  MOV_32_IMM2 = 2,
+  ORN_32_IMM = 3,
+  MVN_32_IMM = 3,
+  EOR_32_IMM = 4,
+  TEQ_32_IMM = 4,
+  ADD_32_IMM3 = 8,
+  CMN_32_IMM = 8,
+  ADC_32_IMM = 10,
+  SBC_32_IMM = 11,
+  SUB_32_IMM3 = 13,
+  CMP_32_IMM = 13,
+  RSB_32_IMM = 14
+};
+
+
+enum ThumbOpcode32Mode3 {
+  ADD_32_IMM4 = 0,
+  MOV_32_IMM3 = 4,
+  SUB_32_IMM4 = 10,
+  MOVT_32_IMM = 12,
+  SBFX_32_IMM = 20,
+  BFI_32_IMM = 22,
+  BFC_32_IMM = 22,
+  USAT_32_IMM = 24,
+  UBFX_32_IMM = 28
+};
+
+
+enum ThumbOpcode32Mode4 {
+// Branches and misc control
+  B_32_3 = 0,
+  MSR_32_REG = 0,
+  MSR_32_REG2 = 0,
+  B_32_4 = 1,
+  BL_32_IMM = 5,
+  BLX_32_IMM = 4
+};
+
+
+enum ThumbOpcode32Mode6 {
+  STRD_32_IMM = 0,
+  STRD_32_IMM_OP2 = 2,
+  STRD_32_IMM2 = 2,
+  STRD_32_IMM2_OP2 = 0,
+  LDRD_32_IMM = 0,
+  LDRD_32_IMM_OP2 = 3,
+  LDRD_32_IMM_OP2_x1 = 1,  // else overwrites W
+  LDRD_32_IMM2 = 2,
+  LDRD_32_IMM2_OP2 = 1
+};
+
+
+enum ThumbOpcode32Mode7 {
+  LDR_32_IMM3 = 0,
+  LDR_32_IMM4 = 0,
+  LDR_32_REG = 0
+};
+
+
+enum ThumbOpcode32Mode8 {
+  LDRH_32_IMM2 = 1,
+  LDRH_32_IMM3 = 0,
+  LDRH_32_REG = 0,
+  LDRSH_32_IMM1 = 3,
+  LDRSH_32_IMM2 = 2,
+  LDRSH_32_REG = 2
+};
+
+
+enum ThumbOpcode32Mode9 {
+  LDRB_32_IMM2 = 1,
+  LDRB_32_IMM3 = 0,
+  LDRB_32_REG = 0,
+  LDRSB_32_IMM1 = 3,
+  LDRSB_32_IMM2 = 2,
+  LDRSB_32_REG = 2
+};
+
+
+enum ThumbOpcode32Mode10 {
+  STRB_32_IMM2 = 4,
+  STRB_32_IMM3 = 0,
+  STRB_32_REG = 0,
+  STRH_32_IMM2 = 5,
+  STRH_32_IMM3 = 1,
+  STRH_32_REG = 1,
+  STR_32_IMM2 = 6,
+  STR_32_IMM3 = 2,
+  STR_32_REG = 2
+};
+
+
+enum ThumbOpcode32Mode11 {
+  AND_32_REG2 = 0,
+  TST_32_REG2 = 0,
+  BIC_32_REG2 = 1,
+  ORR_32_REG2 = 2,
+  MOV_32_REG3 = 2,
+  MVN_32_REG2 = 3,
+  ORN_32_REG = 3,
+  EOR_32_REG2 = 4,
+  TEQ_32_REG = 4,
+  ADD_32_REG3 = 8,
+  CMN_32_REG2 = 8,
+  ADC_32_REG2 = 10,
+  SBC_32_REG2 = 11,
+  SUB_32_REG2 = 13,
+  CMP_32_REG3 = 13,
+  RSB_32_REG = 14
+};
+
+
+enum ThumbOpcode32Mode12 {
+  LSL_32_REG = 0,
+  LSR_32_REG = 2,
+  ASR_32_REG = 4,
+  ROR_32_REG = 6,
+  SXTAH_32_REG = 0,
+  SXTH_32_REG = 0,
+  UXTAH_32_REG = 1,
+  UXTH_32_REG = 1,
+  SXTAB16_32_REG = 2,
+  SXTB16_32_REG = 2,
+  UXTAB16_32_REG = 3,
+  UXTB16_32_REG = 3,
+  SXTAB_32_REG = 4,
+  SXTB_32_REG = 4,
+  UXTAB_32_REG = 5,
+  UXTB_32_REG = 5
+};
+
+
+enum ThumbOpcode32Mode16 {
+  MLA_32 = 0,
+  MUL_32 = 0,
+  MLS_32 = 1
+};
+
+
+enum ThumbOpcode32Mode17 {
+  SMULL_32 = 0,
+  SDIV_32 = 1,
+  UMULL_32 = 2,
+  SMLAL_32 = 4,
+  UMLAL_32 = 6
+};
+
+
 // The bits for bit 7-4 for some type 0 miscellaneous instructions.
 enum MiscInstructionsBits74 {
   // With bits 22-21 01.
@@ -307,6 +460,23 @@ enum {
   B27 = 1 << 27,
   B28 = 1 << 28,
 
+  BH0 = 1 << 16,
+  BH1 = 1 << 17,
+  BH2 = 1 << 18,
+  BH3  = 1 << 19,
+  BH4  = 1 << 20,
+  BH5  = 1 << 21,
+  BH6  = 1 << 22,
+  BH7  = 1 << 23,
+  BH8  = 1 << 24,
+  BH9  = 1 << 25,
+  BH10 = 1 << 26,
+  BH11 = 1 << 27,
+  BH12 = 1 << 28,
+  BH13 = 1 << 29,
+  BH14 = 1 << 30,
+  BH15 = 1 << 31,
+
   // Instruction bit masks.
   kCondMask   = 15 << 28,
   kALUMask    = 0x6f << 21,