Code patching for ARM64.

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 122 matching lines @@
     } else {
       ASSERT((at == PreIndex) || (at == PostIndex));
       return Utils::IsInt(9, offset);
     }
   }
 
   // PC-relative load address.
   static Address PC(int32_t pc_off) {
     ASSERT(CanHoldOffset(pc_off, PCOffset));
     Address addr;
-    addr.encoding_ = (((pc_off >> 2) & kImm19Mask) << kImm19Shift);
+    addr.encoding_ = (((pc_off >> 2) << kImm19Shift) & kImm19Mask);
     addr.base_ = kNoRegister;
     addr.type_ = PCOffset;
     return addr;
   }
 
   // Base register rn with offset rm. rm is sign-extended according to ext.
   // If ext is UXTX, rm may be optionally scaled by the
   // Log2OperandSize (specified by the instruction).
   Address(Register rn, Register rm, Extend ext = UXTX, bool scaled = false) {
     ASSERT((rn != R31) && (rn != ZR));
@@ skipping 417 matching lines @@
   void neg(Register rd, Register rm) {
     sub(rd, ZR, Operand(rm));
   }
   void negs(Register rd, Register rm) {
     subs(rd, ZR, Operand(rm));
   }
   void mul(Register rd, Register rn, Register rm) {
     madd(rd, rn, rm, ZR);
   }
   void Push(Register reg) {
+    ASSERT(reg != PP);  // Only push PP with PushPP().
     str(reg, Address(SP, -1 * kWordSize, Address::PreIndex));
   }
   void Pop(Register reg) {
+    ASSERT(reg != PP);  // Only pop PP with PopPP().
     ldr(reg, Address(SP, 1 * kWordSize, Address::PostIndex));
   }
+  void PushPP() {
+    // Add the heap object tag back to PP before putting it on the stack.
+    add(PP, PP, Operand(kHeapObjectTag));
+    str(PP, Address(SP, -1 * kWordSize, Address::PreIndex));
+  }
+  void PopPP() {
+    ldr(PP, Address(SP, 1 * kWordSize, Address::PostIndex));
+    sub(PP, PP, Operand(kHeapObjectTag));
+  }
   void tst(Register rn, Operand o) {
     ands(ZR, rn, o);
   }
   void tsti(Register rn, uint64_t imm) {
     andis(ZR, rn, imm);
   }
 
+  // Branching to ExternalLabels.
+  void Branch(const ExternalLabel* label) {
+    LoadExternalLabel(TMP, label, kPatchable, PP);
+    br(TMP);
+  }
+
+  void BranchPatchable(const ExternalLabel* label) {
+    LoadPatchableImmediate(TMP, label->address());
+    br(TMP);
+  }
+
+  void BranchLink(const ExternalLabel* label, Register pp) {
+    if (Isolate::Current() == Dart::vm_isolate()) {
+      LoadImmediate(TMP, label->address(), kNoRegister);
+      blr(TMP);
+    } else {
+      LoadExternalLabel(TMP, label, kNotPatchable, pp);
+      blr(TMP);
+    }
+  }
+
+  void BranchLinkPatchable(const ExternalLabel* label) {
+    LoadExternalLabel(TMP, label, kPatchable, PP);
+    blr(TMP);
+  }
+
   // Object pool, loading from pool, etc.
   void LoadPoolPointer(Register pp) {
     const intptr_t object_pool_pc_dist =
       Instructions::HeaderSize() - Instructions::object_pool_offset() +
       CodeSize();
     // PP <- Read(PC - object_pool_pc_dist).
     ldr(pp, Address::PC(-object_pool_pc_dist));
+    // Remove tag so that offsets are aligned for loads from pp.
+    sub(pp, pp, Operand(kHeapObjectTag));

[zra, 2014/04/17 21:27:27]

When in the PP register, the object pool pointer is untagged. When I push it on
the stack with PushPP I tag it again. PopPP then untags when restoring from the
stack. This will make loading from the object pool only one instruction for the
first 4096 entries. Otherwise, becuase the offset wouldn't be aligned, it would
always be at least two instructions.

[regis, 2014/04/17 21:42:28]

Sounds good. How about you merge most of this comment into the comment on line
637?

[zra, 2014/04/17 21:56:32]

Done.

   }
 
   enum Patchability {
     kPatchable,
     kNotPatchable,
   };
 
   void LoadWordFromPoolOffset(Register dst, Register pp, uint32_t offset);
+  intptr_t FindExternalLabel(const ExternalLabel* label,
+                             Patchability patchable);
   intptr_t FindObject(const Object& obj, Patchability patchable);
   intptr_t FindImmediate(int64_t imm);
   bool CanLoadObjectFromPool(const Object& object);
   bool CanLoadImmediateFromPool(int64_t imm, Register pp);
+  void LoadExternalLabel(Register dst, const ExternalLabel* label,
+                         Patchability patchable, Register pp);
   void LoadObject(Register dst, const Object& obj, Register pp);
+  void LoadDecodableImmediate(Register reg, int64_t imm, Register pp);
+  void LoadPatchableImmediate(Register reg, int64_t imm);
   void LoadImmediate(Register reg, int64_t imm, Register pp);
 
  private:
   AssemblerBuffer buffer_;  // Contains position independent code.
 
   // Objects and patchable jump targets.
   GrowableObjectArray& object_pool_;
 
   // Patchability of pool entries.
   GrowableArray<Patchability> patchable_pool_entries_;
@@ skipping 136 matching lines @@
     const int32_t encoding =
         op | size | s |
         (static_cast<int32_t>(rd) << kRdShift) |
         (static_cast<int32_t>(rn) << kRnShift) |
         o.encoding();
     Emit(encoding);
   }
 
   int32_t EncodeImm19BranchOffset(int64_t imm, int32_t instr) {
     const int32_t imm32 = static_cast<int32_t>(imm);
-    const int32_t off = (((imm32 >> 2) & kImm19Mask) << kImm19Shift);
-    return (instr & ~(kImm19Mask << kImm19Shift)) | off;
+    const int32_t off = (((imm32 >> 2) << kImm19Shift) & kImm19Mask);
+    return (instr & ~kImm19Mask) | off;
   }
 
   int64_t DecodeImm19BranchOffset(int32_t instr) {
     const int32_t off = (((instr >> kImm19Shift) & kImm19Shift) << 13) >> 13;
     return static_cast<int64_t>(off);
   }
 
   void EmitCompareAndBranch(CompareAndBranchOp op, Register rt, int64_t imm,
                             OperandSize sz) {
     ASSERT((sz == kDoubleWord) || (sz == kWord));
     ASSERT(Utils::IsInt(21, imm) && ((imm & 0x3) == 0));
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t encoded_offset = EncodeImm19BranchOffset(imm, 0);
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(rt) << kRtShift) |
         encoded_offset;
     Emit(encoding);
   }
 
   void EmitConditionalBranch(ConditionalBranchOp op, Condition cond,
                              int64_t imm) {
     ASSERT(Utils::IsInt(21, imm) && ((imm & 0x3) == 0));
     const int32_t encoding =
         op |
         (static_cast<int32_t>(cond) << kCondShift) |
-        (((imm >> 2) & kImm19Mask) << kImm19Shift);
+        (((imm >> 2) << kImm19Shift) & kImm19Mask);
     Emit(encoding);
   }
 
   bool CanEncodeImm19BranchOffset(int64_t offset) {
     ASSERT(Utils::IsAligned(offset, 4));
     return Utils::IsInt(19, offset);
   }
 
   // TODO(zra): Implement far branches. Requires loading large immediates.
   void EmitBranch(ConditionalBranchOp op, Condition cond, Label* label) {
@@ skipping 53 matching lines @@
         (static_cast<int32_t>(rt) << kRtShift) |
         a.encoding();
     Emit(encoding);
   }
 
   void EmitPCRelOp(PCRelOp op, Register rd, int64_t imm) {
     ASSERT(Utils::IsInt(21, imm));
     ASSERT((rd != R31) && (rd != SP));
     const Register crd = ConcreteRegister(rd);
     const int32_t loimm = (imm & 0x3) << 29;
-    const int32_t hiimm = ((imm >> 2) & kImm19Mask) << kImm19Shift;
+    const int32_t hiimm = ((imm >> 2) << kImm19Shift) & kImm19Mask;
     const int32_t encoding =
         op | loimm | hiimm |
         (static_cast<int32_t>(crd) << kRdShift);
     Emit(encoding);
   }
 
   void EmitMiscDP2Source(MiscDP2SourceOp op,
                          Register rd, Register rn, Register rm,
                          OperandSize sz) {
     ASSERT((rd != SP) && (rn != SP) && (rm != SP));
@@ skipping 27 matching lines @@
     Emit(encoding);
   }
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_