| OLD | NEW |
|---|
| 1 ; This file tests support for the select instruction with vector valued inputs. | 1 ; This file tests support for the select instruction with vector valued inputs. |
| 2 | 2 |
| 3 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ | 3 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ |
| 4 ; RUN: | FileCheck %s | 4 ; RUN: | FileCheck %s |
| 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \ | 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \ |
| 6 ; RUN: | FileCheck %s | 6 ; RUN: | FileCheck %s |
| 7 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -mattr=sse4.1 \ | 7 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -mattr=sse4.1 \ |
| 8 ; RUN: | FileCheck --check-prefix=SSE41 %s | 8 ; RUN: | FileCheck --check-prefix=SSE41 %s |
| 9 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \ | 9 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \ |
| 10 ; RUN: | FileCheck --check-prefix=SSE41 %s | 10 ; RUN: | FileCheck --check-prefix=SSE41 %s |
| 11 | 11 |
| 12 ; RUN: %if --need=target_MIPS32 --need=allow_dump \ |
| 13 ; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\ |
| 14 ; RUN: -i %s --args -O2 --skip-unimplemented \ |
| 15 ; RUN: | %if --need=target_MIPS32 --need=allow_dump \ |
| 16 ; RUN: --command FileCheck --check-prefix MIPS32 %s |
| 17 |
| 12 define internal <16 x i8> @test_select_v16i8(<16 x i1> %cond, <16 x i8> %arg1, | 18 define internal <16 x i8> @test_select_v16i8(<16 x i1> %cond, <16 x i8> %arg1, |
| 13 <16 x i8> %arg2) { | 19 <16 x i8> %arg2) { |
| 14 entry: | 20 entry: |
| 15 %res = select <16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2 | 21 %res = select <16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2 |
| 16 ret <16 x i8> %res | 22 ret <16 x i8> %res |
| 17 ; CHECK-LABEL: test_select_v16i8 | 23 ; CHECK-LABEL: test_select_v16i8 |
| 18 ; CHECK: pand | 24 ; CHECK: pand |
| 19 ; CHECK: pandn | 25 ; CHECK: pandn |
| 20 ; CHECK: por | 26 ; CHECK: por |
| 21 | 27 |
| 22 ; SSE41-LABEL: test_select_v16i8 | 28 ; SSE41-LABEL: test_select_v16i8 |
| 23 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 29 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
| 30 |
| 31 ; MIPS32-LABEL: test_select_v16i8 |
| 32 ; MIPS32: lw [[T0:.*]],36(sp) |
| 33 ; MIPS32: lw [[T1:.*]],40(sp) |
| 34 ; MIPS32: lw [[T2:.*]],44(sp) |
| 35 ; MIPS32: lw [[T3:.*]],48(sp) |
| 36 ; MIPS32: lw [[T4:.*]],52(sp) |
| 37 ; MIPS32: lw [[T5:.*]],56(sp) |
| 38 ; MIPS32: lw [[T6:.*]],60(sp) |
| 39 ; MIPS32: lw [[T7:.*]],64(sp) |
| 40 ; MIPS32: move [[T8:.*]],zero |
| 41 ; MIPS32: move [[T9:.*]],zero |
| 42 ; MIPS32: move [[T10:.*]],zero |
| 43 ; MIPS32: move [[T11:.*]],zero |
| 44 ; MIPS32: andi [[T12:.*]],a0,0xff |
| 45 ; MIPS32: andi [[T12]],[[T12]],0x1 |
| 46 ; MIPS32: andi [[T13:.*]],[[T0]],0xff |
| 47 ; MIPS32: andi [[T14:.*]],[[T4]],0xff |
| 48 ; MIPS32: movn [[T14]],[[T13]],[[T12]] |
| 49 ; MIPS32: andi [[T14]],[[T14]],0xff |
| 50 ; MIPS32: srl [[T8]],[[T8]],0x8 |
| 51 ; MIPS32: sll [[T8]],[[T8]],0x8 |
| 52 ; MIPS32: or [[T14]],[[T14]],[[T8]] |
| 53 ; MIPS32: srl [[T8]],a0,0x8 |
| 54 ; MIPS32: andi [[T8]],[[T8]],0xff |
| 55 ; MIPS32: andi [[T8]],[[T8]],0x1 |
| 56 ; MIPS32: srl [[T12]],[[T0]],0x8 |
| 57 ; MIPS32: andi [[T12]],[[T12]],0xff |
| 58 ; MIPS32: srl [[T13]],[[T4]],0x8 |
| 59 ; MIPS32: andi [[T13]],[[T13]],0xff |
| 60 ; MIPS32: movn [[T13]],[[T12]],[[T8]] |
| 61 ; MIPS32: andi [[T13]],[[T13]],0xff |
| 62 ; MIPS32: sll [[T13]],[[T13]],0x8 |
| 63 ; MIPS32: lui [[T8]],0xffff |
| 64 ; MIPS32: ori [[T8]],[[T8]],0xff |
| 65 ; MIPS32: and [[T14]],[[T14]],[[T8]] |
| 66 ; MIPS32: or [[T13]],[[T13]],[[T14]] |
| 67 ; MIPS32: srl [[T8]],a0,0x10 |
| 68 ; MIPS32: andi [[T8]],[[T8]],0xff |
| 69 ; MIPS32: andi [[T8]],[[T8]],0x1 |
| 70 ; MIPS32: srl [[T12]],[[T0]],0x10 |
| 71 ; MIPS32: andi [[T12]],[[T12]],0xff |
| 72 ; MIPS32: srl [[T14]],[[T4]],0x10 |
| 73 ; MIPS32: andi [[T14]],[[T14]],0xff |
| 74 ; MIPS32: movn [[T14]],[[T12]],[[T8]] |
| 75 ; MIPS32: andi [[T14]],[[T14]],0xff |
| 76 ; MIPS32: sll [[T14]],[[T14]],0x10 |
| 77 ; MIPS32: lui [[T8]],0xff00 |
| 78 ; MIPS32: ori [[T8]],[[T8]],0xffff |
| 79 ; MIPS32: and [[T13]],[[T13]],[[T8]] |
| 80 ; MIPS32: or [[T14]],[[T14]],[[T13]] |
| 81 ; MIPS32: srl [[T15:.*]],a0,0x18 |
| 82 ; MIPS32: andi [[T15]],[[T15]],0x1 |
| 83 ; MIPS32: srl [[T0]],[[T0]],0x18 |
| 84 ; MIPS32: srl [[T4]],[[T4]],0x18 |
| 85 ; MIPS32: movn [[T4]],[[T0]],[[T15]] |
| 86 ; MIPS32: srl [[T4]],[[T4]],0x18 |
| 87 ; MIPS32: sll [[T14]],[[T14]],0x8 |
| 88 ; MIPS32: srl [[T14]],[[T14]],0x8 |
| 89 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]] |
| 90 ; MIPS32: andi [[T0]],a1,0xff |
| 91 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 92 ; MIPS32: andi [[T15]],[[T1]],0xff |
| 93 ; MIPS32: andi [[T8]],[[T5]],0xff |
| 94 ; MIPS32: movn [[T8]],[[T15]],[[T0]] |
| 95 ; MIPS32: andi [[T8]],[[T8]],0xff |
| 96 ; MIPS32: srl [[T9]],[[T9]],0x8 |
| 97 ; MIPS32: sll [[T9]],[[T9]],0x8 |
| 98 ; MIPS32: or [[T8]],[[T8]],[[T9]] |
| 99 ; MIPS32: srl [[T0]],a1,0x8 |
| 100 ; MIPS32: andi [[T0]],[[T0]],0xff |
| 101 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 102 ; MIPS32: srl [[T15]],[[T1]],0x8 |
| 103 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 104 ; MIPS32: srl [[T9]],[[T5]],0x8 |
| 105 ; MIPS32: andi [[T9]],[[T9]],0xff |
| 106 ; MIPS32: movn [[T9]],[[T15]],[[T0]] |
| 107 ; MIPS32: andi [[T9]],[[T9]],0xff |
| 108 ; MIPS32: sll [[T9]],[[T9]],0x8 |
| 109 ; MIPS32: lui [[T0]],0xffff |
| 110 ; MIPS32: ori [[T0]],[[T0]],0xff |
| 111 ; MIPS32: and [[T8]],[[T8]],[[T0]] |
| 112 ; MIPS32: or [[T9]],[[T9]],[[T8]] |
| 113 ; MIPS32: srl [[T0]],a1,0x10 |
| 114 ; MIPS32: andi [[T0]],[[T0]],0xff |
| 115 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 116 ; MIPS32: srl [[T15]],[[T1]],0x10 |
| 117 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 118 ; MIPS32: srl [[T8]],[[T5]],0x10 |
| 119 ; MIPS32: andi [[T8]],[[T8]],0xff |
| 120 ; MIPS32: movn [[T8]],[[T15]],[[T0]] |
| 121 ; MIPS32: andi [[T8]],[[T8]],0xff |
| 122 ; MIPS32: sll [[T8]],[[T8]],0x10 |
| 123 ; MIPS32: lui [[T0]],0xff00 |
| 124 ; MIPS32: ori [[T0]],[[T0]],0xffff |
| 125 ; MIPS32: and [[T9]],[[T9]],[[T0]] |
| 126 ; MIPS32: or [[T8]],[[T8]],[[T9]] |
| 127 ; MIPS32: srl [[T16:.*]],a1,0x18 |
| 128 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 129 ; MIPS32: srl [[T1]],[[T1]],0x18 |
| 130 ; MIPS32: srl [[T5]],[[T5]],0x18 |
| 131 ; MIPS32: movn [[T5]],[[T1]],[[T16]] |
| 132 ; MIPS32: srl [[T5]],[[T5]],0x18 |
| 133 ; MIPS32: sll [[T8]],[[T8]],0x8 |
| 134 ; MIPS32: srl [[T8]],[[T8]],0x8 |
| 135 ; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]] |
| 136 ; MIPS32: andi [[T0]],a2,0xff |
| 137 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 138 ; MIPS32: andi [[T1]],[[T2]],0xff |
| 139 ; MIPS32: andi [[T15]],[[T6]],0xff |
| 140 ; MIPS32: movn [[T15]],[[T1]],[[T0]] |
| 141 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 142 ; MIPS32: srl [[T10]],[[T10]],0x8 |
| 143 ; MIPS32: sll [[T10]],[[T10]],0x8 |
| 144 ; MIPS32: or [[T15]],[[T15]],[[T10]] |
| 145 ; MIPS32: srl [[T0]],a2,0x8 |
| 146 ; MIPS32: andi [[T0]],[[T0]],0xff |
| 147 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 148 ; MIPS32: srl [[T1]],[[T2]],0x8 |
| 149 ; MIPS32: andi [[T1]],[[T1]],0xff |
| 150 ; MIPS32: srl [[T16]],[[T6]],0x8 |
| 151 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 152 ; MIPS32: movn [[T16]],[[T1]],[[T0]] |
| 153 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 154 ; MIPS32: sll [[T16]],[[T16]],0x8 |
| 155 ; MIPS32: lui [[T0]],0xffff |
| 156 ; MIPS32: ori [[T0]],[[T0]],0xff |
| 157 ; MIPS32: and [[T15]],[[T15]],[[T0]] |
| 158 ; MIPS32: or [[T16]],[[T16]],[[T15]] |
| 159 ; MIPS32: srl [[T0]],a2,0x10 |
| 160 ; MIPS32: andi [[T0]],[[T0]],0xff |
| 161 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 162 ; MIPS32: srl [[T1]],[[T2]],0x10 |
| 163 ; MIPS32: andi [[T1]],[[T1]],0xff |
| 164 ; MIPS32: srl [[T15]],[[T6]],0x10 |
| 165 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 166 ; MIPS32: movn [[T15]],[[T1]],[[T0]] |
| 167 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 168 ; MIPS32: sll [[T15]],[[T15]],0x10 |
| 169 ; MIPS32: lui [[T0]],0xff00 |
| 170 ; MIPS32: ori [[T0]],[[T0]],0xffff |
| 171 ; MIPS32: and [[T16]],[[T16]],[[T0]] |
| 172 ; MIPS32: or [[T15]],[[T15]],[[T16]] |
| 173 ; MIPS32: srl [[T17:.*]],a2,0x18 |
| 174 ; MIPS32: andi [[T17]],[[T17]],0x1 |
| 175 ; MIPS32: srl [[T2]],[[T2]],0x18 |
| 176 ; MIPS32: srl [[T6]],[[T6]],0x18 |
| 177 ; MIPS32: movn [[T6]],[[T2]],[[T17]] |
| 178 ; MIPS32: srl [[T6]],[[T6]],0x18 |
| 179 ; MIPS32: sll [[T15]],[[T15]],0x8 |
| 180 ; MIPS32: srl [[T15]],[[T15]],0x8 |
| 181 ; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]] |
| 182 ; MIPS32: andi [[T0]],a3,0xff |
| 183 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 184 ; MIPS32: andi [[T1]],[[T3]],0xff |
| 185 ; MIPS32: andi [[T15]],[[T7]],0xff |
| 186 ; MIPS32: movn [[T15]],[[T1]],[[T0]] |
| 187 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 188 ; MIPS32: srl [[T11]],[[T11]],0x8 |
| 189 ; MIPS32: sll [[T11]],[[T11]],0x8 |
| 190 ; MIPS32: or [[T15]],[[T15]],[[T11]] |
| 191 ; MIPS32: srl [[T0]],a3,0x8 |
| 192 ; MIPS32: andi [[T0]],[[T0]],0xff |
| 193 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 194 ; MIPS32: srl [[T1]],[[T3]],0x8 |
| 195 ; MIPS32: andi [[T1]],[[T1]],0xff |
| 196 ; MIPS32: srl [[T16]],[[T7]],0x8 |
| 197 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 198 ; MIPS32: movn [[T16]],[[T1]],[[T0]] |
| 199 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 200 ; MIPS32: sll [[T16]],[[T16]],0x8 |
| 201 ; MIPS32: lui [[T0]],0xffff |
| 202 ; MIPS32: ori [[T0]],[[T0]],0xff |
| 203 ; MIPS32: and [[T15]],[[T15]],[[T0]] |
| 204 ; MIPS32: or [[T16]],[[T16]],[[T15]] |
| 205 ; MIPS32: srl [[T0]],a3,0x10 |
| 206 ; MIPS32: andi [[T0]],[[T0]],0xff |
| 207 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 208 ; MIPS32: srl [[T1]],[[T3]],0x10 |
| 209 ; MIPS32: andi [[T1]],[[T1]],0xff |
| 210 ; MIPS32: srl [[T15]],[[T7]],0x10 |
| 211 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 212 ; MIPS32: movn [[T15]],[[T1]],[[T0]] |
| 213 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 214 ; MIPS32: sll [[T15]],[[T15]],0x10 |
| 215 ; MIPS32: lui [[T0]],0xff00 |
| 216 ; MIPS32: ori [[T0]],[[T0]],0xffff |
| 217 ; MIPS32: and [[T16]],[[T16]],[[T0]] |
| 218 ; MIPS32: or [[T15]],[[T15]],[[T16]] |
| 219 ; MIPS32: srl [[T18:.*]],a3,0x18 |
| 220 ; MIPS32: andi [[T18]],[[T18]],0x1 |
| 221 ; MIPS32: srl [[T3]],[[T3]],0x18 |
| 222 ; MIPS32: srl [[T7]],[[T7]],0x18 |
| 223 ; MIPS32: movn [[T7]],[[T3]],[[T18]] |
| 224 ; MIPS32: srl [[T7]],[[T7]],0x18 |
| 225 ; MIPS32: sll [[T15]],[[T15]],0x8 |
| 226 ; MIPS32: srl [[T15]],[[T15]],0x8 |
| 227 ; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]] |
| 24 } | 228 } |
| 25 | 229 |
| 26 define internal <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1, | 230 define internal <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1, |
| 27 <16 x i1> %arg2) { | 231 <16 x i1> %arg2) { |
| 28 entry: | 232 entry: |
| 29 %res = select <16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2 | 233 %res = select <16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2 |
| 30 ret <16 x i1> %res | 234 ret <16 x i1> %res |
| 31 ; CHECK-LABEL: test_select_v16i1 | 235 ; CHECK-LABEL: test_select_v16i1 |
| 32 ; CHECK: pand | 236 ; CHECK: pand |
| 33 ; CHECK: pandn | 237 ; CHECK: pandn |
| 34 ; CHECK: por | 238 ; CHECK: por |
| 35 | 239 |
| 36 ; SSE41-LABEL: test_select_v16i1 | 240 ; SSE41-LABEL: test_select_v16i1 |
| 37 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 241 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
| 242 |
| 243 ; MIPS32-LABEL: test_select_v16i1 |
| 244 ; MIPS32: lw [[T0:.*]],36(sp) |
| 245 ; MIPS32: lw [[T1:.*]],40(sp) |
| 246 ; MIPS32: lw [[T2:.*]],44(sp) |
| 247 ; MIPS32: lw [[T3:.*]],48(sp) |
| 248 ; MIPS32: lw [[T4:.*]],52(sp) |
| 249 ; MIPS32: lw [[T5:.*]],56(sp) |
| 250 ; MIPS32: lw [[T6:.*]],60(sp) |
| 251 ; MIPS32: lw [[T7:.*]],64(sp) |
| 252 ; MIPS32: move [[T8:.*]],zero |
| 253 ; MIPS32: move [[T9:.*]],zero |
| 254 ; MIPS32: move [[T10:.*]],zero |
| 255 ; MIPS32: move [[T11:.*]],zero |
| 256 ; MIPS32: andi [[T12:.*]],a0,0xff |
| 257 ; MIPS32: andi [[T12]],[[T12]],0x1 |
| 258 ; MIPS32: andi [[T13:.*]],[[T0]],0xff |
| 259 ; MIPS32: andi [[T13]],[[T13]],0x1 |
| 260 ; MIPS32: andi [[T14:.*]],[[T4]],0xff |
| 261 ; MIPS32: andi [[T14]],[[T14]],0x1 |
| 262 ; MIPS32: movn [[T14]],[[T13]],[[T12]] |
| 263 ; MIPS32: andi [[T14]],[[T14]],0xff |
| 264 ; MIPS32: srl [[T8]],[[T8]],0x8 |
| 265 ; MIPS32: sll [[T8]],[[T8]],0x8 |
| 266 ; MIPS32: or [[T14]],[[T14]],[[T8]] |
| 267 ; MIPS32: srl [[T8]],a0,0x8 |
| 268 ; MIPS32: andi [[T8]],[[T8]],0xff |
| 269 ; MIPS32: andi [[T8]],[[T8]],0x1 |
| 270 ; MIPS32: srl [[T12]],[[T0]],0x8 |
| 271 ; MIPS32: andi [[T12]],[[T12]],0xff |
| 272 ; MIPS32: andi [[T12]],[[T12]],0x1 |
| 273 ; MIPS32: srl [[T13]],[[T4]],0x8 |
| 274 ; MIPS32: andi [[T13]],[[T13]],0xff |
| 275 ; MIPS32: andi [[T13]],[[T13]],0x1 |
| 276 ; MIPS32: movn [[T13]],[[T12]],[[T8]] |
| 277 ; MIPS32: andi [[T13]],[[T13]],0xff |
| 278 ; MIPS32: sll [[T13]],[[T13]],0x8 |
| 279 ; MIPS32: lui [[T8]],0xffff |
| 280 ; MIPS32: ori [[T8]],[[T8]],0xff |
| 281 ; MIPS32: and [[T14]],[[T14]],[[T8]] |
| 282 ; MIPS32: or [[T13]],[[T13]],[[T14]] |
| 283 ; MIPS32: srl [[T8]],a0,0x10 |
| 284 ; MIPS32: andi [[T8]],[[T8]],0xff |
| 285 ; MIPS32: andi [[T8]],[[T8]],0x1 |
| 286 ; MIPS32: srl [[T12]],[[T0]],0x10 |
| 287 ; MIPS32: andi [[T12]],[[T12]],0xff |
| 288 ; MIPS32: andi [[T12]],[[T12]],0x1 |
| 289 ; MIPS32: srl [[T14]],[[T4]],0x10 |
| 290 ; MIPS32: andi [[T14]],[[T14]],0xff |
| 291 ; MIPS32: andi [[T14]],[[T14]],0x1 |
| 292 ; MIPS32: movn [[T14]],[[T12]],[[T8]] |
| 293 ; MIPS32: andi [[T14]],[[T14]],0xff |
| 294 ; MIPS32: sll [[T14]],[[T14]],0x10 |
| 295 ; MIPS32: lui [[T8]],0xff00 |
| 296 ; MIPS32: ori [[T8]],[[T8]],0xffff |
| 297 ; MIPS32: and [[T13]],[[T13]],[[T8]] |
| 298 ; MIPS32: or [[T14]],[[T14]],[[T13]] |
| 299 ; MIPS32: srl [[T15:.*]],a0,0x18 |
| 300 ; MIPS32: andi [[T15]],[[T15]],0x1 |
| 301 ; MIPS32: srl [[T0]],[[T0]],0x18 |
| 302 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 303 ; MIPS32: srl [[T4]],[[T4]],0x18 |
| 304 ; MIPS32: andi [[T4]],[[T4]],0x1 |
| 305 ; MIPS32: movn [[T4]],[[T0]],[[T15]] |
| 306 ; MIPS32: srl [[T4]],[[T4]],0x18 |
| 307 ; MIPS32: sll [[T14]],[[T14]],0x8 |
| 308 ; MIPS32: srl [[T14]],[[T14]],0x8 |
| 309 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]] |
| 310 ; MIPS32: andi [[T0]],a1,0xff |
| 311 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 312 ; MIPS32: andi [[T15]],[[T1]],0xff |
| 313 ; MIPS32: andi [[T15]],[[T15]],0x1 |
| 314 ; MIPS32: andi [[T8]],[[T5]],0xff |
| 315 ; MIPS32: andi [[T8]],[[T8]],0x1 |
| 316 ; MIPS32: movn [[T8]],[[T15]],[[T0]] |
| 317 ; MIPS32: andi [[T8]],[[T8]],0xff |
| 318 ; MIPS32: srl [[T9]],[[T9]],0x8 |
| 319 ; MIPS32: sll [[T9]],[[T9]],0x8 |
| 320 ; MIPS32: or [[T8]],[[T8]],[[T9]] |
| 321 ; MIPS32: srl [[T0]],a1,0x8 |
| 322 ; MIPS32: andi [[T0]],[[T0]],0xff |
| 323 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 324 ; MIPS32: srl [[T15]],[[T1]],0x8 |
| 325 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 326 ; MIPS32: andi [[T15]],[[T15]],0x1 |
| 327 ; MIPS32: srl [[T9]],[[T5]],0x8 |
| 328 ; MIPS32: andi [[T9]],[[T9]],0xff |
| 329 ; MIPS32: andi [[T9]],[[T9]],0x1 |
| 330 ; MIPS32: movn [[T9]],[[T15]],[[T0]] |
| 331 ; MIPS32: andi [[T9]],[[T9]],0xff |
| 332 ; MIPS32: sll [[T9]],[[T9]],0x8 |
| 333 ; MIPS32: lui [[T0]],0xffff |
| 334 ; MIPS32: ori [[T0]],[[T0]],0xff |
| 335 ; MIPS32: and [[T8]],[[T8]],[[T0]] |
| 336 ; MIPS32: or [[T9]],[[T9]],[[T8]] |
| 337 ; MIPS32: srl [[T0]],a1,0x10 |
| 338 ; MIPS32: andi [[T0]],[[T0]],0xff |
| 339 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 340 ; MIPS32: srl [[T15]],[[T1]],0x10 |
| 341 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 342 ; MIPS32: andi [[T15]],[[T15]],0x1 |
| 343 ; MIPS32: srl [[T8]],[[T5]],0x10 |
| 344 ; MIPS32: andi [[T8]],[[T8]],0xff |
| 345 ; MIPS32: andi [[T8]],[[T8]],0x1 |
| 346 ; MIPS32: movn [[T8]],[[T15]],[[T0]] |
| 347 ; MIPS32: andi [[T8]],[[T8]],0xff |
| 348 ; MIPS32: sll [[T8]],[[T8]],0x10 |
| 349 ; MIPS32: lui [[T0]],0xff00 |
| 350 ; MIPS32: ori [[T0]],[[T0]],0xffff |
| 351 ; MIPS32: and [[T9]],[[T9]],[[T0]] |
| 352 ; MIPS32: or [[T8]],[[T8]],[[T9]] |
| 353 ; MIPS32: srl [[T16:.*]],a1,0x18 |
| 354 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 355 ; MIPS32: srl [[T1]],[[T1]],0x18 |
| 356 ; MIPS32: andi [[T1]],[[T1]],0x1 |
| 357 ; MIPS32: srl [[T5]],[[T5]],0x18 |
| 358 ; MIPS32: andi [[T5]],[[T5]],0x1 |
| 359 ; MIPS32: movn [[T5]],[[T1]],[[T16]] |
| 360 ; MIPS32: srl [[T5]],[[T5]],0x18 |
| 361 ; MIPS32: sll [[T8]],[[T8]],0x8 |
| 362 ; MIPS32: srl [[T8]],[[T8]],0x8 |
| 363 ; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]] |
| 364 ; MIPS32: andi [[T0]],a2,0xff |
| 365 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 366 ; MIPS32: andi [[T1]],[[T2]],0xff |
| 367 ; MIPS32: andi [[T1]],[[T1]],0x1 |
| 368 ; MIPS32: andi [[T15]],[[T6]],0xff |
| 369 ; MIPS32: andi [[T15]],[[T15]],0x1 |
| 370 ; MIPS32: movn [[T15]],[[T1]],[[T0]] |
| 371 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 372 ; MIPS32: srl [[T10]],[[T10]],0x8 |
| 373 ; MIPS32: sll [[T10]],[[T10]],0x8 |
| 374 ; MIPS32: or [[T15]],[[T15]],[[T10]] |
| 375 ; MIPS32: srl [[T0]],a2,0x8 |
| 376 ; MIPS32: andi [[T0]],[[T0]],0xff |
| 377 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 378 ; MIPS32: srl [[T1]],[[T2]],0x8 |
| 379 ; MIPS32: andi [[T1]],[[T1]],0xff |
| 380 ; MIPS32: andi [[T1]],[[T1]],0x1 |
| 381 ; MIPS32: srl [[T16]],[[T6]],0x8 |
| 382 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 383 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 384 ; MIPS32: movn [[T16]],[[T1]],[[T0]] |
| 385 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 386 ; MIPS32: sll [[T16]],[[T16]],0x8 |
| 387 ; MIPS32: lui [[T0]],0xffff |
| 388 ; MIPS32: ori [[T0]],[[T0]],0xff |
| 389 ; MIPS32: and [[T15]],[[T15]],[[T0]] |
| 390 ; MIPS32: or [[T16]],[[T16]],[[T15]] |
| 391 ; MIPS32: srl [[T0]],a2,0x10 |
| 392 ; MIPS32: andi [[T0]],[[T0]],0xff |
| 393 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 394 ; MIPS32: srl [[T1]],[[T2]],0x10 |
| 395 ; MIPS32: andi [[T1]],[[T1]],0xff |
| 396 ; MIPS32: andi [[T1]],[[T1]],0x1 |
| 397 ; MIPS32: srl [[T15]],[[T6]],0x10 |
| 398 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 399 ; MIPS32: andi [[T15]],[[T15]],0x1 |
| 400 ; MIPS32: movn [[T15]],[[T1]],[[T0]] |
| 401 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 402 ; MIPS32: sll [[T15]],[[T15]],0x10 |
| 403 ; MIPS32: lui [[T0]],0xff00 |
| 404 ; MIPS32: ori [[T0]],[[T0]],0xffff |
| 405 ; MIPS32: and [[T16]],[[T16]],[[T0]] |
| 406 ; MIPS32: or [[T15]],[[T15]],[[T16]] |
| 407 ; MIPS32: srl [[T17:.*]],a2,0x18 |
| 408 ; MIPS32: andi [[T17]],[[T17]],0x1 |
| 409 ; MIPS32: srl [[T2]],[[T2]],0x18 |
| 410 ; MIPS32: andi [[T2]],[[T2]],0x1 |
| 411 ; MIPS32: srl [[T6]],[[T6]],0x18 |
| 412 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 413 ; MIPS32: movn [[T6]],[[T2]],[[T17]] |
| 414 ; MIPS32: srl [[T6]],[[T6]],0x18 |
| 415 ; MIPS32: sll [[T15]],[[T15]],0x8 |
| 416 ; MIPS32: srl [[T15]],[[T15]],0x8 |
| 417 ; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]] |
| 418 ; MIPS32: andi [[T0]],a3,0xff |
| 419 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 420 ; MIPS32: andi [[T1]],[[T3]],0xff |
| 421 ; MIPS32: andi [[T1]],[[T1]],0x1 |
| 422 ; MIPS32: andi [[T15]],[[T7]],0xff |
| 423 ; MIPS32: andi [[T15]],[[T15]],0x1 |
| 424 ; MIPS32: movn [[T15]],[[T1]],[[T0]] |
| 425 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 426 ; MIPS32: srl [[T11]],[[T11]],0x8 |
| 427 ; MIPS32: sll [[T11]],[[T11]],0x8 |
| 428 ; MIPS32: or [[T15]],[[T15]],[[T11]] |
| 429 ; MIPS32: srl [[T0]],a3,0x8 |
| 430 ; MIPS32: andi [[T0]],[[T0]],0xff |
| 431 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 432 ; MIPS32: srl [[T1]],[[T3]],0x8 |
| 433 ; MIPS32: andi [[T1]],[[T1]],0xff |
| 434 ; MIPS32: andi [[T1]],[[T1]],0x1 |
| 435 ; MIPS32: srl [[T16]],[[T7]],0x8 |
| 436 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 437 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 438 ; MIPS32: movn [[T16]],[[T1]],[[T0]] |
| 439 ; MIPS32: andi [[T16]],[[T16]],0xff |
| 440 ; MIPS32: sll [[T16]],[[T16]],0x8 |
| 441 ; MIPS32: lui [[T0]],0xffff |
| 442 ; MIPS32: ori [[T0]],[[T0]],0xff |
| 443 ; MIPS32: and [[T15]],[[T15]],[[T0]] |
| 444 ; MIPS32: or [[T16]],[[T16]],[[T15]] |
| 445 ; MIPS32: srl [[T0]],a3,0x10 |
| 446 ; MIPS32: andi [[T0]],[[T0]],0xff |
| 447 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 448 ; MIPS32: srl [[T1]],[[T3]],0x10 |
| 449 ; MIPS32: andi [[T1]],[[T1]],0xff |
| 450 ; MIPS32: andi [[T1]],[[T1]],0x1 |
| 451 ; MIPS32: srl [[T15]],[[T7]],0x10 |
| 452 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 453 ; MIPS32: andi [[T15]],[[T15]],0x1 |
| 454 ; MIPS32: movn [[T15]],[[T1]],[[T0]] |
| 455 ; MIPS32: andi [[T15]],[[T15]],0xff |
| 456 ; MIPS32: sll [[T15]],[[T15]],0x10 |
| 457 ; MIPS32: lui [[T0]],0xff00 |
| 458 ; MIPS32: ori [[T0]],[[T0]],0xffff |
| 459 ; MIPS32: and [[T16]],[[T16]],[[T0]] |
| 460 ; MIPS32: or [[T15]],[[T15]],[[T16]] |
| 461 ; MIPS32: srl [[T18:.*]],a3,0x18 |
| 462 ; MIPS32: andi [[T18]],[[T18]],0x1 |
| 463 ; MIPS32: srl [[T3]],[[T3]],0x18 |
| 464 ; MIPS32: andi [[T3]],[[T3]],0x1 |
| 465 ; MIPS32: srl [[T7]],[[T7]],0x18 |
| 466 ; MIPS32: andi [[T7]],[[T7]],0x1 |
| 467 ; MIPS32: movn [[T7]],[[T3]],[[T18]] |
| 468 ; MIPS32: srl [[T7]],[[T7]],0x18 |
| 469 ; MIPS32: sll [[T15]],[[T15]],0x8 |
| 470 ; MIPS32: srl [[T15]],[[T15]],0x8 |
| 471 ; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]] |
| 38 } | 472 } |
| 39 | 473 |
| 40 define internal <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1, | 474 define internal <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1, |
| 41 <8 x i16> %arg2) { | 475 <8 x i16> %arg2) { |
| 42 entry: | 476 entry: |
| 43 %res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2 | 477 %res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2 |
| 44 ret <8 x i16> %res | 478 ret <8 x i16> %res |
| 45 ; CHECK-LABEL: test_select_v8i16 | 479 ; CHECK-LABEL: test_select_v8i16 |
| 46 ; CHECK: pand | 480 ; CHECK: pand |
| 47 ; CHECK: pandn | 481 ; CHECK: pandn |
| 48 ; CHECK: por | 482 ; CHECK: por |
| 49 | 483 |
| 50 ; SSE41-LABEL: test_select_v8i16 | 484 ; SSE41-LABEL: test_select_v8i16 |
| 51 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 485 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
| 486 |
| 487 ; MIPS32-LABEL: test_select_v8i16 |
| 488 ; MIPS32: lw [[T0:.*]],36(sp) |
| 489 ; MIPS32: lw [[T1:.*]],40(sp) |
| 490 ; MIPS32: lw [[T2:.*]],44(sp) |
| 491 ; MIPS32: lw [[T3:.*]],48(sp) |
| 492 ; MIPS32: lw [[T4:.*]],52(sp) |
| 493 ; MIPS32: lw [[T5:.*]],56(sp) |
| 494 ; MIPS32: lw [[T6:.*]],60(sp) |
| 495 ; MIPS32: lw [[T7:.*]],64(sp) |
| 496 ; MIPS32: move [[T8:.*]],zero |
| 497 ; MIPS32: move [[T9:.*]],zero |
| 498 ; MIPS32: move [[T10:.*]],zero |
| 499 ; MIPS32: move [[T11:.*]],zero |
| 500 ; MIPS32: andi [[T12:.*]],a0,0xffff |
| 501 ; MIPS32: andi [[T12]],[[T12]],0x1 |
| 502 ; MIPS32: andi [[T13:.*]],[[T0]],0xffff |
| 503 ; MIPS32: andi [[T14:.*]],[[T4]],0xffff |
| 504 ; MIPS32: movn [[T14]],[[T13]],[[T12]] |
| 505 ; MIPS32: andi [[T14]],[[T14]],0xffff |
| 506 ; MIPS32: srl [[T8]],[[T8]],0x10 |
| 507 ; MIPS32: sll [[T8]],[[T8]],0x10 |
| 508 ; MIPS32: or [[T14]],[[T14]],[[T8]] |
| 509 ; MIPS32: srl [[T15:.*]],a0,0x10 |
| 510 ; MIPS32: andi [[T15]],[[T15]],0x1 |
| 511 ; MIPS32: srl [[T0]],[[T0]],0x10 |
| 512 ; MIPS32: srl [[T4]],[[T4]],0x10 |
| 513 ; MIPS32: movn [[T4]],[[T0]],[[T15]] |
| 514 ; MIPS32: sll [[T4]],[[T4]],0x10 |
| 515 ; MIPS32: sll [[T14]],[[T14]],0x10 |
| 516 ; MIPS32: srl [[T14]],[[T14]],0x10 |
| 517 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]] |
| 518 ; MIPS32: andi [[T0]],a1,0xffff |
| 519 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 520 ; MIPS32: andi [[T15]],[[T1]],0xffff |
| 521 ; MIPS32: andi [[T8]],[[T5]],0xffff |
| 522 ; MIPS32: movn [[T8]],[[T15]],[[T0]] |
| 523 ; MIPS32: andi [[T8]],[[T8]],0xffff |
| 524 ; MIPS32: srl [[T9]],[[T9]],0x10 |
| 525 ; MIPS32: sll [[T9]],[[T9]],0x10 |
| 526 ; MIPS32: or [[T8]],[[T8]],[[T9]] |
| 527 ; MIPS32: srl [[T16:.*]],a1,0x10 |
| 528 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 529 ; MIPS32: srl [[T1]],[[T1]],0x10 |
| 530 ; MIPS32: srl [[T5]],[[T5]],0x10 |
| 531 ; MIPS32: movn [[T5]],[[T1]],[[T16]] |
| 532 ; MIPS32: sll [[T5]],[[T5]],0x10 |
| 533 ; MIPS32: sll [[T8]],[[T8]],0x10 |
| 534 ; MIPS32: srl [[T8]],[[T8]],0x10 |
| 535 ; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]] |
| 536 ; MIPS32: andi [[T0]],a2,0xffff |
| 537 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 538 ; MIPS32: andi [[T1]],[[T2]],0xffff |
| 539 ; MIPS32: andi [[T15]],[[T6]],0xffff |
| 540 ; MIPS32: movn [[T15]],[[T1]],[[T0]] |
| 541 ; MIPS32: andi [[T15]],[[T15]],0xffff |
| 542 ; MIPS32: srl [[T10]],[[T10]],0x10 |
| 543 ; MIPS32: sll [[T10]],[[T10]],0x10 |
| 544 ; MIPS32: or [[T15]],[[T15]],[[T10]] |
| 545 ; MIPS32: srl [[T17:.*]],a2,0x10 |
| 546 ; MIPS32: andi [[T17]],[[T17]],0x1 |
| 547 ; MIPS32: srl [[T2]],[[T2]],0x10 |
| 548 ; MIPS32: srl [[T6]],[[T6]],0x10 |
| 549 ; MIPS32: movn [[T6]],[[T2]],[[T17]] |
| 550 ; MIPS32: sll [[T6]],[[T6]],0x10 |
| 551 ; MIPS32: sll [[T15]],[[T15]],0x10 |
| 552 ; MIPS32: srl [[T15]],[[T15]],0x10 |
| 553 ; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]] |
| 554 ; MIPS32: andi [[T0]],a3,0xffff |
| 555 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 556 ; MIPS32: andi [[T1]],[[T3]],0xffff |
| 557 ; MIPS32: andi [[T15]],[[T7]],0xffff |
| 558 ; MIPS32: movn [[T15]],[[T1]],[[T0]] |
| 559 ; MIPS32: andi [[T15]],[[T15]],0xffff |
| 560 ; MIPS32: srl [[T11]],[[T11]],0x10 |
| 561 ; MIPS32: sll [[T11]],[[T11]],0x10 |
| 562 ; MIPS32: or [[T15]],[[T15]],[[T11]] |
| 563 ; MIPS32: srl [[T18:.*]],a3,0x10 |
| 564 ; MIPS32: andi [[T18]],[[T18]],0x1 |
| 565 ; MIPS32: srl [[T3]],[[T3]],0x10 |
| 566 ; MIPS32: srl [[T7]],[[T7]],0x10 |
| 567 ; MIPS32: movn [[T7]],[[T3]],[[T18]] |
| 568 ; MIPS32: sll [[T7]],[[T7]],0x10 |
| 569 ; MIPS32: sll [[T15]],[[T15]],0x10 |
| 570 ; MIPS32: srl [[T15]],[[T15]],0x10 |
| 571 ; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]] |
| 52 } | 572 } |
| 53 | 573 |
| 54 define internal <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1, | 574 define internal <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1, |
| 55 <8 x i1> %arg2) { | 575 <8 x i1> %arg2) { |
| 56 entry: | 576 entry: |
| 57 %res = select <8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2 | 577 %res = select <8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2 |
| 58 ret <8 x i1> %res | 578 ret <8 x i1> %res |
| 59 ; CHECK-LABEL: test_select_v8i1 | 579 ; CHECK-LABEL: test_select_v8i1 |
| 60 ; CHECK: pand | 580 ; CHECK: pand |
| 61 ; CHECK: pandn | 581 ; CHECK: pandn |
| 62 ; CHECK: por | 582 ; CHECK: por |
| 63 | 583 |
| 64 ; SSE41-LABEL: test_select_v8i1 | 584 ; SSE41-LABEL: test_select_v8i1 |
| 65 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 585 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
| 586 |
| 587 ; MIPS32-LABEL: test_select_v8i1 |
| 588 ; MIPS32: lw [[T0:.*]],36(sp) |
| 589 ; MIPS32: lw [[T1:.*]],40(sp) |
| 590 ; MIPS32: lw [[T2:.*]],44(sp) |
| 591 ; MIPS32: lw [[T3:.*]],48(sp) |
| 592 ; MIPS32: lw [[T4:.*]],52(sp) |
| 593 ; MIPS32: lw [[T5:.*]],56(sp) |
| 594 ; MIPS32: lw [[T6:.*]],60(sp) |
| 595 ; MIPS32: lw [[T7:.*]],64(sp) |
| 596 ; MIPS32: move [[T8:.*]],zero |
| 597 ; MIPS32: move [[T9:.*]],zero |
| 598 ; MIPS32: move [[T10:.*]],zero |
| 599 ; MIPS32: move [[T11:.*]],zero |
| 600 ; MIPS32: andi [[T12:.*]],a0,0xffff |
| 601 ; MIPS32: andi [[T12]],[[T12]],0x1 |
| 602 ; MIPS32: andi [[T13:.*]],[[T0]],0xffff |
| 603 ; MIPS32: andi [[T13]],[[T13]],0x1 |
| 604 ; MIPS32: andi [[T14:.*]],[[T4]],0xffff |
| 605 ; MIPS32: andi [[T14]],[[T14]],0x1 |
| 606 ; MIPS32: movn [[T14]],[[T13]],[[T12]] |
| 607 ; MIPS32: andi [[T14]],[[T14]],0xffff |
| 608 ; MIPS32: srl [[T8]],[[T8]],0x10 |
| 609 ; MIPS32: sll [[T8]],[[T8]],0x10 |
| 610 ; MIPS32: or [[T14]],[[T14]],[[T8]] |
| 611 ; MIPS32: srl [[T15:.*]],a0,0x10 |
| 612 ; MIPS32: andi [[T15]],[[T15]],0x1 |
| 613 ; MIPS32: srl [[T0]],[[T0]],0x10 |
| 614 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 615 ; MIPS32: srl [[T4]],[[T4]],0x10 |
| 616 ; MIPS32: andi [[T4]],[[T4]],0x1 |
| 617 ; MIPS32: movn [[T4]],[[T0]],[[T15]] |
| 618 ; MIPS32: sll [[T4]],[[T4]],0x10 |
| 619 ; MIPS32: sll [[T14]],[[T14]],0x10 |
| 620 ; MIPS32: srl [[T14]],[[T14]],0x10 |
| 621 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]] |
| 622 ; MIPS32: andi [[T0]],a1,0xffff |
| 623 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 624 ; MIPS32: andi [[T15]],[[T1]],0xffff |
| 625 ; MIPS32: andi [[T15]],[[T15]],0x1 |
| 626 ; MIPS32: andi [[T8]],[[T5]],0xffff |
| 627 ; MIPS32: andi [[T8]],[[T8]],0x1 |
| 628 ; MIPS32: movn [[T8]],[[T15]],[[T0]] |
| 629 ; MIPS32: andi [[T8]],[[T8]],0xffff |
| 630 ; MIPS32: srl [[T9]],[[T9]],0x10 |
| 631 ; MIPS32: sll [[T9]],[[T9]],0x10 |
| 632 ; MIPS32: or [[T8]],[[T8]],[[T9]] |
| 633 ; MIPS32: srl [[T16:.*]],a1,0x10 |
| 634 ; MIPS32: andi [[T16]],[[T16]],0x1 |
| 635 ; MIPS32: srl [[T1]],[[T1]],0x10 |
| 636 ; MIPS32: andi [[T1]],[[T1]],0x1 |
| 637 ; MIPS32: srl [[T5]],[[T5]],0x10 |
| 638 ; MIPS32: andi [[T5]],[[T5]],0x1 |
| 639 ; MIPS32: movn [[T5]],[[T1]],[[T16]] |
| 640 ; MIPS32: sll [[T5]],[[T5]],0x10 |
| 641 ; MIPS32: sll [[T8]],[[T8]],0x10 |
| 642 ; MIPS32: srl [[T8]],[[T8]],0x10 |
| 643 ; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]] |
| 644 ; MIPS32: andi [[T0]],a2,0xffff |
| 645 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 646 ; MIPS32: andi [[T1]],[[T2]],0xffff |
| 647 ; MIPS32: andi [[T1]],[[T1]],0x1 |
| 648 ; MIPS32: andi [[T15]],[[T6]],0xffff |
| 649 ; MIPS32: andi [[T15]],[[T15]],0x1 |
| 650 ; MIPS32: movn [[T15]],[[T1]],[[T0]] |
| 651 ; MIPS32: andi [[T15]],[[T15]],0xffff |
| 652 ; MIPS32: srl [[T10]],[[T10]],0x10 |
| 653 ; MIPS32: sll [[T10]],[[T10]],0x10 |
| 654 ; MIPS32: or [[T15]],[[T15]],[[T10]] |
| 655 ; MIPS32: srl [[T17:.*]],a2,0x10 |
| 656 ; MIPS32: andi [[T17]],[[T17]],0x1 |
| 657 ; MIPS32: srl [[T2]],[[T2]],0x10 |
| 658 ; MIPS32: andi [[T2]],[[T2]],0x1 |
| 659 ; MIPS32: srl [[T6]],[[T6]],0x10 |
| 660 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 661 ; MIPS32: movn [[T6]],[[T2]],[[T17]] |
| 662 ; MIPS32: sll [[T6]],[[T6]],0x10 |
| 663 ; MIPS32: sll [[T15]],[[T15]],0x10 |
| 664 ; MIPS32: srl [[T15]],[[T15]],0x10 |
| 665 ; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]] |
| 666 ; MIPS32: andi [[T0]],a3,0xffff |
| 667 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 668 ; MIPS32: andi [[T1]],[[T3]],0xffff |
| 669 ; MIPS32: andi [[T1]],[[T1]],0x1 |
| 670 ; MIPS32: andi [[T15]],[[T7]],0xffff |
| 671 ; MIPS32: andi [[T15]],[[T15]],0x1 |
| 672 ; MIPS32: movn [[T15]],[[T1]],[[T0]] |
| 673 ; MIPS32: andi [[T15]],[[T15]],0xffff |
| 674 ; MIPS32: srl [[T11]],[[T11]],0x10 |
| 675 ; MIPS32: sll [[T11]],[[T11]],0x10 |
| 676 ; MIPS32: or [[T15]],[[T15]],[[T11]] |
| 677 ; MIPS32: srl [[T18:.*]],a3,0x10 |
| 678 ; MIPS32: andi [[T18]],[[T18]],0x1 |
| 679 ; MIPS32: srl [[T3]],[[T3]],0x10 |
| 680 ; MIPS32: andi [[T3]],[[T3]],0x1 |
| 681 ; MIPS32: srl [[T7]],[[T7]],0x10 |
| 682 ; MIPS32: andi [[T7]],[[T7]],0x1 |
| 683 ; MIPS32: movn [[T7]],[[T3]],[[T18]] |
| 684 ; MIPS32: sll [[T7]],[[T7]],0x10 |
| 685 ; MIPS32: sll [[T15]],[[T15]],0x10 |
| 686 ; MIPS32: srl [[T15]],[[T15]],0x10 |
| 687 ; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]] |
| 66 } | 688 } |
| 67 | 689 |
| 68 define internal <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1, | 690 define internal <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1, |
| 69 <4 x i32> %arg2) { | 691 <4 x i32> %arg2) { |
| 70 entry: | 692 entry: |
| 71 %res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2 | 693 %res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2 |
| 72 ret <4 x i32> %res | 694 ret <4 x i32> %res |
| 73 ; CHECK-LABEL: test_select_v4i32 | 695 ; CHECK-LABEL: test_select_v4i32 |
| 74 ; CHECK: pand | 696 ; CHECK: pand |
| 75 ; CHECK: pandn | 697 ; CHECK: pandn |
| 76 ; CHECK: por | 698 ; CHECK: por |
| 77 | 699 |
| 78 ; SSE41-LABEL: test_select_v4i32 | 700 ; SSE41-LABEL: test_select_v4i32 |
| 79 ; SSE41: pslld xmm0,0x1f | 701 ; SSE41: pslld xmm0,0x1f |
| 80 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 702 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
| 703 |
| 704 ; MIPS32-LABEL: test_select_v4i32 |
| 705 ; MIPS32: lw [[T0:.*]],16(sp) |
| 706 ; MIPS32: lw [[T1:.*]],20(sp) |
| 707 ; MIPS32: lw [[T2:.*]],24(sp) |
| 708 ; MIPS32: lw [[T3:.*]],28(sp) |
| 709 ; MIPS32: lw [[T4:.*]],32(sp) |
| 710 ; MIPS32: lw [[T5:.*]],36(sp) |
| 711 ; MIPS32: lw [[T6:.*]],40(sp) |
| 712 ; MIPS32: lw [[T7:.*]],44(sp) |
| 713 ; MIPS32: andi [[T8:.*]],a0,0x1 |
| 714 ; MIPS32: movn [[T4]],[[T0]],[[T8]] |
| 715 ; MIPS32: andi [[T9:.*]],a1,0x1 |
| 716 ; MIPS32: movn [[T5]],[[T1]],[[T9]] |
| 717 ; MIPS32: andi [[T10:.*]],a2,0x1 |
| 718 ; MIPS32: movn [[T6]],[[T2]],[[T10]] |
| 719 ; MIPS32: andi [[T11:.*]],a3,0x1 |
| 720 ; MIPS32: movn [[T7]],[[T3]],[[T11]] |
| 721 ; MIPS32: move v0,[[T4]] |
| 722 ; MIPS32: move v1,[[T5]] |
| 723 ; MIPS32: move a0,[[T6]] |
| 724 ; MIPS32: move a1,[[T7]] |
| 81 } | 725 } |
| 82 | 726 |
| 83 define internal <4 x float> @test_select_v4f32( | 727 define internal <4 x float> @test_select_v4f32( |
| 84 <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2) { | 728 <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2) { |
| 85 entry: | 729 entry: |
| 86 %res = select <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2 | 730 %res = select <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2 |
| 87 ret <4 x float> %res | 731 ret <4 x float> %res |
| 88 ; CHECK-LABEL: test_select_v4f32 | 732 ; CHECK-LABEL: test_select_v4f32 |
| 89 ; CHECK: pand | 733 ; CHECK: pand |
| 90 ; CHECK: pandn | 734 ; CHECK: pandn |
| 91 ; CHECK: por | 735 ; CHECK: por |
| 92 | 736 |
| 93 ; SSE41-LABEL: test_select_v4f32 | 737 ; SSE41-LABEL: test_select_v4f32 |
| 94 ; SSE41: pslld xmm0,0x1f | 738 ; SSE41: pslld xmm0,0x1f |
| 95 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 739 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
| 740 |
| 741 ; MIPS32-LABEL: test_select_v4f32 |
| 742 ; MIPS32: lw [[T0:.*]],16(sp) |
| 743 ; MIPS32: lw [[T1:.*]],20(sp) |
| 744 ; MIPS32: lw [[T2:.*]],24(sp) |
| 745 ; MIPS32: lw [[T3:.*]],28(sp) |
| 746 ; MIPS32: lw [[T4:.*]],32(sp) |
| 747 ; MIPS32: lw [[T5:.*]],36(sp) |
| 748 ; MIPS32: lw [[T6:.*]],40(sp) |
| 749 ; MIPS32: lw [[T7:.*]],44(sp) |
| 750 ; MIPS32: lw [[T8:.*]],48(sp) |
| 751 ; MIPS32: lw [[T9:.*]],52(sp) |
| 752 ; MIPS32: andi [[T10:.*]],a2,0x1 |
| 753 ; MIPS32: mtc1 [[T2]],[[F0:.*]] |
| 754 ; MIPS32: mtc1 [[T6]],[[F1:.*]] |
| 755 ; MIPS32: movn.s [[T11:.*]],[[F0]],[[T10]] |
| 756 ; MIPS32: mfc1 v0,[[T11]] |
| 757 ; MIPS32: andi [[T12:.*]],a3,0x1 |
| 758 ; MIPS32: mtc1 [[T3]],[[F0]] |
| 759 ; MIPS32: mtc1 [[T7]],[[T11]] |
| 760 ; MIPS32: movn.s [[T11]],[[F0]],[[T12]] |
| 761 ; MIPS32: mfc1 v1,[[T11]] |
| 762 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 763 ; MIPS32: mtc1 [[T4]],[[F0]] |
| 764 ; MIPS32: mtc1 [[T8]],[[T11]] |
| 765 ; MIPS32: movn.s [[T11]],[[F0]],[[T0]] |
| 766 ; MIPS32: mfc1 a1,[[T11]] |
| 767 ; MIPS32: andi [[T1]],[[T1]],0x1 |
| 768 ; MIPS32: mtc1 [[T5]],[[F0]] |
| 769 ; MIPS32: mtc1 [[T9]],[[T11]] |
| 770 ; MIPS32: movn.s [[T11]],[[F0]],[[T1]] |
| 771 ; MIPS32: mfc1 a2,[[T11]] |
| 772 ; MIPS32: move [[RET:.*]],a0 |
| 773 ; MIPS32: sw v0,0([[RET]]) |
| 774 ; MIPS32: sw v1,4([[RET]]) |
| 775 ; MIPS32: sw a1,8([[RET]]) |
| 776 ; MIPS32: sw a2,12([[RET]]) |
| 777 ; MIPS32: move v0,a0 |
| 96 } | 778 } |
| 97 | 779 |
| 98 define internal <4 x i1> @test_select_v4i1(<4 x i1> %cond, <4 x i1> %arg1, | 780 define internal <4 x i1> @test_select_v4i1(<4 x i1> %cond, <4 x i1> %arg1, |
| 99 <4 x i1> %arg2) { | 781 <4 x i1> %arg2) { |
| 100 entry: | 782 entry: |
| 101 %res = select <4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2 | 783 %res = select <4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2 |
| 102 ret <4 x i1> %res | 784 ret <4 x i1> %res |
| 103 ; CHECK-LABEL: test_select_v4i1 | 785 ; CHECK-LABEL: test_select_v4i1 |
| 104 ; CHECK: pand | 786 ; CHECK: pand |
| 105 ; CHECK: pandn | 787 ; CHECK: pandn |
| 106 ; CHECK: por | 788 ; CHECK: por |
| 107 | 789 |
| 108 ; SSE41-LABEL: test_select_v4i1 | 790 ; SSE41-LABEL: test_select_v4i1 |
| 109 ; SSE41: pslld xmm0,0x1f | 791 ; SSE41: pslld xmm0,0x1f |
| 110 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} | 792 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} |
| 793 |
| 794 ; MIPS32-LABEL: test_select_v4i1 |
| 795 ; MIPS32: lw [[T0:.*]],16(sp) |
| 796 ; MIPS32: lw [[T1:.*]],20(sp) |
| 797 ; MIPS32: lw [[T2:.*]],24(sp) |
| 798 ; MIPS32: lw [[T3:.*]],28(sp) |
| 799 ; MIPS32: lw [[T4:.*]],32(sp) |
| 800 ; MIPS32: lw [[T5:.*]],36(sp) |
| 801 ; MIPS32: lw [[T6:.*]],40(sp) |
| 802 ; MIPS32: lw [[T7:.*]],44(sp) |
| 803 ; MIPS32: andi [[T8:.*]],a0,0x1 |
| 804 ; MIPS32: andi [[T0]],[[T0]],0x1 |
| 805 ; MIPS32: andi [[T4]],[[T4]],0x1 |
| 806 ; MIPS32: movn [[T4]],[[T0]],[[T8]] |
| 807 ; MIPS32: andi [[T9:.*]],a1,0x1 |
| 808 ; MIPS32: andi [[T1]],[[T1]],0x1 |
| 809 ; MIPS32: andi [[T5]],[[T5]],0x1 |
| 810 ; MIPS32: movn [[T5]],[[T1]],[[T9]] |
| 811 ; MIPS32: andi [[T10:.*]],a2,0x1 |
| 812 ; MIPS32: andi [[T2]],[[T2]],0x1 |
| 813 ; MIPS32: andi [[T6]],[[T6]],0x1 |
| 814 ; MIPS32: movn [[T6]],[[T2]],[[T10]] |
| 815 ; MIPS32: andi [[T11:.*]],a3,0x1 |
| 816 ; MIPS32: andi [[T3]],[[T3]],0x1 |
| 817 ; MIPS32: andi [[T7]],[[T7]],0x1 |
| 818 ; MIPS32: movn [[T7]],[[T3]],[[T11]] |
| 819 ; MIPS32: move v0,[[T4]] |
| 820 ; MIPS32: move v1,[[T5]] |
| 821 ; MIPS32: move a0,[[T6]] |
| 822 ; MIPS32: move a1,[[T7]] |
| 111 } | 823 } |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 2412053002:
[SubZero] Implement Fcmp, ICmp, Cast and Select for vector type (Closed)
Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master