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Issue 2412053002: [SubZero] Implement Fcmp, ICmp, Cast and Select for vector type (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 2 months ago
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1 ; This file checks support for comparing vector values with the icmp 1 ; This file checks support for comparing vector values with the icmp
2 ; instruction. 2 ; instruction.
3 3
4 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s 4 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s
5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s
6 6
7 ; RUN: %if --need=target_MIPS32 --need=allow_dump \
8 ; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
9 ; RUN: -i %s --args -O2 --skip-unimplemented \
10 ; RUN: | %if --need=target_MIPS32 --need=allow_dump \
11 ; RUN: --command FileCheck --check-prefix MIPS32 %s
12
7 ; Check that sext elimination occurs when the result of the comparison 13 ; Check that sext elimination occurs when the result of the comparison
8 ; instruction is alrady sign extended. Sign extension to 4 x i32 uses 14 ; instruction is alrady sign extended. Sign extension to 4 x i32 uses
Jim Stichnoth 2016/10/14 13:43:37 Could you fix this typo while you're at it? :) s/
jaydeep.patil 2016/10/15 03:47:57 Done.
9 ; the pslld instruction. 15 ; the pslld instruction.
Jim Stichnoth 2016/10/14 13:43:37 maybe "uses the pslld instruction on x86" ?
jaydeep.patil 2016/10/15 03:47:57 Done.
10 define internal <4 x i32> @test_sext_elimination(<4 x i32> %a, <4 x i32> %b) { 16 define internal <4 x i32> @test_sext_elimination(<4 x i32> %a, <4 x i32> %b) {
11 entry: 17 entry:
12 %res.trunc = icmp eq <4 x i32> %a, %b 18 %res.trunc = icmp eq <4 x i32> %a, %b
13 %res = sext <4 x i1> %res.trunc to <4 x i32> 19 %res = sext <4 x i1> %res.trunc to <4 x i32>
14 ret <4 x i32> %res 20 ret <4 x i32> %res
15 ; CHECK-LABEL: test_sext_elimination 21 ; CHECK-LABEL: test_sext_elimination
16 ; CHECK: pcmpeqd 22 ; CHECK: pcmpeqd
17 ; CHECK-NOT: pslld 23 ; CHECK-NOT: pslld
24
25 ; MIPS32-LABEL: test_sext_elimination
Jim Stichnoth 2016/10/14 13:43:37 Regarding this file: WOW! These MIPS tests are hi
jaydeep.patil 2016/10/15 03:47:57 Acknowledged.
26 ; MIPS32: lw [[B_E0:.*]],
27 ; MIPS32: lw [[B_E1:.*]],
28 ; MIPS32: lw [[B_E2:.*]],
29 ; MIPS32: lw [[B_E3:.*]],
30 ; MIPS32: xor [[R_E0:.*]],a0,[[B_E0]]
31 ; MIPS32: sltiu [[R_E0]],[[R_E0]],1
32 ; MIPS32: xor [[R_E1:.*]],a1,[[B_E1]]
33 ; MIPS32: sltiu [[R_E1]],[[R_E1]],1
34 ; MIPS32: xor [[R_E2:.*]],a2,[[B_E2]]
35 ; MIPS32: sltiu [[R_E2]],[[R_E2]],1
36 ; MIPS32: xor [[R_E3:.*]],a3,[[B_E3]]
37 ; MIPS32: sltiu [[R_E3]],[[R_E3]],1
38 ; MIPS32: andi [[R_E0]],[[R_E0]],0x1
39 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
40 ; MIPS32: sra [[R_E0]],[[R_E0]],0x1f
41 ; MIPS32: andi [[R_E1]],[[R_E1]],0x1
42 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
43 ; MIPS32: sra [[R_E1]],[[R_E1]],0x1f
44 ; MIPS32: andi [[R_E2]],[[R_E2]],0x1
45 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
46 ; MIPS32: sra [[R_E2]],[[R_E2]],0x1f
47 ; MIPS32: andi [[R_E3]],[[R_E3]],0x1
48 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
49 ; MIPS32: sra [[R_E3]],[[R_E3]],0x1f
50 ; MIPS32: move v0,[[R_E0]]
51 ; MIPS32: move v1,[[R_E1]]
52 ; MIPS32: move a0,[[R_E2]]
53 ; MIPS32: move a1,[[R_E3]]
18 } 54 }
19 55
20 define internal <4 x i1> @test_icmp_v4i32_eq(<4 x i32> %a, <4 x i32> %b) { 56 define internal <4 x i1> @test_icmp_v4i32_eq(<4 x i32> %a, <4 x i32> %b) {
21 entry: 57 entry:
22 %res = icmp eq <4 x i32> %a, %b 58 %res = icmp eq <4 x i32> %a, %b
23 ret <4 x i1> %res 59 ret <4 x i1> %res
24 ; CHECK-LABEL: test_icmp_v4i32_eq 60 ; CHECK-LABEL: test_icmp_v4i32_eq
25 ; CHECK: pcmpeqd 61 ; CHECK: pcmpeqd
62
63 ; MIPS32-LABEL: test_icmp_v4i32_eq
64 ; MIPS32: lw [[B_E0:.*]],
65 ; MIPS32: lw [[B_E1:.*]],
66 ; MIPS32: lw [[B_E2:.*]],
67 ; MIPS32: lw [[B_E3:.*]],
68 ; MIPS32: xor [[R_E0:.*]],a0,[[B_E0]]
69 ; MIPS32: sltiu [[R_E0]],[[R_E0]],1
70 ; MIPS32: xor [[R_E1:.*]],a1,[[B_E1]]
71 ; MIPS32: sltiu [[R_E1]],[[R_E1]],1
72 ; MIPS32: xor [[R_E2:.*]],a2,[[B_E2]]
73 ; MIPS32: sltiu [[R_E2]],[[R_E2]],1
74 ; MIPS32: xor [[R_E3:.*]],a3,[[B_E3]]
75 ; MIPS32: sltiu [[R_E3]],[[R_E3]],1
76 ; MIPS32: move v0,[[R_E0]]
77 ; MIPS32: move v1,[[R_E1]]
78 ; MIPS32: move a0,[[R_E2]]
79 ; MIPS32: move a1,[[R_E3]]
26 } 80 }
27 81
28 define internal <4 x i1> @test_icmp_v4i32_ne(<4 x i32> %a, <4 x i32> %b) { 82 define internal <4 x i1> @test_icmp_v4i32_ne(<4 x i32> %a, <4 x i32> %b) {
29 entry: 83 entry:
30 %res = icmp ne <4 x i32> %a, %b 84 %res = icmp ne <4 x i32> %a, %b
31 ret <4 x i1> %res 85 ret <4 x i1> %res
32 ; CHECK-LABEL: test_icmp_v4i32_ne 86 ; CHECK-LABEL: test_icmp_v4i32_ne
33 ; CHECK: pcmpeqd 87 ; CHECK: pcmpeqd
34 ; CHECK: pxor 88 ; CHECK: pxor
89
90 ; MIPS32-LABEL: test_icmp_v4i32_ne
91 ; MIPS32: lw [[B_E0:.*]],
92 ; MIPS32: lw [[B_E1:.*]],
93 ; MIPS32: lw [[B_E2:.*]],
94 ; MIPS32: lw [[B_E3:.*]],
95 ; MIPS32: xor [[R_E0:.*]],a0,[[B_E0]]
96 ; MIPS32: sltu [[R_E0]],zero,[[R_E0]]
97 ; MIPS32: xor [[R_E1:.*]],a1,[[B_E1]]
98 ; MIPS32: sltu [[R_E1]],zero,[[R_E1]]
99 ; MIPS32: xor [[R_E2:.*]],a2,[[B_E2]]
100 ; MIPS32: sltu [[R_E2]],zero,[[R_E2]]
101 ; MIPS32: xor [[R_E3:.*]],a3,[[B_E3]]
102 ; MIPS32: sltu [[R_E3]],zero,[[R_E3]]
103 ; MIPS32: move v0,[[R_E0]]
104 ; MIPS32: move v1,[[R_E1]]
105 ; MIPS32: move a0,[[R_E2]]
106 ; MIPS32: move a1,[[R_E3]]
35 } 107 }
36 108
37 define internal <4 x i1> @test_icmp_v4i32_sgt(<4 x i32> %a, <4 x i32> %b) { 109 define internal <4 x i1> @test_icmp_v4i32_sgt(<4 x i32> %a, <4 x i32> %b) {
38 entry: 110 entry:
39 %res = icmp sgt <4 x i32> %a, %b 111 %res = icmp sgt <4 x i32> %a, %b
40 ret <4 x i1> %res 112 ret <4 x i1> %res
41 ; CHECK: pcmpgtd 113 ; CHECK: pcmpgtd
114
115 ; MIPS32-LABEL: test_icmp_v4i32_sgt
116 ; MIPS32: lw [[B_E0:.*]],
117 ; MIPS32: lw [[B_E1:.*]],
118 ; MIPS32: lw [[B_E2:.*]],
119 ; MIPS32: lw [[B_E3:.*]],
120 ; MIPS32: slt [[R_E0:.*]],[[B_E0]],a0
121 ; MIPS32: slt [[R_E1:.*]],[[B_E1]],a1
122 ; MIPS32: slt [[R_E2:.*]],[[B_E2]],a2
123 ; MIPS32: slt [[R_E3:.*]],[[B_E3]],a3
42 } 124 }
43 125
44 define internal <4 x i1> @test_icmp_v4i32_sle(<4 x i32> %a, <4 x i32> %b) { 126 define internal <4 x i1> @test_icmp_v4i32_sle(<4 x i32> %a, <4 x i32> %b) {
45 entry: 127 entry:
46 %res = icmp sle <4 x i32> %a, %b 128 %res = icmp sle <4 x i32> %a, %b
47 ret <4 x i1> %res 129 ret <4 x i1> %res
48 ; CHECK-LABEL: test_icmp_v4i32_sle 130 ; CHECK-LABEL: test_icmp_v4i32_sle
49 ; CHECK: pcmpgtd 131 ; CHECK: pcmpgtd
50 ; CHECK: pxor 132 ; CHECK: pxor
133
134 ; MIPS32-LABEL: test_icmp_v4i32_sle
135 ; MIPS32: lw [[B_E0:.*]],
136 ; MIPS32: lw [[B_E1:.*]],
137 ; MIPS32: lw [[B_E2:.*]],
138 ; MIPS32: lw [[B_E3:.*]],
139 ; MIPS32: slt [[R_E0:.*]],[[B_E0]],a0
140 ; MIPS32: xori [[R_E0]],[[R_E0]],0x1
141 ; MIPS32: slt [[R_E1:.*]],[[B_E1]],a1
142 ; MIPS32: xori [[R_E1]],[[R_E1]],0x1
143 ; MIPS32: slt [[R_E2:.*]],[[B_E2]],a2
144 ; MIPS32: xori [[R_E2]],[[R_E2]],0x1
145 ; MIPS32: slt [[R_E3:.*]],[[B_E3]],a3
146 ; MIPS32: xori [[R_E3]],[[R_E3]],0x1
51 } 147 }
52 148
53 define internal <4 x i1> @test_icmp_v4i32_slt(<4 x i32> %a, <4 x i32> %b) { 149 define internal <4 x i1> @test_icmp_v4i32_slt(<4 x i32> %a, <4 x i32> %b) {
54 entry: 150 entry:
55 %res = icmp slt <4 x i32> %a, %b 151 %res = icmp slt <4 x i32> %a, %b
56 ret <4 x i1> %res 152 ret <4 x i1> %res
57 ; CHECK-LABEL: test_icmp_v4i32_slt 153 ; CHECK-LABEL: test_icmp_v4i32_slt
58 ; CHECK: pcmpgtd 154 ; CHECK: pcmpgtd
155
156 ; MIPS32-LABEL: test_icmp_v4i32_slt
157 ; MIPS32: lw [[B_E0:.*]],
158 ; MIPS32: lw [[B_E1:.*]],
159 ; MIPS32: lw [[B_E2:.*]],
160 ; MIPS32: lw [[B_E3:.*]],
161 ; MIPS32: slt [[R_E0:.*]],a0,[[B_E0]]
162 ; MIPS32: slt [[R_E1:.*]],a1,[[B_E1]]
163 ; MIPS32: slt [[R_E2:.*]],a2,[[B_E2]]
164 ; MIPS32: slt [[R_E3:.*]],a3,[[B_E3]]
59 } 165 }
60 166
61 define internal <4 x i1> @test_icmp_v4i32_uge(<4 x i32> %a, <4 x i32> %b) { 167 define internal <4 x i1> @test_icmp_v4i32_uge(<4 x i32> %a, <4 x i32> %b) {
62 entry: 168 entry:
63 %res = icmp uge <4 x i32> %a, %b 169 %res = icmp uge <4 x i32> %a, %b
64 ret <4 x i1> %res 170 ret <4 x i1> %res
65 ; CHECK-LABEL: test_icmp_v4i32_uge 171 ; CHECK-LABEL: test_icmp_v4i32_uge
66 ; CHECK: pxor 172 ; CHECK: pxor
67 ; CHECK: pcmpgtd 173 ; CHECK: pcmpgtd
68 ; CHECK: pxor 174 ; CHECK: pxor
175
176 ; MIPS32-LABEL: test_icmp_v4i32_uge
177 ; MIPS32: lw [[B_E0:.*]],
178 ; MIPS32: lw [[B_E1:.*]],
179 ; MIPS32: lw [[B_E2:.*]],
180 ; MIPS32: lw [[B_E3:.*]],
181 ; MIPS32: sltu [[R_E0:.*]],a0,[[B_E0]]
182 ; MIPS32: xori [[R_E0]],[[R_E0]],0x1
183 ; MIPS32: sltu [[R_E1:.*]],a1,[[B_E1]]
184 ; MIPS32: xori [[R_E1]],[[R_E1]],0x1
185 ; MIPS32: sltu [[R_E2:.*]],a2,[[B_E2]]
186 ; MIPS32: xori [[R_E2]],[[R_E2]],0x1
187 ; MIPS32: sltu [[R_E3:.*]],a3,[[B_E3]]
188 ; MIPS32: xori [[R_E3]],[[R_E3]],0x1
69 } 189 }
70 190
71 define internal <4 x i1> @test_icmp_v4i32_ugt(<4 x i32> %a, <4 x i32> %b) { 191 define internal <4 x i1> @test_icmp_v4i32_ugt(<4 x i32> %a, <4 x i32> %b) {
72 entry: 192 entry:
73 %res = icmp ugt <4 x i32> %a, %b 193 %res = icmp ugt <4 x i32> %a, %b
74 ret <4 x i1> %res 194 ret <4 x i1> %res
75 ; CHECK-LABEL: test_icmp_v4i32_ugt 195 ; CHECK-LABEL: test_icmp_v4i32_ugt
76 ; CHECK: pxor 196 ; CHECK: pxor
77 ; CHECK: pcmpgtd 197 ; CHECK: pcmpgtd
198
199 ; MIPS32-LABEL: test_icmp_v4i32_ugt
200 ; MIPS32: lw [[B_E0:.*]],
201 ; MIPS32: lw [[B_E1:.*]],
202 ; MIPS32: lw [[B_E2:.*]],
203 ; MIPS32: lw [[B_E3:.*]],
204 ; MIPS32: sltu [[R_E0:.*]],[[B_E0]],a0
205 ; MIPS32: sltu [[R_E1:.*]],[[B_E1]],a1
206 ; MIPS32: sltu [[R_E2:.*]],[[B_E2]],a2
207 ; MIPS32: sltu [[R_E3:.*]],[[B_E3]],a3
78 } 208 }
79 209
80 define internal <4 x i1> @test_icmp_v4i32_ule(<4 x i32> %a, <4 x i32> %b) { 210 define internal <4 x i1> @test_icmp_v4i32_ule(<4 x i32> %a, <4 x i32> %b) {
81 entry: 211 entry:
82 %res = icmp ule <4 x i32> %a, %b 212 %res = icmp ule <4 x i32> %a, %b
83 ret <4 x i1> %res 213 ret <4 x i1> %res
84 ; CHECK-LABEL: test_icmp_v4i32_ule 214 ; CHECK-LABEL: test_icmp_v4i32_ule
85 ; CHECK: pxor 215 ; CHECK: pxor
86 ; CHECK: pcmpgtd 216 ; CHECK: pcmpgtd
87 ; CHECK: pxor 217 ; CHECK: pxor
218
219 ; MIPS32-LABEL: test_icmp_v4i32_ule
220 ; MIPS32: lw [[B_E0:.*]],
221 ; MIPS32: lw [[B_E1:.*]],
222 ; MIPS32: lw [[B_E2:.*]],
223 ; MIPS32: lw [[B_E3:.*]],
224 ; MIPS32: sltu [[R_E0:.*]],[[B_E0]],a0
225 ; MIPS32: xori [[R_E0]],[[R_E0]],0x1
226 ; MIPS32: sltu [[R_E1:.*]],[[B_E1]],a1
227 ; MIPS32: xori [[R_E1]],[[R_E1]],0x1
228 ; MIPS32: sltu [[R_E2:.*]],[[B_E2]],a2
229 ; MIPS32: xori [[R_E2]],[[R_E2]],0x1
230 ; MIPS32: sltu [[R_E3:.*]],[[B_E3]],a3
231 ; MIPS32: xori [[R_E3]],[[R_E3]],0x1
88 } 232 }
89 233
90 define internal <4 x i1> @test_icmp_v4i32_ult(<4 x i32> %a, <4 x i32> %b) { 234 define internal <4 x i1> @test_icmp_v4i32_ult(<4 x i32> %a, <4 x i32> %b) {
91 entry: 235 entry:
92 %res = icmp ult <4 x i32> %a, %b 236 %res = icmp ult <4 x i32> %a, %b
93 ret <4 x i1> %res 237 ret <4 x i1> %res
94 ; CHECK-LABEL: test_icmp_v4i32_ult 238 ; CHECK-LABEL: test_icmp_v4i32_ult
95 ; CHECK: pxor 239 ; CHECK: pxor
96 ; CHECK: pcmpgtd 240 ; CHECK: pcmpgtd
241
242 ; MIPS32-LABEL: test_icmp_v4i32_ult
243 ; MIPS32: lw [[B_E0:.*]],
244 ; MIPS32: lw [[B_E1:.*]],
245 ; MIPS32: lw [[B_E2:.*]],
246 ; MIPS32: lw [[B_E3:.*]],
247 ; MIPS32: sltu [[R_E0:.*]],a0,[[B_E0]]
248 ; MIPS32: sltu [[R_E1:.*]],a1,[[B_E1]]
249 ; MIPS32: sltu [[R_E2:.*]],a2,[[B_E2]]
250 ; MIPS32: sltu [[R_E3:.*]],a3,[[B_E3]]
97 } 251 }
98 252
99 define internal <4 x i1> @test_icmp_v4i1_eq(<4 x i1> %a, <4 x i1> %b) { 253 define internal <4 x i1> @test_icmp_v4i1_eq(<4 x i1> %a, <4 x i1> %b) {
100 entry: 254 entry:
101 %res = icmp eq <4 x i1> %a, %b 255 %res = icmp eq <4 x i1> %a, %b
102 ret <4 x i1> %res 256 ret <4 x i1> %res
103 ; CHECK-LABEL: test_icmp_v4i1_eq 257 ; CHECK-LABEL: test_icmp_v4i1_eq
104 ; CHECK: pcmpeqd 258 ; CHECK: pcmpeqd
259
260 ; MIPS32-LABEL: test_icmp_v4i1_eq
261 ; MIPS32: lw [[B_E0:.*]],
262 ; MIPS32: lw [[B_E1:.*]],
263 ; MIPS32: lw [[B_E2:.*]],
264 ; MIPS32: lw [[B_E3:.*]],
265 ; MIPS32: andi [[R_E0:.*]],a0,0x1
266 ; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1
267 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
268 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
269 ; MIPS32: xor [[R_E0]],[[R_E0]],[[T_E0]]
270 ; MIPS32: sltiu [[R_E0]],[[R_E0]],1
271 ; MIPS32: andi [[R_E1:.*]],a1,0x1
272 ; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1
273 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
274 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
275 ; MIPS32: xor [[R_E1]],[[R_E1]],[[T_E1]]
276 ; MIPS32: sltiu [[R_E1]],[[R_E1]],1
277 ; MIPS32: andi [[R_E2:.*]],a2,0x1
278 ; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1
279 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
280 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
281 ; MIPS32: xor [[R_E2]],[[R_E2]],[[T_E2]]
282 ; MIPS32: sltiu [[R_E2]],[[R_E2]],1
283 ; MIPS32: andi [[R_E3:.*]],a3,0x1
284 ; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1
285 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
286 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
287 ; MIPS32: xor [[R_E3]],[[R_E3]],[[T_E3]]
288 ; MIPS32: sltiu [[R_E3]],[[R_E3]],1
289 ; MIPS32: move v0,[[R_E0]]
290 ; MIPS32: move v1,[[R_E1]]
291 ; MIPS32: move a0,[[R_E2]]
292 ; MIPS32: move a1,[[R_E3]]
105 } 293 }
106 294
107 define internal <4 x i1> @test_icmp_v4i1_ne(<4 x i1> %a, <4 x i1> %b) { 295 define internal <4 x i1> @test_icmp_v4i1_ne(<4 x i1> %a, <4 x i1> %b) {
108 entry: 296 entry:
109 %res = icmp ne <4 x i1> %a, %b 297 %res = icmp ne <4 x i1> %a, %b
110 ret <4 x i1> %res 298 ret <4 x i1> %res
111 ; CHECK-LABEL: test_icmp_v4i1_ne 299 ; CHECK-LABEL: test_icmp_v4i1_ne
112 ; CHECK: pcmpeqd 300 ; CHECK: pcmpeqd
113 ; CHECK: pxor 301 ; CHECK: pxor
302
303 ; MIPS32-LABEL: test_icmp_v4i1_ne
304 ; MIPS32: lw [[B_E0:.*]],
305 ; MIPS32: lw [[B_E1:.*]],
306 ; MIPS32: lw [[B_E2:.*]],
307 ; MIPS32: lw [[B_E3:.*]],
308 ; MIPS32: andi [[R_E0:.*]],a0,0x1
309 ; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1
310 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
311 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
312 ; MIPS32: xor [[R_E0]],[[R_E0]],[[T_E0]]
313 ; MIPS32: sltu [[R_E0]],zero,[[R_E0]]
314 ; MIPS32: andi [[R_E1:.*]],a1,0x1
315 ; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1
316 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
317 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
318 ; MIPS32: xor [[R_E1]],[[R_E1]],[[T_E1]]
319 ; MIPS32: sltu [[R_E1]],zero,[[R_E1]]
320 ; MIPS32: andi [[R_E2:.*]],a2,0x1
321 ; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1
322 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
323 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
324 ; MIPS32: xor [[R_E2]],[[R_E2]],[[T_E2]]
325 ; MIPS32: sltu [[R_E2]],zero,[[R_E2]]
326 ; MIPS32: andi [[R_E3:.*]],a3,0x1
327 ; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1
328 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
329 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
330 ; MIPS32: xor [[R_E3]],[[R_E3]],[[T_E3]]
331 ; MIPS32: sltu [[R_E3]],zero,[[R_E3]]
332 ; MIPS32: move v0,[[R_E0]]
333 ; MIPS32: move v1,[[R_E1]]
334 ; MIPS32: move a0,[[R_E2]]
335 ; MIPS32: move a1,[[R_E3]]
114 } 336 }
115 337
116 define internal <4 x i1> @test_icmp_v4i1_sgt(<4 x i1> %a, <4 x i1> %b) { 338 define internal <4 x i1> @test_icmp_v4i1_sgt(<4 x i1> %a, <4 x i1> %b) {
117 entry: 339 entry:
118 %res = icmp sgt <4 x i1> %a, %b 340 %res = icmp sgt <4 x i1> %a, %b
119 ret <4 x i1> %res 341 ret <4 x i1> %res
120 ; CHECK-LABEL: test_icmp_v4i1_sgt 342 ; CHECK-LABEL: test_icmp_v4i1_sgt
121 ; CHECK: pcmpgtd 343 ; CHECK: pcmpgtd
344
345 ; MIPS32-LABEL: test_icmp_v4i1_sgt
346 ; MIPS32: lw [[B_E0:.*]],
347 ; MIPS32: lw [[B_E1:.*]],
348 ; MIPS32: lw [[B_E2:.*]],
349 ; MIPS32: lw [[B_E3:.*]],
350 ; MIPS32: andi [[T_E0:.*]],a0,0x1
351 ; MIPS32: andi [[R_E0:.*]],[[B_E0]],0x1
352 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
353 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
354 ; MIPS32: slt [[R_E0]],[[R_E0]],[[T_E0]]
355 ; MIPS32: andi [[T_E1:.*]],a1,0x1
356 ; MIPS32: andi [[R_E1:.*]],[[B_E1]],0x1
357 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
358 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
359 ; MIPS32: slt [[R_E1]],[[R_E1]],[[T_E1]]
360 ; MIPS32: andi [[T_E2:.*]],a2,0x1
361 ; MIPS32: andi [[R_E2:.*]],[[B_E2]],0x1
362 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
363 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
364 ; MIPS32: slt [[R_E2]],[[R_E2]],[[T_E2]]
365 ; MIPS32: andi [[T_E3:.*]],a3,0x1
366 ; MIPS32: andi [[R_E3:.*]],[[B_E3]],0x1
367 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
368 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
369 ; MIPS32: slt [[R_E3]],[[R_E3]],[[T_E3]]
122 } 370 }
123 371
124 define internal <4 x i1> @test_icmp_v4i1_sle(<4 x i1> %a, <4 x i1> %b) { 372 define internal <4 x i1> @test_icmp_v4i1_sle(<4 x i1> %a, <4 x i1> %b) {
125 entry: 373 entry:
126 %res = icmp sle <4 x i1> %a, %b 374 %res = icmp sle <4 x i1> %a, %b
127 ret <4 x i1> %res 375 ret <4 x i1> %res
128 ; CHECK-LABEL: test_icmp_v4i1_sle 376 ; CHECK-LABEL: test_icmp_v4i1_sle
129 ; CHECK: pcmpgtd 377 ; CHECK: pcmpgtd
130 ; CHECK: pxor 378 ; CHECK: pxor
379
380 ; MIPS32-LABEL: test_icmp_v4i1_sle
381 ; MIPS32: lw [[B_E0:.*]],
382 ; MIPS32: lw [[B_E1:.*]],
383 ; MIPS32: lw [[B_E2:.*]],
384 ; MIPS32: lw [[B_E3:.*]],
385 ; MIPS32: andi [[T_E0:.*]],a0,0x1
386 ; MIPS32: andi [[R_E0:.*]],[[B_E0]],0x1
387 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
388 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
389 ; MIPS32: slt [[R_E0]],[[R_E0]],[[T_E0]]
390 ; MIPS32: xori [[R_E0]],[[R_E0]],0x1
391 ; MIPS32: andi [[T_E1:.*]],a1,0x1
392 ; MIPS32: andi [[R_E1:.*]],[[B_E1]],0x1
393 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
394 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
395 ; MIPS32: slt [[R_E1]],[[R_E1]],[[T_E1]]
396 ; MIPS32: xori [[R_E1]],[[R_E1]],0x1
397 ; MIPS32: andi [[T_E2:.*]],a2,0x1
398 ; MIPS32: andi [[R_E2:.*]],[[B_E2]],0x1
399 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
400 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
401 ; MIPS32: slt [[R_E2]],[[R_E2]],[[T_E2]]
402 ; MIPS32: xori [[R_E2]],[[R_E2]],0x1
403 ; MIPS32: andi [[T_E3:.*]],a3,0x1
404 ; MIPS32: andi [[R_E3:.*]],[[B_E3]],0x1
405 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
406 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
407 ; MIPS32: slt [[R_E3]],[[R_E3]],[[T_E3]]
408 ; MIPS32: xori [[R_E3]],[[R_E3]],0x1
131 } 409 }
132 410
133 define internal <4 x i1> @test_icmp_v4i1_slt(<4 x i1> %a, <4 x i1> %b) { 411 define internal <4 x i1> @test_icmp_v4i1_slt(<4 x i1> %a, <4 x i1> %b) {
134 entry: 412 entry:
135 %res = icmp slt <4 x i1> %a, %b 413 %res = icmp slt <4 x i1> %a, %b
136 ret <4 x i1> %res 414 ret <4 x i1> %res
137 ; CHECK-LABEL: test_icmp_v4i1_slt 415 ; CHECK-LABEL: test_icmp_v4i1_slt
138 ; CHECK: pcmpgtd 416 ; CHECK: pcmpgtd
417
418 ; MIPS32-LABEL: test_icmp_v4i1_slt
419 ; MIPS32: lw [[B_E0:.*]],
420 ; MIPS32: lw [[B_E1:.*]],
421 ; MIPS32: lw [[B_E2:.*]],
422 ; MIPS32: lw [[B_E3:.*]],
423 ; MIPS32: andi [[R_E0:.*]],a0,0x1
424 ; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1
425 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
426 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
427 ; MIPS32: slt [[R_E0]],[[R_E0]],[[T_E0]]
428 ; MIPS32: andi [[R_E1:.*]],a1,0x1
429 ; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1
430 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
431 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
432 ; MIPS32: slt [[R_E1]],[[R_E1]],[[T_E1]]
433 ; MIPS32: andi [[R_E2:.*]],a2,0x1
434 ; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1
435 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
436 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
437 ; MIPS32: slt [[R_E2]],[[R_E2]],[[T_E2]]
438 ; MIPS32: andi [[R_E3:.*]],a3,0x1
439 ; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1
440 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
441 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
442 ; MIPS32: slt [[R_E3]],[[R_E3]],[[T_E3]]
443 ; MIPS32: move v0,[[R_E0]]
444 ; MIPS32: move v1,[[R_E1]]
445 ; MIPS32: move a0,[[R_E2]]
446 ; MIPS32: move a1,[[R_E3]]
139 } 447 }
140 448
141 define internal <4 x i1> @test_icmp_v4i1_uge(<4 x i1> %a, <4 x i1> %b) { 449 define internal <4 x i1> @test_icmp_v4i1_uge(<4 x i1> %a, <4 x i1> %b) {
142 entry: 450 entry:
143 %res = icmp uge <4 x i1> %a, %b 451 %res = icmp uge <4 x i1> %a, %b
144 ret <4 x i1> %res 452 ret <4 x i1> %res
145 ; CHECK-LABEL: test_icmp_v4i1_uge 453 ; CHECK-LABEL: test_icmp_v4i1_uge
146 ; CHECK: pxor 454 ; CHECK: pxor
147 ; CHECK: pcmpgtd 455 ; CHECK: pcmpgtd
148 ; CHECK: pxor 456 ; CHECK: pxor
457
458 ; MIPS32-LABEL: test_icmp_v4i1_uge
459 ; MIPS32: lw [[B_E0:.*]],
460 ; MIPS32: lw [[B_E1:.*]],
461 ; MIPS32: lw [[B_E2:.*]],
462 ; MIPS32: lw [[B_E3:.*]],
463 ; MIPS32: andi [[R_E0:.*]],a0,0x1
464 ; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1
465 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
466 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
467 ; MIPS32: sltu [[R_E0]],[[R_E0]],[[T_E0]]
468 ; MIPS32: xori [[R_E0]],[[R_E0]],0x1
469 ; MIPS32: andi [[R_E1:.*]],a1,0x1
470 ; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1
471 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
472 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
473 ; MIPS32: sltu [[R_E1]],[[R_E1]],[[T_E1]]
474 ; MIPS32: xori [[R_E1]],[[R_E1]],0x1
475 ; MIPS32: andi [[R_E2:.*]],a2,0x1
476 ; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1
477 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
478 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
479 ; MIPS32: sltu [[R_E2]],[[R_E2]],[[T_E2]]
480 ; MIPS32: xori [[R_E2]],[[R_E2]],0x1
481 ; MIPS32: andi [[R_E3:.*]],a3,0x1
482 ; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1
483 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
484 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
485 ; MIPS32: sltu [[R_E3]],[[R_E3]],[[T_E3]]
486 ; MIPS32: xori [[R_E3]],[[R_E3]],0x1
487 ; MIPS32: move v0,[[R_E0]]
488 ; MIPS32: move v1,[[R_E1]]
489 ; MIPS32: move a0,[[R_E2]]
490 ; MIPS32: move a1,[[R_E3]]
149 } 491 }
150 492
151 define internal <4 x i1> @test_icmp_v4i1_ugt(<4 x i1> %a, <4 x i1> %b) { 493 define internal <4 x i1> @test_icmp_v4i1_ugt(<4 x i1> %a, <4 x i1> %b) {
152 entry: 494 entry:
153 %res = icmp ugt <4 x i1> %a, %b 495 %res = icmp ugt <4 x i1> %a, %b
154 ret <4 x i1> %res 496 ret <4 x i1> %res
155 ; CHECK-LABEL: test_icmp_v4i1_ugt 497 ; CHECK-LABEL: test_icmp_v4i1_ugt
156 ; CHECK: pxor 498 ; CHECK: pxor
157 ; CHECK: pcmpgtd 499 ; CHECK: pcmpgtd
500
501 ; MIPS32-LABEL: test_icmp_v4i1_ugt
502 ; MIPS32: lw [[B_E0:.*]],
503 ; MIPS32: lw [[B_E1:.*]],
504 ; MIPS32: lw [[B_E2:.*]],
505 ; MIPS32: lw [[B_E3:.*]],
506 ; MIPS32: andi [[T_E0:.*]],a0,0x1
507 ; MIPS32: andi [[R_E0:.*]],[[B_E0]],0x1
508 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
509 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
510 ; MIPS32: sltu [[R_E0]],[[R_E0]],[[T_E0]]
511 ; MIPS32: andi [[T_E1:.*]],a1,0x1
512 ; MIPS32: andi [[R_E1:.*]],[[B_E1]],0x1
513 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
514 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
515 ; MIPS32: sltu [[R_E1]],[[R_E1]],[[T_E1]]
516 ; MIPS32: andi [[T_E2:.*]],a2,0x1
517 ; MIPS32: andi [[R_E2:.*]],[[B_E2]],0x1
518 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
519 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
520 ; MIPS32: sltu [[R_E2]],[[R_E2]],[[T_E2]]
521 ; MIPS32: andi [[T_E3:.*]],a3,0x1
522 ; MIPS32: andi [[R_E3:.*]],[[B_E3]],0x1
523 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
524 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
525 ; MIPS32: sltu [[R_E3]],[[R_E3]],[[T_E3]]
158 } 526 }
159 527
160 define internal <4 x i1> @test_icmp_v4i1_ule(<4 x i1> %a, <4 x i1> %b) { 528 define internal <4 x i1> @test_icmp_v4i1_ule(<4 x i1> %a, <4 x i1> %b) {
161 entry: 529 entry:
162 %res = icmp ule <4 x i1> %a, %b 530 %res = icmp ule <4 x i1> %a, %b
163 ret <4 x i1> %res 531 ret <4 x i1> %res
164 ; CHECK-LABEL: test_icmp_v4i1_ule 532 ; CHECK-LABEL: test_icmp_v4i1_ule
165 ; CHECK: pxor 533 ; CHECK: pxor
166 ; CHECK: pcmpgtd 534 ; CHECK: pcmpgtd
167 ; CHECK: pxor 535 ; CHECK: pxor
536
537 ; MIPS32-LABEL: test_icmp_v4i1_ule
538 ; MIPS32: lw [[B_E0:.*]],
539 ; MIPS32: lw [[B_E1:.*]],
540 ; MIPS32: lw [[B_E2:.*]],
541 ; MIPS32: lw [[B_E3:.*]],
542 ; MIPS32: andi [[T_E0:.*]],a0,0x1
543 ; MIPS32: andi [[R_E0:.*]],[[B_E0]],0x1
544 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
545 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
546 ; MIPS32: sltu [[R_E0]],[[R_E0]],[[T_E0]]
547 ; MIPS32: xori [[R_E0]],[[R_E0]],0x1
548 ; MIPS32: andi [[T_E1:.*]],a1,0x1
549 ; MIPS32: andi [[R_E1:.*]],[[B_E1]],0x1
550 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
551 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
552 ; MIPS32: sltu [[R_E1]],[[R_E1]],[[T_E1]]
553 ; MIPS32: xori [[R_E1]],[[R_E1]],0x1
554 ; MIPS32: andi [[T_E2:.*]],a2,0x1
555 ; MIPS32: andi [[R_E2:.*]],[[B_E2]],0x1
556 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
557 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
558 ; MIPS32: sltu [[R_E2]],[[R_E2]],[[T_E2]]
559 ; MIPS32: xori [[R_E2]],[[R_E2]],0x1
560 ; MIPS32: andi [[T_E3:.*]],a3,0x1
561 ; MIPS32: andi [[R_E3:.*]],[[B_E3]],0x1
562 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
563 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
564 ; MIPS32: sltu [[R_E3]],[[R_E3]],[[T_E3]]
565 ; MIPS32: xori [[R_E3]],[[R_E3]],0x1
168 } 566 }
169 567
170 define internal <4 x i1> @test_icmp_v4i1_ult(<4 x i1> %a, <4 x i1> %b) { 568 define internal <4 x i1> @test_icmp_v4i1_ult(<4 x i1> %a, <4 x i1> %b) {
171 entry: 569 entry:
172 %res = icmp ult <4 x i1> %a, %b 570 %res = icmp ult <4 x i1> %a, %b
173 ret <4 x i1> %res 571 ret <4 x i1> %res
174 ; CHECK-LABEL: test_icmp_v4i1_ult 572 ; CHECK-LABEL: test_icmp_v4i1_ult
175 ; CHECK: pxor 573 ; CHECK: pxor
176 ; CHECK: pcmpgtd 574 ; CHECK: pcmpgtd
575
576 ; MIPS32-LABEL: test_icmp_v4i1_ult
577 ; MIPS32: lw [[B_E0:.*]],
578 ; MIPS32: lw [[B_E1:.*]],
579 ; MIPS32: lw [[B_E2:.*]],
580 ; MIPS32: lw [[B_E3:.*]],
581 ; MIPS32: andi [[R_E0:.*]],a0,0x1
582 ; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1
583 ; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
584 ; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
585 ; MIPS32: sltu [[R_E0]],[[R_E0]],[[T_E0]]
586 ; MIPS32: andi [[R_E1:.*]],a1,0x1
587 ; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1
588 ; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
589 ; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
590 ; MIPS32: sltu [[R_E1]],[[R_E1]],[[T_E1]]
591 ; MIPS32: andi [[R_E2:.*]],a2,0x1
592 ; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1
593 ; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
594 ; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
595 ; MIPS32: sltu [[R_E2]],[[R_E2]],[[T_E2]]
596 ; MIPS32: andi [[R_E3:.*]],a3,0x1
597 ; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1
598 ; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
599 ; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
600 ; MIPS32: sltu [[R_E3]],[[R_E3]],[[T_E3]]
601 ; MIPS32: move v0,[[R_E0]]
602 ; MIPS32: move v1,[[R_E1]]
603 ; MIPS32: move a0,[[R_E2]]
604 ; MIPS32: move a1,[[R_E3]]
177 } 605 }
178 606
179 define internal <8 x i1> @test_icmp_v8i16_eq(<8 x i16> %a, <8 x i16> %b) { 607 define internal <8 x i1> @test_icmp_v8i16_eq(<8 x i16> %a, <8 x i16> %b) {
180 entry: 608 entry:
181 %res = icmp eq <8 x i16> %a, %b 609 %res = icmp eq <8 x i16> %a, %b
182 ret <8 x i1> %res 610 ret <8 x i1> %res
183 ; CHECK-LABEL: test_icmp_v8i16_eq 611 ; CHECK-LABEL: test_icmp_v8i16_eq
184 ; CHECK: pcmpeqw 612 ; CHECK: pcmpeqw
613
614 ; MIPS32-LABEL: test_icmp_v8i16_eq
615 ; MIPS32: lw [[B_E0:.*]],
616 ; MIPS32: lw [[B_E1:.*]],
617 ; MIPS32: lw [[B_E2:.*]],
618 ; MIPS32: lw [[B_E3:.*]],
619 ; MIPS32: move [[T1_E0:.*]],zero
620 ; MIPS32: move [[T1_E1:.*]],zero
621 ; MIPS32: move [[T1_E2:.*]],zero
622 ; MIPS32: move [[T1_E3:.*]],zero
623 ; *** icmp a[0] and b[0] ***
624 ; MIPS32: andi [[T2:.*]],a0,0xffff
625 ; MIPS32: andi [[T3:.*]],[[B_E0]],0xffff
626 ; MIPS32: sll [[T2]],[[T2]],0x10
627 ; MIPS32: sll [[T3]],[[T3]],0x10
628 ; MIPS32: xor [[T2]],[[T2]],[[T3]]
629 ; MIPS32: sltiu [[T2]],[[T2]],1
630 ; MIPS32: andi [[T2]],[[T2]],0xffff
631 ; MIPS32: srl [[T4:.*]],[[T1_E0]],0x10
632 ; MIPS32: sll [[T4]],[[T4]],0x10
633 ; MIPS32: or [[T2]],[[T2]],[[T4]]
634 ; *** icmp a[1] and b[1] ***
635 ; MIPS32: srl [[R_E0:.*]],a0,0x10
636 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
637 ; MIPS32: sll [[R_E0]],[[R_E0]],0x10
638 ; MIPS32: sll [[T5]],[[T5]],0x10
639 ; MIPS32: xor [[R_E0]],[[R_E0]],[[T5]]
640 ; MIPS32: sltiu [[R_E0]],[[R_E0]],1
641 ; MIPS32: sll [[R_E0]],[[R_E0]],0x10
642 ; MIPS32: sll [[T2]],[[T2]],0x10
643 ; MIPS32: srl [[T2]],[[T2]],0x10
644 ; MIPS32: or [[R_E0]],[[R_E0]],[[T2]]
645 ; *** icmp a[2] and b[2] ***
646 ; MIPS32: andi [[T2:.*]],a1,0xffff
647 ; MIPS32: andi [[T3:.*]],[[B_E1]],0xffff
648 ; MIPS32: sll [[T2]],[[T2]],0x10
649 ; MIPS32: sll [[T3]],[[T3]],0x10
650 ; MIPS32: xor [[T2]],[[T2]],[[T3]]
651 ; MIPS32: sltiu [[T2]],[[T2]],1
652 ; MIPS32: andi [[T2]],[[T2]],0xffff
653 ; MIPS32: srl [[T4:.*]],[[T1_E1]],0x10
654 ; MIPS32: sll [[T4]],[[T4]],0x10
655 ; MIPS32: or [[T2]],[[T2]],[[T4]]
656 ; *** icmp a[3] and b[3] ***
657 ; MIPS32: srl [[R_E1:.*]],a1,0x10
658 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
659 ; MIPS32: sll [[R_E1]],[[R_E1]],0x10
660 ; MIPS32: sll [[T5]],[[T5]],0x10
661 ; MIPS32: xor [[R_E1]],[[R_E1]],[[T5]]
662 ; MIPS32: sltiu [[R_E1]],[[R_E1]],1
663 ; MIPS32: sll [[R_E1]],[[R_E1]],0x10
664 ; MIPS32: sll [[T2]],[[T2]],0x10
665 ; MIPS32: srl [[T2]],[[T2]],0x10
666 ; MIPS32: or [[R_E1]],[[R_E1]],[[T2]]
667 ; *** icmp a[4] and b[4] ***
668 ; MIPS32: andi [[T2:.*]],a2,0xffff
669 ; MIPS32: andi [[T3:.*]],[[B_E2]],0xffff
670 ; MIPS32: sll [[T2]],[[T2]],0x10
671 ; MIPS32: sll [[T3]],[[T3]],0x10
672 ; MIPS32: xor [[T2]],[[T2]],[[T3]]
673 ; MIPS32: sltiu [[T2]],[[T2]],1
674 ; MIPS32: andi [[T2]],[[T2]],0xffff
675 ; MIPS32: srl [[T4:.*]],[[T1_E2]],0x10
676 ; MIPS32: sll [[T4]],[[T4]],0x10
677 ; MIPS32: or [[T2]],[[T2]],[[T4]]
678 ; *** icmp a[5] and b[5] ***
679 ; MIPS32: srl [[R_E2:.*]],a2,0x10
680 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
681 ; MIPS32: sll [[R_E2]],[[R_E2]],0x10
682 ; MIPS32: sll [[T5]],[[T5]],0x10
683 ; MIPS32: xor [[R_E2]],[[R_E2]],[[T5]]
684 ; MIPS32: sltiu [[R_E2]],[[R_E2]],1
685 ; MIPS32: sll [[R_E2]],[[R_E2]],0x10
686 ; MIPS32: sll [[T2]],[[T2]],0x10
687 ; MIPS32: srl [[T2]],[[T2]],0x10
688 ; MIPS32: or [[R_E2]],[[R_E2]],[[T2]]
689 ; *** icmp a[6] and b[6] ***
690 ; MIPS32: andi [[T2:.*]],a3,0xffff
691 ; MIPS32: andi [[T3:.*]],[[B_E3]],0xffff
692 ; MIPS32: sll [[T2]],[[T2]],0x10
693 ; MIPS32: sll [[T3]],[[T3]],0x10
694 ; MIPS32: xor [[T2]],[[T2]],[[T3]]
695 ; MIPS32: sltiu [[T2]],[[T2]],1
696 ; MIPS32: andi [[T2]],[[T2]],0xffff
697 ; MIPS32: srl [[T5:.*]],[[T1_E3]],0x10
698 ; MIPS32: sll [[T5]],[[T5]],0x10
699 ; MIPS32: or [[T2]],[[T2]],[[T5]]
700 ; *** icmp a[7] and b[7] ***
701 ; MIPS32: srl [[R_E3:.*]],a3,0x10
702 ; MIPS32: srl [[T6:.*]],[[B_E3]],0x10
703 ; MIPS32: sll [[R_E3]],[[R_E3]],0x10
704 ; MIPS32: sll [[T6]],[[T6]],0x10
705 ; MIPS32: xor [[R_E3]],[[R_E3]],[[T6]]
706 ; MIPS32: sltiu [[R_E3]],[[R_E3]],1
707 ; MIPS32: sll [[R_E3]],[[R_E3]],0x10
708 ; MIPS32: sll [[T2]],[[T2]],0x10
709 ; MIPS32: srl [[T2]],[[T2]],0x10
710 ; MIPS32: or [[R_E3]],[[R_E3]],[[T2]]
711 ; *** move result to $2:$3:$4:$5 ***
712 ; MIPS32: move v0,[[R_E0]]
713 ; MIPS32: move v1,[[R_E1]]
714 ; MIPS32: move a0,[[R_E2]]
715 ; MIPS32: move a1,[[R_E3]]
185 } 716 }
186 717
187 define internal <8 x i1> @test_icmp_v8i16_ne(<8 x i16> %a, <8 x i16> %b) { 718 define internal <8 x i1> @test_icmp_v8i16_ne(<8 x i16> %a, <8 x i16> %b) {
188 entry: 719 entry:
189 %res = icmp ne <8 x i16> %a, %b 720 %res = icmp ne <8 x i16> %a, %b
190 ret <8 x i1> %res 721 ret <8 x i1> %res
191 ; CHECK-LABEL: test_icmp_v8i16_ne 722 ; CHECK-LABEL: test_icmp_v8i16_ne
192 ; CHECK: pcmpeqw 723 ; CHECK: pcmpeqw
193 ; CHECK: pxor 724 ; CHECK: pxor
725
726 ; MIPS32-LABEL: test_icmp_v8i16_ne
727 ; MIPS32: lw [[B_E0:.*]],
728 ; MIPS32: lw [[B_E1:.*]],
729 ; MIPS32: lw [[B_E2:.*]],
730 ; MIPS32: lw [[B_E3:.*]],
731 ; MIPS32: move [[T1_E0:.*]],zero
732 ; MIPS32: move [[T1_E1:.*]],zero
733 ; MIPS32: move [[T1_E2:.*]],zero
734 ; MIPS32: move [[T1_E3:.*]],zero
735 ; *** icmp a[0] and b[0] ***
736 ; MIPS32: andi [[T2:.*]],a0,0xffff
737 ; MIPS32: andi [[T3:.*]],[[B_E0]],0xffff
738 ; MIPS32: sll [[T2]],[[T2]],0x10
739 ; MIPS32: sll [[T3]],[[T3]],0x10
740 ; MIPS32: xor [[T2]],[[T2]],[[T3]]
741 ; MIPS32: sltu [[T2]],zero,[[T2]]
742 ; MIPS32: andi [[T2]],[[T2]],0xffff
743 ; MIPS32: srl [[T4:.*]],[[T1_E0]],0x10
744 ; MIPS32: sll [[T4]],[[T4]],0x10
745 ; MIPS32: or [[T2]],[[T2]],[[T4]]
746 ; *** icmp a[1] and b[1] ***
747 ; MIPS32: srl [[R_E0:.*]],a0,0x10
748 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
749 ; MIPS32: sll [[R_E0]],[[R_E0]],0x10
750 ; MIPS32: sll [[T5]],[[T5]],0x10
751 ; MIPS32: xor [[R_E0]],[[R_E0]],[[T5]]
752 ; MIPS32: sltu [[R_E0]],zero,[[R_E0]]
753 ; MIPS32: sll [[R_E0]],[[R_E0]],0x10
754 ; MIPS32: sll [[T2]],[[T2]],0x10
755 ; MIPS32: srl [[T2]],[[T2]],0x10
756 ; MIPS32: or [[R_E0]],[[R_E0]],[[T2]]
757 ; *** icmp a[2] and b[2] ***
758 ; MIPS32: andi [[T2:.*]],a1,0xffff
759 ; MIPS32: andi [[T3:.*]],[[B_E1]],0xffff
760 ; MIPS32: sll [[T2]],[[T2]],0x10
761 ; MIPS32: sll [[T3]],[[T3]],0x10
762 ; MIPS32: xor [[T2]],[[T2]],[[T3]]
763 ; MIPS32: sltu [[T2]],zero,[[T2]]
764 ; MIPS32: andi [[T2]],[[T2]],0xffff
765 ; MIPS32: srl [[T4:.*]],[[T1_E1]],0x10
766 ; MIPS32: sll [[T4]],[[T4]],0x10
767 ; MIPS32: or [[T2]],[[T2]],[[T4]]
768 ; *** icmp a[3] and b[3] ***
769 ; MIPS32: srl [[R_E1:.*]],a1,0x10
770 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
771 ; MIPS32: sll [[R_E1]],[[R_E1]],0x10
772 ; MIPS32: sll [[T5]],[[T5]],0x10
773 ; MIPS32: xor [[R_E1]],[[R_E1]],[[T5]]
774 ; MIPS32: sltu [[R_E1]],zero,[[R_E1]]
775 ; MIPS32: sll [[R_E1]],[[R_E1]],0x10
776 ; MIPS32: sll [[T2]],[[T2]],0x10
777 ; MIPS32: srl [[T2]],[[T2]],0x10
778 ; MIPS32: or [[R_E1]],[[R_E1]],[[T2]]
779 ; *** icmp a[4] and b[4] ***
780 ; MIPS32: andi [[T2:.*]],a2,0xffff
781 ; MIPS32: andi [[T3:.*]],[[B_E2]],0xffff
782 ; MIPS32: sll [[T2]],[[T2]],0x10
783 ; MIPS32: sll [[T3]],[[T3]],0x10
784 ; MIPS32: xor [[T2]],[[T2]],[[T3]]
785 ; MIPS32: sltu [[T2]],zero,[[T2]]
786 ; MIPS32: andi [[T2]],[[T2]],0xffff
787 ; MIPS32: srl [[T4:.*]],[[T1_E2]],0x10
788 ; MIPS32: sll [[T4]],[[T4]],0x10
789 ; MIPS32: or [[T2]],[[T2]],[[T4]]
790 ; *** icmp a[5] and b[5] ***
791 ; MIPS32: srl [[R_E2:.*]],a2,0x10
792 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
793 ; MIPS32: sll [[R_E2]],[[R_E2]],0x10
794 ; MIPS32: sll [[T5]],[[T5]],0x10
795 ; MIPS32: xor [[R_E2]],[[R_E2]],[[T5]]
796 ; MIPS32: sltu [[R_E2]],zero,[[R_E2]]
797 ; MIPS32: sll [[R_E2]],[[R_E2]],0x10
798 ; MIPS32: sll [[T2]],[[T2]],0x10
799 ; MIPS32: srl [[T2]],[[T2]],0x10
800 ; MIPS32: or [[R_E2]],[[R_E2]],[[T2]]
801 ; *** icmp a[6] and b[6] ***
802 ; MIPS32: andi [[T2:.*]],a3,0xffff
803 ; MIPS32: andi [[T3:.*]],[[B_E3]],0xffff
804 ; MIPS32: sll [[T2]],[[T2]],0x10
805 ; MIPS32: sll [[T3]],[[T3]],0x10
806 ; MIPS32: xor [[T2]],[[T2]],[[T3]]
807 ; MIPS32: sltu [[T2]],zero,[[T2]]
808 ; MIPS32: andi [[T2]],[[T2]],0xffff
809 ; MIPS32: srl [[T5:.*]],[[T1_E3]],0x10
810 ; MIPS32: sll [[T5]],[[T5]],0x10
811 ; MIPS32: or [[T2]],[[T2]],[[T5]]
812 ; *** icmp a[7] and b[7] ***
813 ; MIPS32: srl [[R_E3:.*]],a3,0x10
814 ; MIPS32: srl [[T6:.*]],[[B_E3]],0x10
815 ; MIPS32: sll [[R_E3]],[[R_E3]],0x10
816 ; MIPS32: sll [[T6]],[[T6]],0x10
817 ; MIPS32: xor [[R_E3]],[[R_E3]],[[T6]]
818 ; MIPS32: sltu [[R_E3]],zero,[[R_E3]]
819 ; MIPS32: sll [[R_E3]],[[R_E3]],0x10
820 ; MIPS32: sll [[T2]],[[T2]],0x10
821 ; MIPS32: srl [[T2]],[[T2]],0x10
822 ; MIPS32: or [[R_E3]],[[R_E3]],[[T2]]
823 ; *** move result to $2:$3:$4:$5 ***
824 ; MIPS32: move v0,[[R_E0]]
825 ; MIPS32: move v1,[[R_E1]]
826 ; MIPS32: move a0,[[R_E2]]
827 ; MIPS32: move a1,[[R_E3]]
194 } 828 }
195 829
196 define internal <8 x i1> @test_icmp_v8i16_sgt(<8 x i16> %a, <8 x i16> %b) { 830 define internal <8 x i1> @test_icmp_v8i16_sgt(<8 x i16> %a, <8 x i16> %b) {
197 entry: 831 entry:
198 %res = icmp sgt <8 x i16> %a, %b 832 %res = icmp sgt <8 x i16> %a, %b
199 ret <8 x i1> %res 833 ret <8 x i1> %res
200 ; CHECK-LABEL: test_icmp_v8i16_sgt 834 ; CHECK-LABEL: test_icmp_v8i16_sgt
201 ; CHECK: pcmpgtw 835 ; CHECK: pcmpgtw
836
837 ; MIPS32-LABEL: test_icmp_v8i16_sgt
838 ; MIPS32: lw [[B_E0:.*]],
839 ; MIPS32: lw [[B_E1:.*]],
840 ; MIPS32: lw [[B_E2:.*]],
841 ; MIPS32: lw [[B_E3:.*]],
842 ; MIPS32: move [[T1_E0:.*]],zero
843 ; MIPS32: move [[T1_E1:.*]],zero
844 ; MIPS32: move [[T1_E2:.*]],zero
845 ; MIPS32: move [[T1_E3:.*]],zero
846 ; MIPS32: andi [[T1:.*]],a0,0xffff
847 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
848 ; MIPS32: sll [[T1]],[[T1]],0x10
849 ; MIPS32: sll [[T2]],[[T2]],0x10
850 ; MIPS32: slt [[T2]],[[T2]],[[T1]]
851 ; MIPS32: andi [[T2]],[[T2]],0xffff
852 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
853 ; MIPS32: sll [[T3]],[[T3]],0x10
854 ; MIPS32: or [[T2]],[[T2]],[[T3]]
855 ; MIPS32: srl [[T4:.*]],a0,0x10
856 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
857 ; MIPS32: sll [[T4]],[[T4]],0x10
858 ; MIPS32: sll [[T5]],[[T5]],0x10
859 ; MIPS32: slt [[T5]],[[T5]],[[T4]]
860 ; MIPS32: sll [[T5]],[[T5]],0x10
861 ; MIPS32: sll [[T2]],[[T2]],0x10
862 ; MIPS32: srl [[T2]],[[T2]],0x10
863 ; MIPS32: or [[R_E0:.*]],[[T5]],[[T2]]
864 ; MIPS32: andi [[T4]],a1,0xffff
865 ; MIPS32: andi [[T3]],[[B_E1]],0xffff
866 ; MIPS32: sll [[T4]],[[T4]],0x10
867 ; MIPS32: sll [[T3]],[[T3]],0x10
868 ; MIPS32: slt [[T3]],[[T3]],[[T4]]
869 ; MIPS32: andi [[T3]],[[T3]],0xffff
870 ; MIPS32: srl [[T6:.*]],[[T1_E1]],0x10
871 ; MIPS32: sll [[T6]],[[T6]],0x10
872 ; MIPS32: or [[T3]],[[T3]],[[T6]]
873 ; MIPS32: srl [[T7:.*]],a1,0x10
874 ; MIPS32: srl [[T8:.*]],[[B_E1]],0x10
875 ; MIPS32: sll [[T7]],[[T7]],0x10
876 ; MIPS32: sll [[T8]],[[T8]],0x10
877 ; MIPS32: slt [[T8]],[[T8]],[[T7]]
878 ; MIPS32: sll [[T8]],[[T8]],0x10
879 ; MIPS32: sll [[T3]],[[T3]],0x10
880 ; MIPS32: srl [[T3]],[[T3]],0x10
881 ; MIPS32: or [[R_E1:.*]],[[T8]],[[T3]]
882 ; MIPS32: andi [[T4]],a2,0xffff
883 ; MIPS32: andi [[T7]],[[B_E2]],0xffff
884 ; MIPS32: sll [[T4]],[[T4]],0x10
885 ; MIPS32: sll [[T7]],[[T7]],0x10
886 ; MIPS32: slt [[T7]],[[T7]],[[T4]]
887 ; MIPS32: andi [[T7]],[[T7]],0xffff
888 ; MIPS32: srl [[T9:.*]],[[T1_E2]],0x10
889 ; MIPS32: sll [[T9]],[[T9]],0x10
890 ; MIPS32: or [[T7]],[[T7]],[[T9]]
891 ; MIPS32: srl [[T10:.*]],a2,0x10
892 ; MIPS32: srl [[T11:.*]],[[B_E2]],0x10
893 ; MIPS32: sll [[T10]],[[T10]],0x10
894 ; MIPS32: sll [[T11]],[[T11]],0x10
895 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
896 ; MIPS32: sll [[T11]],[[T11]],0x10
897 ; MIPS32: sll [[T7]],[[T7]],0x10
898 ; MIPS32: srl [[T7]],[[T7]],0x10
899 ; MIPS32: or [[R_E2:.*]],[[T11]],[[T7]]
900 ; MIPS32: andi [[T4]],a3,0xffff
901 ; MIPS32: andi [[T7]],[[B_E3]],0xffff
902 ; MIPS32: sll [[T4]],[[T4]],0x10
903 ; MIPS32: sll [[T7]],[[T7]],0x10
904 ; MIPS32: slt [[T7]],[[T7]],[[T4]]
905 ; MIPS32: andi [[T7]],[[T7]],0xffff
906 ; MIPS32: srl [[T12:.*]],[[T1_E3]],0x10
907 ; MIPS32: sll [[T12]],[[T12]],0x10
908 ; MIPS32: or [[T7]],[[T7]],[[T12]]
909 ; MIPS32: srl [[T13:.*]],a3,0x10
910 ; MIPS32: srl [[T14:.*]],[[B_E3]],0x10
911 ; MIPS32: sll [[T13]],[[T13]],0x10
912 ; MIPS32: sll [[T14]],[[T14]],0x10
913 ; MIPS32: slt [[T14]],[[T14]],[[T13]]
914 ; MIPS32: sll [[T14]],[[T14]],0x10
915 ; MIPS32: sll [[T7]],[[T7]],0x10
916 ; MIPS32: srl [[T7]],[[T7]],0x10
917 ; MIPS32: or [[R_E3:.*]],[[T14]],[[T7]]
202 } 918 }
203 919
204 define internal <8 x i1> @test_icmp_v8i16_sle(<8 x i16> %a, <8 x i16> %b) { 920 define internal <8 x i1> @test_icmp_v8i16_sle(<8 x i16> %a, <8 x i16> %b) {
205 entry: 921 entry:
206 %res = icmp sle <8 x i16> %a, %b 922 %res = icmp sle <8 x i16> %a, %b
207 ret <8 x i1> %res 923 ret <8 x i1> %res
208 ; CHECK-LABEL: test_icmp_v8i16_sle 924 ; CHECK-LABEL: test_icmp_v8i16_sle
209 ; CHECK: pcmpgtw 925 ; CHECK: pcmpgtw
210 ; CHECK: pxor 926 ; CHECK: pxor
927
928 ; MIPS32-LABEL: test_icmp_v8i16_sle
929 ; MIPS32: lw [[B_E0:.*]],
930 ; MIPS32: lw [[B_E1:.*]],
931 ; MIPS32: lw [[B_E2:.*]],
932 ; MIPS32: lw [[B_E3:.*]],
933 ; MIPS32: move [[T1_E0:.*]],zero
934 ; MIPS32: move [[T1_E1:.*]],zero
935 ; MIPS32: move [[T1_E2:.*]],zero
936 ; MIPS32: move [[T1_E3:.*]],zero
937 ; MIPS32: andi [[T1:.*]],a0,0xffff
938 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
939 ; MIPS32: sll [[T1]],[[T1]],0x10
940 ; MIPS32: sll [[T2]],[[T2]],0x10
941 ; MIPS32: slt [[T2]],[[T2]],[[T1]]
942 ; MIPS32: xori [[T2]],[[T2]],0x1
943 ; MIPS32: andi [[T2]],[[T2]],0xffff
944 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
945 ; MIPS32: sll [[T3]],[[T3]],0x10
946 ; MIPS32: or [[T2]],[[T2]],[[T3]]
947 ; MIPS32: srl [[T4:.*]],a0,0x10
948 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
949 ; MIPS32: sll [[T4]],[[T4]],0x10
950 ; MIPS32: sll [[T5]],[[T5]],0x10
951 ; MIPS32: slt [[T5]],[[T5]],[[T4]]
952 ; MIPS32: xori [[T5]],[[T5]],0x1
953 ; MIPS32: sll [[T5]],[[T5]],0x10
954 ; MIPS32: sll [[T2]],[[T2]],0x10
955 ; MIPS32: srl [[T2]],[[T2]],0x10
956 ; MIPS32: or [[R_E0:.*]],[[T5]],[[T2]]
957 ; MIPS32: andi [[T4]],a1,0xffff
958 ; MIPS32: andi [[T3]],[[B_E1]],0xffff
959 ; MIPS32: sll [[T4]],[[T4]],0x10
960 ; MIPS32: sll [[T3]],[[T3]],0x10
961 ; MIPS32: slt [[T3]],[[T3]],[[T4]]
962 ; MIPS32: xori [[T3]],[[T3]],0x1
963 ; MIPS32: andi [[T3]],[[T3]],0xffff
964 ; MIPS32: srl [[T6:.*]],[[T1_E1]],0x10
965 ; MIPS32: sll [[T6]],[[T6]],0x10
966 ; MIPS32: or [[T3]],[[T3]],[[T6]]
967 ; MIPS32: srl [[T7:.*]],a1,0x10
968 ; MIPS32: srl [[T8:.*]],[[B_E1]],0x10
969 ; MIPS32: sll [[T7]],[[T7]],0x10
970 ; MIPS32: sll [[T8]],[[T8]],0x10
971 ; MIPS32: slt [[T8]],[[T8]],[[T7]]
972 ; MIPS32: xori [[T8]],[[T8]],0x1
973 ; MIPS32: sll [[T8]],[[T8]],0x10
974 ; MIPS32: sll [[T3]],[[T3]],0x10
975 ; MIPS32: srl [[T3]],[[T3]],0x10
976 ; MIPS32: or [[R_E1:.*]],[[T8]],[[T3]]
977 ; MIPS32: andi [[T4]],a2,0xffff
978 ; MIPS32: andi [[T7]],[[B_E2]],0xffff
979 ; MIPS32: sll [[T4]],[[T4]],0x10
980 ; MIPS32: sll [[T7]],[[T7]],0x10
981 ; MIPS32: slt [[T7]],[[T7]],[[T4]]
982 ; MIPS32: xori [[T7]],[[T7]],0x1
983 ; MIPS32: andi [[T7]],[[T7]],0xffff
984 ; MIPS32: srl [[T9:.*]],[[T1_E2]],0x10
985 ; MIPS32: sll [[T9]],[[T9]],0x10
986 ; MIPS32: or [[T7]],[[T7]],[[T9]]
987 ; MIPS32: srl [[T10:.*]],a2,0x10
988 ; MIPS32: srl [[T11:.*]],[[B_E2]],0x10
989 ; MIPS32: sll [[T10]],[[T10]],0x10
990 ; MIPS32: sll [[T11]],[[T11]],0x10
991 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
992 ; MIPS32: xori [[T11]],[[T11]],0x1
993 ; MIPS32: sll [[T11]],[[T11]],0x10
994 ; MIPS32: sll [[T7]],[[T7]],0x10
995 ; MIPS32: srl [[T7]],[[T7]],0x10
996 ; MIPS32: or [[R_E2:.*]],[[T11]],[[T7]]
997 ; MIPS32: andi [[T4]],a3,0xffff
998 ; MIPS32: andi [[T7]],[[B_E3]],0xffff
999 ; MIPS32: sll [[T4]],[[T4]],0x10
1000 ; MIPS32: sll [[T7]],[[T7]],0x10
1001 ; MIPS32: slt [[T7]],[[T7]],[[T4]]
1002 ; MIPS32: xori [[T7]],[[T7]],0x1
1003 ; MIPS32: andi [[T7]],[[T7]],0xffff
1004 ; MIPS32: srl [[T12:.*]],[[T1_E3]],0x10
1005 ; MIPS32: sll [[T12]],[[T12]],0x10
1006 ; MIPS32: or [[T7]],[[T7]],[[T12]]
1007 ; MIPS32: srl [[T13:.*]],a3,0x10
1008 ; MIPS32: srl [[T14:.*]],[[B_E3]],0x10
1009 ; MIPS32: sll [[T13]],[[T13]],0x10
1010 ; MIPS32: sll [[T14]],[[T14]],0x10
1011 ; MIPS32: slt [[T14]],[[T14]],[[T13]]
1012 ; MIPS32: xori [[T14]],[[T14]],0x1
1013 ; MIPS32: sll [[T14]],[[T14]],0x10
1014 ; MIPS32: sll [[T7]],[[T7]],0x10
1015 ; MIPS32: srl [[T7]],[[T7]],0x10
1016 ; MIPS32: or [[R_E3:.*]],[[T14]],[[T7]]
211 } 1017 }
212 1018
213 define internal <8 x i1> @test_icmp_v8i16_slt(<8 x i16> %a, <8 x i16> %b) { 1019 define internal <8 x i1> @test_icmp_v8i16_slt(<8 x i16> %a, <8 x i16> %b) {
214 entry: 1020 entry:
215 %res = icmp slt <8 x i16> %a, %b 1021 %res = icmp slt <8 x i16> %a, %b
216 ret <8 x i1> %res 1022 ret <8 x i1> %res
217 ; CHECK-LABEL: test_icmp_v8i16_slt 1023 ; CHECK-LABEL: test_icmp_v8i16_slt
218 ; CHECK: pcmpgtw 1024 ; CHECK: pcmpgtw
1025
1026 ; MIPS32-LABEL: test_icmp_v8i16_slt
1027 ; MIPS32: lw [[B_E0:.*]],
1028 ; MIPS32: lw [[B_E1:.*]],
1029 ; MIPS32: lw [[B_E2:.*]],
1030 ; MIPS32: lw [[B_E3:.*]],
1031 ; MIPS32: move [[T1_E0:.*]],zero
1032 ; MIPS32: move [[T1_E1:.*]],zero
1033 ; MIPS32: move [[T1_E2:.*]],zero
1034 ; MIPS32: move [[T1_E3:.*]],zero
1035 ; MIPS32: andi [[T1:.*]],a0,0xffff
1036 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
1037 ; MIPS32: sll [[T1]],[[T1]],0x10
1038 ; MIPS32: sll [[T2]],[[T2]],0x10
1039 ; MIPS32: slt [[T1]],[[T1]],[[T2]]
1040 ; MIPS32: andi [[T1]],[[T1]],0xffff
1041 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
1042 ; MIPS32: sll [[T3]],[[T3]],0x10
1043 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1044 ; MIPS32: srl [[T4:.*]],a0,0x10
1045 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
1046 ; MIPS32: sll [[T4]],[[T4]],0x10
1047 ; MIPS32: sll [[T5]],[[T5]],0x10
1048 ; MIPS32: slt [[T4]],[[T4]],[[T5]]
1049 ; MIPS32: sll [[T4]],[[T4]],0x10
1050 ; MIPS32: sll [[T1]],[[T1]],0x10
1051 ; MIPS32: srl [[T1]],[[T1]],0x10
1052 ; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]]
1053 ; MIPS32: andi [[T1:.*]],a1,0xffff
1054 ; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
1055 ; MIPS32: sll [[T1]],[[T1]],0x10
1056 ; MIPS32: sll [[T2]],[[T2]],0x10
1057 ; MIPS32: slt [[T1]],[[T1]],[[T2]]
1058 ; MIPS32: andi [[T1]],[[T1]],0xffff
1059 ; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
1060 ; MIPS32: sll [[T3]],[[T3]],0x10
1061 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1062 ; MIPS32: srl [[T4:.*]],a1,0x10
1063 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
1064 ; MIPS32: sll [[T4]],[[T4]],0x10
1065 ; MIPS32: sll [[T5]],[[T5]],0x10
1066 ; MIPS32: slt [[T4]],[[T4]],[[T5]]
1067 ; MIPS32: sll [[T4]],[[T4]],0x10
1068 ; MIPS32: sll [[T1]],[[T1]],0x10
1069 ; MIPS32: srl [[T1]],[[T1]],0x10
1070 ; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]]
1071 ; MIPS32: andi [[T1:.*]],a2,0xffff
1072 ; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
1073 ; MIPS32: sll [[T1]],[[T1]],0x10
1074 ; MIPS32: sll [[T2]],[[T2]],0x10
1075 ; MIPS32: slt [[T1]],[[T1]],[[T2]]
1076 ; MIPS32: andi [[T1]],[[T1]],0xffff
1077 ; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
1078 ; MIPS32: sll [[T3]],[[T3]],0x10
1079 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1080 ; MIPS32: srl [[T4:.*]],a2,0x10
1081 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
1082 ; MIPS32: sll [[T4]],[[T4]],0x10
1083 ; MIPS32: sll [[T5]],[[T5]],0x10
1084 ; MIPS32: slt [[T4]],[[T4]],[[T5]]
1085 ; MIPS32: sll [[T4]],[[T4]],0x10
1086 ; MIPS32: sll [[T1]],[[T1]],0x10
1087 ; MIPS32: srl [[T1]],[[T1]],0x10
1088 ; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]]
1089 ; MIPS32: andi [[T1:.*]],a3,0xffff
1090 ; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
1091 ; MIPS32: sll [[T1]],[[T1]],0x10
1092 ; MIPS32: sll [[T2]],[[T2]],0x10
1093 ; MIPS32: slt [[T1]],[[T1]],[[T2]]
1094 ; MIPS32: andi [[T1]],[[T1]],0xffff
1095 ; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
1096 ; MIPS32: sll [[T3]],[[T3]],0x10
1097 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1098 ; MIPS32: srl [[T4:.*]],a3,0x10
1099 ; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
1100 ; MIPS32: sll [[T4]],[[T4]],0x10
1101 ; MIPS32: sll [[T5]],[[T5]],0x10
1102 ; MIPS32: slt [[T4]],[[T4]],[[T5]]
1103 ; MIPS32: sll [[T4]],[[T4]],0x10
1104 ; MIPS32: sll [[T1]],[[T1]],0x10
1105 ; MIPS32: srl [[T1]],[[T1]],0x10
1106 ; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]]
219 } 1107 }
220 1108
221 define internal <8 x i1> @test_icmp_v8i16_uge(<8 x i16> %a, <8 x i16> %b) { 1109 define internal <8 x i1> @test_icmp_v8i16_uge(<8 x i16> %a, <8 x i16> %b) {
222 entry: 1110 entry:
223 %res = icmp uge <8 x i16> %a, %b 1111 %res = icmp uge <8 x i16> %a, %b
224 ret <8 x i1> %res 1112 ret <8 x i1> %res
225 ; CHECK-LABEL: test_icmp_v8i16_uge 1113 ; CHECK-LABEL: test_icmp_v8i16_uge
226 ; CHECK: pxor 1114 ; CHECK: pxor
227 ; CHECK: pcmpgtw 1115 ; CHECK: pcmpgtw
228 ; CHECK: pxor 1116 ; CHECK: pxor
1117
1118 ; MIPS32-LABEL: test_icmp_v8i16_uge
1119 ; MIPS32: lw [[B_E0:.*]],
1120 ; MIPS32: lw [[B_E1:.*]],
1121 ; MIPS32: lw [[B_E2:.*]],
1122 ; MIPS32: lw [[B_E3:.*]],
1123 ; MIPS32: move [[T1_E0:.*]],zero
1124 ; MIPS32: move [[T1_E1:.*]],zero
1125 ; MIPS32: move [[T1_E2:.*]],zero
1126 ; MIPS32: move [[T1_E3:.*]],zero
1127 ; MIPS32: andi [[T1:.*]],a0,0xffff
1128 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
1129 ; MIPS32: sll [[T1]],[[T1]],0x10
1130 ; MIPS32: sll [[T2]],[[T2]],0x10
1131 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
1132 ; MIPS32: xori [[T1]],[[T1]],0x1
1133 ; MIPS32: andi [[T1]],[[T1]],0xffff
1134 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
1135 ; MIPS32: sll [[T3]],[[T3]],0x10
1136 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1137 ; MIPS32: srl [[T4:.*]],a0,0x10
1138 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
1139 ; MIPS32: sll [[T4]],[[T4]],0x10
1140 ; MIPS32: sll [[T5]],[[T5]],0x10
1141 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
1142 ; MIPS32: xori [[T4]],[[T4]],0x1
1143 ; MIPS32: sll [[T4]],[[T4]],0x10
1144 ; MIPS32: sll [[T1]],[[T1]],0x10
1145 ; MIPS32: srl [[T1]],[[T1]],0x10
1146 ; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]]
1147 ; MIPS32: andi [[T1:.*]],a1,0xffff
1148 ; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
1149 ; MIPS32: sll [[T1]],[[T1]],0x10
1150 ; MIPS32: sll [[T2]],[[T2]],0x10
1151 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
1152 ; MIPS32: xori [[T1]],[[T1]],0x1
1153 ; MIPS32: andi [[T1]],[[T1]],0xffff
1154 ; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
1155 ; MIPS32: sll [[T3]],[[T3]],0x10
1156 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1157 ; MIPS32: srl [[T4:.*]],a1,0x10
1158 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
1159 ; MIPS32: sll [[T4]],[[T4]],0x10
1160 ; MIPS32: sll [[T5]],[[T5]],0x10
1161 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
1162 ; MIPS32: xori [[T4]],[[T4]],0x1
1163 ; MIPS32: sll [[T4]],[[T4]],0x10
1164 ; MIPS32: sll [[T1]],[[T1]],0x10
1165 ; MIPS32: srl [[T1]],[[T1]],0x10
1166 ; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]]
1167 ; MIPS32: andi [[T1:.*]],a2,0xffff
1168 ; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
1169 ; MIPS32: sll [[T1]],[[T1]],0x10
1170 ; MIPS32: sll [[T2]],[[T2]],0x10
1171 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
1172 ; MIPS32: xori [[T1]],[[T1]],0x1
1173 ; MIPS32: andi [[T1]],[[T1]],0xffff
1174 ; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
1175 ; MIPS32: sll [[T3]],[[T3]],0x10
1176 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1177 ; MIPS32: srl [[T4:.*]],a2,0x10
1178 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
1179 ; MIPS32: sll [[T4]],[[T4]],0x10
1180 ; MIPS32: sll [[T5]],[[T5]],0x10
1181 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
1182 ; MIPS32: xori [[T4]],[[T4]],0x1
1183 ; MIPS32: sll [[T4]],[[T4]],0x10
1184 ; MIPS32: sll [[T1]],[[T1]],0x10
1185 ; MIPS32: srl [[T1]],[[T1]],0x10
1186 ; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]]
1187 ; MIPS32: andi [[T1:.*]],a3,0xffff
1188 ; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
1189 ; MIPS32: sll [[T1]],[[T1]],0x10
1190 ; MIPS32: sll [[T2]],[[T2]],0x10
1191 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
1192 ; MIPS32: xori [[T1]],[[T1]],0x1
1193 ; MIPS32: andi [[T1]],[[T1]],0xffff
1194 ; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
1195 ; MIPS32: sll [[T3]],[[T3]],0x10
1196 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1197 ; MIPS32: srl [[T4:.*]],a3,0x10
1198 ; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
1199 ; MIPS32: sll [[T4]],[[T4]],0x10
1200 ; MIPS32: sll [[T5]],[[T5]],0x10
1201 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
1202 ; MIPS32: xori [[T4]],[[T4]],0x1
1203 ; MIPS32: sll [[T4]],[[T4]],0x10
1204 ; MIPS32: sll [[T1]],[[T1]],0x10
1205 ; MIPS32: srl [[T1]],[[T1]],0x10
1206 ; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]]
1207 ; MIPS32: move v0,[[R_E0]]
1208 ; MIPS32: move v1,[[R_E1]]
1209 ; MIPS32: move a0,[[R_E2]]
1210 ; MIPS32: move a1,[[R_E3]]
229 } 1211 }
230 1212
231 define internal <8 x i1> @test_icmp_v8i16_ugt(<8 x i16> %a, <8 x i16> %b) { 1213 define internal <8 x i1> @test_icmp_v8i16_ugt(<8 x i16> %a, <8 x i16> %b) {
232 entry: 1214 entry:
233 %res = icmp ugt <8 x i16> %a, %b 1215 %res = icmp ugt <8 x i16> %a, %b
234 ret <8 x i1> %res 1216 ret <8 x i1> %res
235 ; CHECK-LABEL: test_icmp_v8i16_ugt 1217 ; CHECK-LABEL: test_icmp_v8i16_ugt
236 ; CHECK: pxor 1218 ; CHECK: pxor
237 ; CHECK: pcmpgtw 1219 ; CHECK: pcmpgtw
1220
1221 ; MIPS32-LABEL: test_icmp_v8i16_ugt
1222 ; MIPS32: lw [[B_E0:.*]],
1223 ; MIPS32: lw [[B_E1:.*]],
1224 ; MIPS32: lw [[B_E2:.*]],
1225 ; MIPS32: lw [[B_E3:.*]],
1226 ; MIPS32: move [[T1_E0:.*]],zero
1227 ; MIPS32: move [[T1_E1:.*]],zero
1228 ; MIPS32: move [[T1_E2:.*]],zero
1229 ; MIPS32: move [[T1_E3:.*]],zero
1230 ; MIPS32: andi [[T1:.*]],a0,0xffff
1231 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
1232 ; MIPS32: sll [[T1]],[[T1]],0x10
1233 ; MIPS32: sll [[T2]],[[T2]],0x10
1234 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
1235 ; MIPS32: andi [[T2]],[[T2]],0xffff
1236 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
1237 ; MIPS32: sll [[T3]],[[T3]],0x10
1238 ; MIPS32: or [[T2]],[[T2]],[[T3]]
1239 ; MIPS32: srl [[T4:.*]],a0,0x10
1240 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
1241 ; MIPS32: sll [[T4]],[[T4]],0x10
1242 ; MIPS32: sll [[T5]],[[T5]],0x10
1243 ; MIPS32: sltu [[T5]],[[T5]],[[T4]]
1244 ; MIPS32: sll [[T5]],[[T5]],0x10
1245 ; MIPS32: sll [[T2]],[[T2]],0x10
1246 ; MIPS32: srl [[T2]],[[T2]],0x10
1247 ; MIPS32: or [[R_E0:.*]],[[T5]],[[T2]]
1248 ; MIPS32: andi [[T1:.*]],a1,0xffff
1249 ; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
1250 ; MIPS32: sll [[T1]],[[T1]],0x10
1251 ; MIPS32: sll [[T2]],[[T2]],0x10
1252 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
1253 ; MIPS32: andi [[T2]],[[T2]],0xffff
1254 ; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
1255 ; MIPS32: sll [[T3]],[[T3]],0x10
1256 ; MIPS32: or [[T2]],[[T2]],[[T3]]
1257 ; MIPS32: srl [[T4:.*]],a1,0x10
1258 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
1259 ; MIPS32: sll [[T4]],[[T4]],0x10
1260 ; MIPS32: sll [[T5]],[[T5]],0x10
1261 ; MIPS32: sltu [[T5]],[[T5]],[[T4]]
1262 ; MIPS32: sll [[T5]],[[T5]],0x10
1263 ; MIPS32: sll [[T2]],[[T2]],0x10
1264 ; MIPS32: srl [[T2]],[[T2]],0x10
1265 ; MIPS32: or [[R_E1:.*]],[[T5]],[[T2]]
1266 ; MIPS32: andi [[T1:.*]],a2,0xffff
1267 ; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
1268 ; MIPS32: sll [[T1]],[[T1]],0x10
1269 ; MIPS32: sll [[T2]],[[T2]],0x10
1270 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
1271 ; MIPS32: andi [[T2]],[[T2]],0xffff
1272 ; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
1273 ; MIPS32: sll [[T3]],[[T3]],0x10
1274 ; MIPS32: or [[T2]],[[T2]],[[T3]]
1275 ; MIPS32: srl [[T4:.*]],a2,0x10
1276 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
1277 ; MIPS32: sll [[T4]],[[T4]],0x10
1278 ; MIPS32: sll [[T5]],[[T5]],0x10
1279 ; MIPS32: sltu [[T5]],[[T5]],[[T4]]
1280 ; MIPS32: sll [[T5]],[[T5]],0x10
1281 ; MIPS32: sll [[T2]],[[T2]],0x10
1282 ; MIPS32: srl [[T2]],[[T2]],0x10
1283 ; MIPS32: or [[R_E2:.*]],[[T5]],[[T2]]
1284 ; MIPS32: andi [[T1:.*]],a3,0xffff
1285 ; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
1286 ; MIPS32: sll [[T1]],[[T1]],0x10
1287 ; MIPS32: sll [[T2]],[[T2]],0x10
1288 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
1289 ; MIPS32: andi [[T2]],[[T2]],0xffff
1290 ; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
1291 ; MIPS32: sll [[T3]],[[T3]],0x10
1292 ; MIPS32: or [[T2]],[[T2]],[[T3]]
1293 ; MIPS32: srl [[T4:.*]],a3,0x10
1294 ; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
1295 ; MIPS32: sll [[T4]],[[T4]],0x10
1296 ; MIPS32: sll [[T5]],[[T5]],0x10
1297 ; MIPS32: sltu [[T5]],[[T5]],[[T4]]
1298 ; MIPS32: sll [[T5]],[[T5]],0x10
1299 ; MIPS32: sll [[T2]],[[T2]],0x10
1300 ; MIPS32: srl [[T2]],[[T2]],0x10
1301 ; MIPS32: or [[R_E3:.*]],[[T5]],[[T2]]
1302
238 } 1303 }
239 1304
240 define internal <8 x i1> @test_icmp_v8i16_ule(<8 x i16> %a, <8 x i16> %b) { 1305 define internal <8 x i1> @test_icmp_v8i16_ule(<8 x i16> %a, <8 x i16> %b) {
241 entry: 1306 entry:
242 %res = icmp ule <8 x i16> %a, %b 1307 %res = icmp ule <8 x i16> %a, %b
243 ret <8 x i1> %res 1308 ret <8 x i1> %res
244 ; CHECK-LABEL: test_icmp_v8i16_ule 1309 ; CHECK-LABEL: test_icmp_v8i16_ule
245 ; CHECK: pxor 1310 ; CHECK: pxor
246 ; CHECK: pcmpgtw 1311 ; CHECK: pcmpgtw
247 ; CHECK: pxor 1312 ; CHECK: pxor
1313
1314 ; MIPS32-LABEL: test_icmp_v8i16_ule
1315 ; MIPS32: lw [[B_E0:.*]],
1316 ; MIPS32: lw [[B_E1:.*]],
1317 ; MIPS32: lw [[B_E2:.*]],
1318 ; MIPS32: lw [[B_E3:.*]],
1319 ; MIPS32: move [[T1_E0:.*]],zero
1320 ; MIPS32: move [[T1_E1:.*]],zero
1321 ; MIPS32: move [[T1_E2:.*]],zero
1322 ; MIPS32: move [[T1_E3:.*]],zero
1323 ; MIPS32: andi [[T1:.*]],a0,0xffff
1324 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
1325 ; MIPS32: sll [[T1]],[[T1]],0x10
1326 ; MIPS32: sll [[T2]],[[T2]],0x10
1327 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
1328 ; MIPS32: xori [[T2]],[[T2]],0x1
1329 ; MIPS32: andi [[T2]],[[T2]],0xffff
1330 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
1331 ; MIPS32: sll [[T3]],[[T3]],0x10
1332 ; MIPS32: or [[T2]],[[T2]],[[T3]]
1333 ; MIPS32: srl [[T4:.*]],a0,0x10
1334 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
1335 ; MIPS32: sll [[T4]],[[T4]],0x10
1336 ; MIPS32: sll [[T5]],[[T5]],0x10
1337 ; MIPS32: sltu [[T5]],[[T5]],[[T4]]
1338 ; MIPS32: xori [[T5]],[[T5]],0x1
1339 ; MIPS32: sll [[T5]],[[T5]],0x10
1340 ; MIPS32: sll [[T2]],[[T2]],0x10
1341 ; MIPS32: srl [[T2]],[[T2]],0x10
1342 ; MIPS32: or [[R_E0:.*]],[[T5]],[[T2]]
1343 ; MIPS32: andi [[T1:.*]],a1,0xffff
1344 ; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
1345 ; MIPS32: sll [[T1]],[[T1]],0x10
1346 ; MIPS32: sll [[T2]],[[T2]],0x10
1347 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
1348 ; MIPS32: xori [[T2]],[[T2]],0x1
1349 ; MIPS32: andi [[T2]],[[T2]],0xffff
1350 ; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
1351 ; MIPS32: sll [[T3]],[[T3]],0x10
1352 ; MIPS32: or [[T2]],[[T2]],[[T3]]
1353 ; MIPS32: srl [[T4:.*]],a1,0x10
1354 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
1355 ; MIPS32: sll [[T4]],[[T4]],0x10
1356 ; MIPS32: sll [[T5]],[[T5]],0x10
1357 ; MIPS32: sltu [[T5]],[[T5]],[[T4]]
1358 ; MIPS32: xori [[T5]],[[T5]],0x1
1359 ; MIPS32: sll [[T5]],[[T5]],0x10
1360 ; MIPS32: sll [[T2]],[[T2]],0x10
1361 ; MIPS32: srl [[T2]],[[T2]],0x10
1362 ; MIPS32: or [[R_E1:.*]],[[T5]],[[T2]]
1363 ; MIPS32: andi [[T1:.*]],a2,0xffff
1364 ; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
1365 ; MIPS32: sll [[T1]],[[T1]],0x10
1366 ; MIPS32: sll [[T2]],[[T2]],0x10
1367 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
1368 ; MIPS32: xori [[T2]],[[T2]],0x1
1369 ; MIPS32: andi [[T2]],[[T2]],0xffff
1370 ; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
1371 ; MIPS32: sll [[T3]],[[T3]],0x10
1372 ; MIPS32: or [[T2]],[[T2]],[[T3]]
1373 ; MIPS32: srl [[T4:.*]],a2,0x10
1374 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
1375 ; MIPS32: sll [[T4]],[[T4]],0x10
1376 ; MIPS32: sll [[T5]],[[T5]],0x10
1377 ; MIPS32: sltu [[T5]],[[T5]],[[T4]]
1378 ; MIPS32: xori [[T5]],[[T5]],0x1
1379 ; MIPS32: sll [[T5]],[[T5]],0x10
1380 ; MIPS32: sll [[T2]],[[T2]],0x10
1381 ; MIPS32: srl [[T2]],[[T2]],0x10
1382 ; MIPS32: or [[R_E2:.*]],[[T5]],[[T2]]
1383 ; MIPS32: andi [[T1:.*]],a3,0xffff
1384 ; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
1385 ; MIPS32: sll [[T1]],[[T1]],0x10
1386 ; MIPS32: sll [[T2]],[[T2]],0x10
1387 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
1388 ; MIPS32: xori [[T2]],[[T2]],0x1
1389 ; MIPS32: andi [[T2]],[[T2]],0xffff
1390 ; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
1391 ; MIPS32: sll [[T3]],[[T3]],0x10
1392 ; MIPS32: or [[T2]],[[T2]],[[T3]]
1393 ; MIPS32: srl [[T4:.*]],a3,0x10
1394 ; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
1395 ; MIPS32: sll [[T4]],[[T4]],0x10
1396 ; MIPS32: sll [[T5]],[[T5]],0x10
1397 ; MIPS32: sltu [[T5]],[[T5]],[[T4]]
1398 ; MIPS32: xori [[T5]],[[T5]],0x1
1399 ; MIPS32: sll [[T5]],[[T5]],0x10
1400 ; MIPS32: sll [[T2]],[[T2]],0x10
1401 ; MIPS32: srl [[T2]],[[T2]],0x10
1402 ; MIPS32: or [[R_E3:.*]],[[T5]],[[T2]]
248 } 1403 }
249 1404
250 define internal <8 x i1> @test_icmp_v8i16_ult(<8 x i16> %a, <8 x i16> %b) { 1405 define internal <8 x i1> @test_icmp_v8i16_ult(<8 x i16> %a, <8 x i16> %b) {
251 entry: 1406 entry:
252 %res = icmp ult <8 x i16> %a, %b 1407 %res = icmp ult <8 x i16> %a, %b
253 ret <8 x i1> %res 1408 ret <8 x i1> %res
254 ; CHECK-LABEL: test_icmp_v8i16_ult 1409 ; CHECK-LABEL: test_icmp_v8i16_ult
255 ; CHECK: pxor 1410 ; CHECK: pxor
256 ; CHECK: pcmpgtw 1411 ; CHECK: pcmpgtw
1412
1413 ; MIPS32-LABEL: test_icmp_v8i16_ult
1414 ; MIPS32: lw [[B_E0:.*]],
1415 ; MIPS32: lw [[B_E1:.*]],
1416 ; MIPS32: lw [[B_E2:.*]],
1417 ; MIPS32: lw [[B_E3:.*]],
1418 ; MIPS32: move [[T1_E0:.*]],zero
1419 ; MIPS32: move [[T1_E1:.*]],zero
1420 ; MIPS32: move [[T1_E2:.*]],zero
1421 ; MIPS32: move [[T1_E3:.*]],zero
1422 ; MIPS32: andi [[T1:.*]],a0,0xffff
1423 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
1424 ; MIPS32: sll [[T1]],[[T1]],0x10
1425 ; MIPS32: sll [[T2]],[[T2]],0x10
1426 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
1427 ; MIPS32: andi [[T1]],[[T1]],0xffff
1428 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
1429 ; MIPS32: sll [[T3]],[[T3]],0x10
1430 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1431 ; MIPS32: srl [[T4:.*]],a0,0x10
1432 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
1433 ; MIPS32: sll [[T4]],[[T4]],0x10
1434 ; MIPS32: sll [[T5]],[[T5]],0x10
1435 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
1436 ; MIPS32: sll [[T4]],[[T4]],0x10
1437 ; MIPS32: sll [[T1]],[[T1]],0x10
1438 ; MIPS32: srl [[T1]],[[T1]],0x10
1439 ; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]]
1440 ; MIPS32: andi [[T1:.*]],a1,0xffff
1441 ; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
1442 ; MIPS32: sll [[T1]],[[T1]],0x10
1443 ; MIPS32: sll [[T2]],[[T2]],0x10
1444 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
1445 ; MIPS32: andi [[T1]],[[T1]],0xffff
1446 ; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
1447 ; MIPS32: sll [[T3]],[[T3]],0x10
1448 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1449 ; MIPS32: srl [[T4:.*]],a1,0x10
1450 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
1451 ; MIPS32: sll [[T4]],[[T4]],0x10
1452 ; MIPS32: sll [[T5]],[[T5]],0x10
1453 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
1454 ; MIPS32: sll [[T4]],[[T4]],0x10
1455 ; MIPS32: sll [[T1]],[[T1]],0x10
1456 ; MIPS32: srl [[T1]],[[T1]],0x10
1457 ; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]]
1458 ; MIPS32: andi [[T1:.*]],a2,0xffff
1459 ; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
1460 ; MIPS32: sll [[T1]],[[T1]],0x10
1461 ; MIPS32: sll [[T2]],[[T2]],0x10
1462 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
1463 ; MIPS32: andi [[T1]],[[T1]],0xffff
1464 ; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
1465 ; MIPS32: sll [[T3]],[[T3]],0x10
1466 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1467 ; MIPS32: srl [[T4:.*]],a2,0x10
1468 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
1469 ; MIPS32: sll [[T4]],[[T4]],0x10
1470 ; MIPS32: sll [[T5]],[[T5]],0x10
1471 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
1472 ; MIPS32: sll [[T4]],[[T4]],0x10
1473 ; MIPS32: sll [[T1]],[[T1]],0x10
1474 ; MIPS32: srl [[T1]],[[T1]],0x10
1475 ; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]]
1476 ; MIPS32: andi [[T1:.*]],a3,0xffff
1477 ; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
1478 ; MIPS32: sll [[T1]],[[T1]],0x10
1479 ; MIPS32: sll [[T2]],[[T2]],0x10
1480 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
1481 ; MIPS32: andi [[T1]],[[T1]],0xffff
1482 ; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
1483 ; MIPS32: sll [[T3]],[[T3]],0x10
1484 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1485 ; MIPS32: srl [[T4:.*]],a3,0x10
1486 ; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
1487 ; MIPS32: sll [[T4]],[[T4]],0x10
1488 ; MIPS32: sll [[T5]],[[T5]],0x10
1489 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
1490 ; MIPS32: sll [[T4]],[[T4]],0x10
1491 ; MIPS32: sll [[T1]],[[T1]],0x10
1492 ; MIPS32: srl [[T1]],[[T1]],0x10
1493 ; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]]
1494 ; MIPS32: move v0,[[R_E0]]
1495 ; MIPS32: move v1,[[R_E1]]
1496 ; MIPS32: move a0,[[R_E2]]
1497 ; MIPS32: move a1,[[R_E3]]
257 } 1498 }
258 1499
259 define internal <8 x i1> @test_icmp_v8i1_eq(<8 x i1> %a, <8 x i1> %b) { 1500 define internal <8 x i1> @test_icmp_v8i1_eq(<8 x i1> %a, <8 x i1> %b) {
260 entry: 1501 entry:
261 %res = icmp eq <8 x i1> %a, %b 1502 %res = icmp eq <8 x i1> %a, %b
262 ret <8 x i1> %res 1503 ret <8 x i1> %res
263 ; CHECK-LABEL: test_icmp_v8i1_eq 1504 ; CHECK-LABEL: test_icmp_v8i1_eq
264 ; CHECK: pcmpeqw 1505 ; CHECK: pcmpeqw
1506
1507 ; MIPS32-LABEL: test_icmp_v8i1_eq
1508 ; MIPS32: lw [[B_E0:.*]],
1509 ; MIPS32: lw [[B_E1:.*]],
1510 ; MIPS32: lw [[B_E2:.*]],
1511 ; MIPS32: lw [[B_E3:.*]],
1512 ; MIPS32: move [[T1_E0:.*]],zero
1513 ; MIPS32: move [[T1_E1:.*]],zero
1514 ; MIPS32: move [[T1_E2:.*]],zero
1515 ; MIPS32: move [[T1_E3:.*]],zero
1516 ; MIPS32: andi [[T1:.*]],a0,0xffff
1517 ; MIPS32: andi [[T1]],[[T1]],0x1
1518 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
1519 ; MIPS32: andi [[T2]],[[T2]],0x1
1520 ; MIPS32: sll [[T1]],[[T1]],0x1f
1521 ; MIPS32: sll [[T2]],[[T2]],0x1f
1522 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
1523 ; MIPS32: sltiu [[T1]],[[T1]],1
1524 ; MIPS32: andi [[T1]],[[T1]],0xffff
1525 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
1526 ; MIPS32: sll [[T3]],[[T3]],0x10
1527 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1528 ; MIPS32: srl [[T4:.*]],a0,0x10
1529 ; MIPS32: andi [[T4]],[[T4]],0x1
1530 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
1531 ; MIPS32: andi [[T5]],[[T5]],0x1
1532 ; MIPS32: sll [[T4]],[[T4]],0x1f
1533 ; MIPS32: sll [[T5]],[[T5]],0x1f
1534 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
1535 ; MIPS32: sltiu [[T4]],[[T4]],1
1536 ; MIPS32: sll [[T4]],[[T4]],0x10
1537 ; MIPS32: sll [[T1]],[[T1]],0x10
1538 ; MIPS32: srl [[T1]],[[T1]],0x10
1539 ; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]]
1540 ; MIPS32: andi [[T1:.*]],a1,0xffff
1541 ; MIPS32: andi [[T1]],[[T1]],0x1
1542 ; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
1543 ; MIPS32: andi [[T2]],[[T2]],0x1
1544 ; MIPS32: sll [[T1]],[[T1]],0x1f
1545 ; MIPS32: sll [[T2]],[[T2]],0x1f
1546 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
1547 ; MIPS32: sltiu [[T1]],[[T1]],1
1548 ; MIPS32: andi [[T1]],[[T1]],0xffff
1549 ; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
1550 ; MIPS32: sll [[T3]],[[T3]],0x10
1551 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1552 ; MIPS32: srl [[T4:.*]],a1,0x10
1553 ; MIPS32: andi [[T4]],[[T4]],0x1
1554 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
1555 ; MIPS32: andi [[T5]],[[T5]],0x1
1556 ; MIPS32: sll [[T4]],[[T4]],0x1f
1557 ; MIPS32: sll [[T5]],[[T5]],0x1f
1558 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
1559 ; MIPS32: sltiu [[T4]],[[T4]],1
1560 ; MIPS32: sll [[T4]],[[T4]],0x10
1561 ; MIPS32: sll [[T1]],[[T1]],0x10
1562 ; MIPS32: srl [[T1]],[[T1]],0x10
1563 ; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]]
1564 ; MIPS32: andi [[T1:.*]],a2,0xffff
1565 ; MIPS32: andi [[T1]],[[T1]],0x1
1566 ; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
1567 ; MIPS32: andi [[T2]],[[T2]],0x1
1568 ; MIPS32: sll [[T1]],[[T1]],0x1f
1569 ; MIPS32: sll [[T2]],[[T2]],0x1f
1570 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
1571 ; MIPS32: sltiu [[T1]],[[T1]],1
1572 ; MIPS32: andi [[T1]],[[T1]],0xffff
1573 ; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
1574 ; MIPS32: sll [[T3]],[[T3]],0x10
1575 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1576 ; MIPS32: srl [[T4:.*]],a2,0x10
1577 ; MIPS32: andi [[T4]],[[T4]],0x1
1578 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
1579 ; MIPS32: andi [[T5]],[[T5]],0x1
1580 ; MIPS32: sll [[T4]],[[T4]],0x1f
1581 ; MIPS32: sll [[T5]],[[T5]],0x1f
1582 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
1583 ; MIPS32: sltiu [[T4]],[[T4]],1
1584 ; MIPS32: sll [[T4]],[[T4]],0x10
1585 ; MIPS32: sll [[T1]],[[T1]],0x10
1586 ; MIPS32: srl [[T1]],[[T1]],0x10
1587 ; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]]
1588 ; MIPS32: andi [[T1:.*]],a3,0xffff
1589 ; MIPS32: andi [[T1]],[[T1]],0x1
1590 ; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
1591 ; MIPS32: andi [[T2]],[[T2]],0x1
1592 ; MIPS32: sll [[T1]],[[T1]],0x1f
1593 ; MIPS32: sll [[T2]],[[T2]],0x1f
1594 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
1595 ; MIPS32: sltiu [[T1]],[[T1]],1
1596 ; MIPS32: andi [[T1]],[[T1]],0xffff
1597 ; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
1598 ; MIPS32: sll [[T3]],[[T3]],0x10
1599 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1600 ; MIPS32: srl [[T4:.*]],a3,0x10
1601 ; MIPS32: andi [[T4]],[[T4]],0x1
1602 ; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
1603 ; MIPS32: andi [[T5]],[[T5]],0x1
1604 ; MIPS32: sll [[T4]],[[T4]],0x1f
1605 ; MIPS32: sll [[T5]],[[T5]],0x1f
1606 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
1607 ; MIPS32: sltiu [[T4]],[[T4]],1
1608 ; MIPS32: sll [[T4]],[[T4]],0x10
1609 ; MIPS32: sll [[T1]],[[T1]],0x10
1610 ; MIPS32: srl [[T1]],[[T1]],0x10
1611 ; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]]
1612 ; MIPS32: move v0,[[R_E0]]
1613 ; MIPS32: move v1,[[R_E1]]
1614 ; MIPS32: move a0,[[R_E2]]
1615 ; MIPS32: move a1,[[R_E3]]
265 } 1616 }
266 1617
267 define internal <8 x i1> @test_icmp_v8i1_ne(<8 x i1> %a, <8 x i1> %b) { 1618 define internal <8 x i1> @test_icmp_v8i1_ne(<8 x i1> %a, <8 x i1> %b) {
268 entry: 1619 entry:
269 %res = icmp ne <8 x i1> %a, %b 1620 %res = icmp ne <8 x i1> %a, %b
270 ret <8 x i1> %res 1621 ret <8 x i1> %res
271 ; CHECK-LABEL: test_icmp_v8i1_ne 1622 ; CHECK-LABEL: test_icmp_v8i1_ne
272 ; CHECK: pcmpeqw 1623 ; CHECK: pcmpeqw
273 ; CHECK: pxor 1624 ; CHECK: pxor
1625
1626 ; MIPS32-LABEL: test_icmp_v8i1_ne
1627 ; MIPS32: lw [[B_E0:.*]],
1628 ; MIPS32: lw [[B_E1:.*]],
1629 ; MIPS32: lw [[B_E2:.*]],
1630 ; MIPS32: lw [[B_E3:.*]],
1631 ; MIPS32: move [[T1_E0:.*]],zero
1632 ; MIPS32: move [[T1_E1:.*]],zero
1633 ; MIPS32: move [[T1_E2:.*]],zero
1634 ; MIPS32: move [[T1_E3:.*]],zero
1635 ; MIPS32: andi [[T1:.*]],a0,0xffff
1636 ; MIPS32: andi [[T1]],[[T1]],0x1
1637 ; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
1638 ; MIPS32: andi [[T2]],[[T2]],0x1
1639 ; MIPS32: sll [[T1]],[[T1]],0x1f
1640 ; MIPS32: sll [[T2]],[[T2]],0x1f
1641 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
1642 ; MIPS32: sltu [[T1]],zero,[[T1]]
1643 ; MIPS32: andi [[T1]],[[T1]],0xffff
1644 ; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
1645 ; MIPS32: sll [[T3]],[[T3]],0x10
1646 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1647 ; MIPS32: srl [[T4:.*]],a0,0x10
1648 ; MIPS32: andi [[T4]],[[T4]],0x1
1649 ; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
1650 ; MIPS32: andi [[T5]],[[T5]],0x1
1651 ; MIPS32: sll [[T4]],[[T4]],0x1f
1652 ; MIPS32: sll [[T5]],[[T5]],0x1f
1653 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
1654 ; MIPS32: sltu [[T4]],zero,[[T4]]
1655 ; MIPS32: sll [[T4]],[[T4]],0x10
1656 ; MIPS32: sll [[T1]],[[T1]],0x10
1657 ; MIPS32: srl [[T1]],[[T1]],0x10
1658 ; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]]
1659 ; MIPS32: andi [[T1:.*]],a1,0xffff
1660 ; MIPS32: andi [[T1]],[[T1]],0x1
1661 ; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
1662 ; MIPS32: andi [[T2]],[[T2]],0x1
1663 ; MIPS32: sll [[T1]],[[T1]],0x1f
1664 ; MIPS32: sll [[T2]],[[T2]],0x1f
1665 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
1666 ; MIPS32: sltu [[T1]],zero,[[T1]]
1667 ; MIPS32: andi [[T1]],[[T1]],0xffff
1668 ; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
1669 ; MIPS32: sll [[T3]],[[T3]],0x10
1670 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1671 ; MIPS32: srl [[T4:.*]],a1,0x10
1672 ; MIPS32: andi [[T4]],[[T4]],0x1
1673 ; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
1674 ; MIPS32: andi [[T5]],[[T5]],0x1
1675 ; MIPS32: sll [[T4]],[[T4]],0x1f
1676 ; MIPS32: sll [[T5]],[[T5]],0x1f
1677 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
1678 ; MIPS32: sltu [[T4]],zero,[[T4]]
1679 ; MIPS32: sll [[T4]],[[T4]],0x10
1680 ; MIPS32: sll [[T1]],[[T1]],0x10
1681 ; MIPS32: srl [[T1]],[[T1]],0x10
1682 ; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]]
1683 ; MIPS32: andi [[T1:.*]],a2,0xffff
1684 ; MIPS32: andi [[T1]],[[T1]],0x1
1685 ; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
1686 ; MIPS32: andi [[T2]],[[T2]],0x1
1687 ; MIPS32: sll [[T1]],[[T1]],0x1f
1688 ; MIPS32: sll [[T2]],[[T2]],0x1f
1689 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
1690 ; MIPS32: sltu [[T1]],zero,[[T1]]
1691 ; MIPS32: andi [[T1]],[[T1]],0xffff
1692 ; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
1693 ; MIPS32: sll [[T3]],[[T3]],0x10
1694 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1695 ; MIPS32: srl [[T4:.*]],a2,0x10
1696 ; MIPS32: andi [[T4]],[[T4]],0x1
1697 ; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
1698 ; MIPS32: andi [[T5]],[[T5]],0x1
1699 ; MIPS32: sll [[T4]],[[T4]],0x1f
1700 ; MIPS32: sll [[T5]],[[T5]],0x1f
1701 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
1702 ; MIPS32: sltu [[T4]],zero,[[T4]]
1703 ; MIPS32: sll [[T4]],[[T4]],0x10
1704 ; MIPS32: sll [[T1]],[[T1]],0x10
1705 ; MIPS32: srl [[T1]],[[T1]],0x10
1706 ; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]]
1707 ; MIPS32: andi [[T1:.*]],a3,0xffff
1708 ; MIPS32: andi [[T1]],[[T1]],0x1
1709 ; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
1710 ; MIPS32: andi [[T2]],[[T2]],0x1
1711 ; MIPS32: sll [[T1]],[[T1]],0x1f
1712 ; MIPS32: sll [[T2]],[[T2]],0x1f
1713 ; MIPS32: xor [[T1]],[[T1]],[[T2]]
1714 ; MIPS32: sltu [[T1]],zero,[[T1]]
1715 ; MIPS32: andi [[T1]],[[T1]],0xffff
1716 ; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
1717 ; MIPS32: sll [[T3]],[[T3]],0x10
1718 ; MIPS32: or [[T1]],[[T1]],[[T3]]
1719 ; MIPS32: srl [[T4:.*]],a3,0x10
1720 ; MIPS32: andi [[T4]],[[T4]],0x1
1721 ; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
1722 ; MIPS32: andi [[T5]],[[T5]],0x1
1723 ; MIPS32: sll [[T4]],[[T4]],0x1f
1724 ; MIPS32: sll [[T5]],[[T5]],0x1f
1725 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
1726 ; MIPS32: sltu [[T4]],zero,[[T4]]
1727 ; MIPS32: sll [[T4]],[[T4]],0x10
1728 ; MIPS32: sll [[T1]],[[T1]],0x10
1729 ; MIPS32: srl [[T1]],[[T1]],0x10
1730 ; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]]
1731 ; MIPS32: move v0,[[R_E0]]
1732 ; MIPS32: move v1,[[R_E1]]
1733 ; MIPS32: move a0,[[R_E2]]
1734 ; MIPS32: move a1,[[R_E3]]
274 } 1735 }
275 1736
276 define internal <8 x i1> @test_icmp_v8i1_sgt(<8 x i1> %a, <8 x i1> %b) { 1737 define internal <8 x i1> @test_icmp_v8i1_sgt(<8 x i1> %a, <8 x i1> %b) {
277 entry: 1738 entry:
278 %res = icmp sgt <8 x i1> %a, %b 1739 %res = icmp sgt <8 x i1> %a, %b
279 ret <8 x i1> %res 1740 ret <8 x i1> %res
280 ; CHECK-LABEL: test_icmp_v8i1_sgt 1741 ; CHECK-LABEL: test_icmp_v8i1_sgt
281 ; CHECK: pcmpgtw 1742 ; CHECK: pcmpgtw
1743
1744 ; MIPS32-LABEL: test_icmp_v8i1_sgt
1745 ; MIPS32: lw [[BV_E0:.*]],
1746 ; MIPS32: lw [[BV_E1:.*]],
1747 ; MIPS32: lw [[BV_E2:.*]],
1748 ; MIPS32: lw [[BV_E3:.*]],
1749 ; MIPS32: move [[TV_E0:.*]],zero
1750 ; MIPS32: move [[TV_E1:.*]],zero
1751 ; MIPS32: move [[TV_E2:.*]],zero
1752 ; MIPS32: move [[TV_E3:.*]],zero
1753 ; MIPS32: andi [[T0:.*]],a0,0xffff
1754 ; MIPS32: andi [[T0]],[[T0]],0x1
1755 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff
1756 ; MIPS32: andi [[T1]],[[T1]],0x1
1757 ; MIPS32: sll [[T0]],[[T0]],0x1f
1758 ; MIPS32: sll [[T1]],[[T1]],0x1f
1759 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
1760 ; MIPS32: andi [[T1]],[[T1]],0xffff
1761 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10
1762 ; MIPS32: sll [[T2]],[[T2]],0x10
1763 ; MIPS32: or [[T1]],[[T1]],[[T2]]
1764 ; MIPS32: srl [[T3:.*]],a0,0x10
1765 ; MIPS32: andi [[T3]],[[T3]],0x1
1766 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10
1767 ; MIPS32: andi [[T4]],[[T4]],0x1
1768 ; MIPS32: sll [[T3]],[[T3]],0x1f
1769 ; MIPS32: sll [[T4]],[[T4]],0x1f
1770 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
1771 ; MIPS32: sll [[T4]],[[T4]],0x10
1772 ; MIPS32: sll [[T1]],[[T1]],0x10
1773 ; MIPS32: srl [[T1]],[[T1]],0x10
1774 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
1775 ; MIPS32: andi [[T0:.*]],a1,0xffff
1776 ; MIPS32: andi [[T0]],[[T0]],0x1
1777 ; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
1778 ; MIPS32: andi [[T1]],[[T1]],0x1
1779 ; MIPS32: sll [[T0]],[[T0]],0x1f
1780 ; MIPS32: sll [[T1]],[[T1]],0x1f
1781 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
1782 ; MIPS32: andi [[T1]],[[T1]],0xffff
1783 ; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
1784 ; MIPS32: sll [[T2]],[[T2]],0x10
1785 ; MIPS32: or [[T1]],[[T1]],[[T2]]
1786 ; MIPS32: srl [[T3:.*]],a1,0x10
1787 ; MIPS32: andi [[T3]],[[T3]],0x1
1788 ; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
1789 ; MIPS32: andi [[T4]],[[T4]],0x1
1790 ; MIPS32: sll [[T3]],[[T3]],0x1f
1791 ; MIPS32: sll [[T4]],[[T4]],0x1f
1792 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
1793 ; MIPS32: sll [[T4]],[[T4]],0x10
1794 ; MIPS32: sll [[T1]],[[T1]],0x10
1795 ; MIPS32: srl [[T1]],[[T1]],0x10
1796 ; MIPS32: or [[RV_E1:.*]],[[T4]],[[T1]]
1797 ; MIPS32: andi [[T0:.*]],a2,0xffff
1798 ; MIPS32: andi [[T0]],[[T0]],0x1
1799 ; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
1800 ; MIPS32: andi [[T1]],[[T1]],0x1
1801 ; MIPS32: sll [[T0]],[[T0]],0x1f
1802 ; MIPS32: sll [[T1]],[[T1]],0x1f
1803 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
1804 ; MIPS32: andi [[T1]],[[T1]],0xffff
1805 ; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
1806 ; MIPS32: sll [[T2]],[[T2]],0x10
1807 ; MIPS32: or [[T1]],[[T1]],[[T2]]
1808 ; MIPS32: srl [[T3:.*]],a2,0x10
1809 ; MIPS32: andi [[T3]],[[T3]],0x1
1810 ; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
1811 ; MIPS32: andi [[T4]],[[T4]],0x1
1812 ; MIPS32: sll [[T3]],[[T3]],0x1f
1813 ; MIPS32: sll [[T4]],[[T4]],0x1f
1814 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
1815 ; MIPS32: sll [[T4]],[[T4]],0x10
1816 ; MIPS32: sll [[T1]],[[T1]],0x10
1817 ; MIPS32: srl [[T1]],[[T1]],0x10
1818 ; MIPS32: or [[RV_E2:.*]],[[T4]],[[T1]]
1819 ; MIPS32: andi [[T0:.*]],a3,0xffff
1820 ; MIPS32: andi [[T0]],[[T0]],0x1
1821 ; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
1822 ; MIPS32: andi [[T1]],[[T1]],0x1
1823 ; MIPS32: sll [[T0]],[[T0]],0x1f
1824 ; MIPS32: sll [[T1]],[[T1]],0x1f
1825 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
1826 ; MIPS32: andi [[T1]],[[T1]],0xffff
1827 ; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
1828 ; MIPS32: sll [[T2]],[[T2]],0x10
1829 ; MIPS32: or [[T1]],[[T1]],[[T2]]
1830 ; MIPS32: srl [[T3:.*]],a3,0x10
1831 ; MIPS32: andi [[T3]],[[T3]],0x1
1832 ; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
1833 ; MIPS32: andi [[T4]],[[T4]],0x1
1834 ; MIPS32: sll [[T3]],[[T3]],0x1f
1835 ; MIPS32: sll [[T4]],[[T4]],0x1f
1836 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
1837 ; MIPS32: sll [[T4]],[[T4]],0x10
1838 ; MIPS32: sll [[T1]],[[T1]],0x10
1839 ; MIPS32: srl [[T1]],[[T1]],0x10
1840 ; MIPS32: or [[RV_E3:.*]],[[T4]],[[T1]]
282 } 1841 }
283 1842
284 define internal <8 x i1> @test_icmp_v8i1_sle(<8 x i1> %a, <8 x i1> %b) { 1843 define internal <8 x i1> @test_icmp_v8i1_sle(<8 x i1> %a, <8 x i1> %b) {
285 entry: 1844 entry:
286 %res = icmp sle <8 x i1> %a, %b 1845 %res = icmp sle <8 x i1> %a, %b
287 ret <8 x i1> %res 1846 ret <8 x i1> %res
288 ; CHECK-LABEL: test_icmp_v8i1_sle 1847 ; CHECK-LABEL: test_icmp_v8i1_sle
289 ; CHECK: pcmpgtw 1848 ; CHECK: pcmpgtw
290 ; CHECK: pxor 1849 ; CHECK: pxor
1850
1851 ; MIPS32-LABEL: test_icmp_v8i1_sle
1852 ; MIPS32: lw [[BV_E0:.*]],
1853 ; MIPS32: lw [[BV_E1:.*]],
1854 ; MIPS32: lw [[BV_E2:.*]],
1855 ; MIPS32: lw [[BV_E3:.*]],
1856 ; MIPS32: move [[TV_E0:.*]],zero
1857 ; MIPS32: move [[TV_E1:.*]],zero
1858 ; MIPS32: move [[TV_E2:.*]],zero
1859 ; MIPS32: move [[TV_E3:.*]],zero
1860 ; MIPS32: andi [[T0:.*]],a0,0xffff
1861 ; MIPS32: andi [[T0]],[[T0]],0x1
1862 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff
1863 ; MIPS32: andi [[T1]],[[T1]],0x1
1864 ; MIPS32: sll [[T0]],[[T0]],0x1f
1865 ; MIPS32: sll [[T1]],[[T1]],0x1f
1866 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
1867 ; MIPS32: xori [[T1]],[[T1]],0x1
1868 ; MIPS32: andi [[T1]],[[T1]],0xffff
1869 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10
1870 ; MIPS32: sll [[T2]],[[T2]],0x10
1871 ; MIPS32: or [[T1]],[[T1]],[[T2]]
1872 ; MIPS32: srl [[T3:.*]],a0,0x10
1873 ; MIPS32: andi [[T3]],[[T3]],0x1
1874 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10
1875 ; MIPS32: andi [[T4]],[[T4]],0x1
1876 ; MIPS32: sll [[T3]],[[T3]],0x1f
1877 ; MIPS32: sll [[T4]],[[T4]],0x1f
1878 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
1879 ; MIPS32: xori [[T4]],[[T4]],0x1
1880 ; MIPS32: sll [[T4]],[[T4]],0x10
1881 ; MIPS32: sll [[T1]],[[T1]],0x10
1882 ; MIPS32: srl [[T1]],[[T1]],0x10
1883 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
1884 ; MIPS32: andi [[T0:.*]],a1,0xffff
1885 ; MIPS32: andi [[T0]],[[T0]],0x1
1886 ; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
1887 ; MIPS32: andi [[T1]],[[T1]],0x1
1888 ; MIPS32: sll [[T0]],[[T0]],0x1f
1889 ; MIPS32: sll [[T1]],[[T1]],0x1f
1890 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
1891 ; MIPS32: xori [[T1]],[[T1]],0x1
1892 ; MIPS32: andi [[T1]],[[T1]],0xffff
1893 ; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
1894 ; MIPS32: sll [[T2]],[[T2]],0x10
1895 ; MIPS32: or [[T1]],[[T1]],[[T2]]
1896 ; MIPS32: srl [[T3:.*]],a1,0x10
1897 ; MIPS32: andi [[T3]],[[T3]],0x1
1898 ; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
1899 ; MIPS32: andi [[T4]],[[T4]],0x1
1900 ; MIPS32: sll [[T3]],[[T3]],0x1f
1901 ; MIPS32: sll [[T4]],[[T4]],0x1f
1902 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
1903 ; MIPS32: xori [[T4]],[[T4]],0x1
1904 ; MIPS32: sll [[T4]],[[T4]],0x10
1905 ; MIPS32: sll [[T1]],[[T1]],0x10
1906 ; MIPS32: srl [[T1]],[[T1]],0x10
1907 ; MIPS32: or [[RV_E1:.*]],[[T4]],[[T1]]
1908 ; MIPS32: andi [[T0:.*]],a2,0xffff
1909 ; MIPS32: andi [[T0]],[[T0]],0x1
1910 ; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
1911 ; MIPS32: andi [[T1]],[[T1]],0x1
1912 ; MIPS32: sll [[T0]],[[T0]],0x1f
1913 ; MIPS32: sll [[T1]],[[T1]],0x1f
1914 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
1915 ; MIPS32: xori [[T1]],[[T1]],0x1
1916 ; MIPS32: andi [[T1]],[[T1]],0xffff
1917 ; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
1918 ; MIPS32: sll [[T2]],[[T2]],0x10
1919 ; MIPS32: or [[T1]],[[T1]],[[T2]]
1920 ; MIPS32: srl [[T3:.*]],a2,0x10
1921 ; MIPS32: andi [[T3]],[[T3]],0x1
1922 ; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
1923 ; MIPS32: andi [[T4]],[[T4]],0x1
1924 ; MIPS32: sll [[T3]],[[T3]],0x1f
1925 ; MIPS32: sll [[T4]],[[T4]],0x1f
1926 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
1927 ; MIPS32: xori [[T4]],[[T4]],0x1
1928 ; MIPS32: sll [[T4]],[[T4]],0x10
1929 ; MIPS32: sll [[T1]],[[T1]],0x10
1930 ; MIPS32: srl [[T1]],[[T1]],0x10
1931 ; MIPS32: or [[RV_E2:.*]],[[T4]],[[T1]]
1932 ; MIPS32: andi [[T0:.*]],a3,0xffff
1933 ; MIPS32: andi [[T0]],[[T0]],0x1
1934 ; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
1935 ; MIPS32: andi [[T1]],[[T1]],0x1
1936 ; MIPS32: sll [[T0]],[[T0]],0x1f
1937 ; MIPS32: sll [[T1]],[[T1]],0x1f
1938 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
1939 ; MIPS32: xori [[T1]],[[T1]],0x1
1940 ; MIPS32: andi [[T1]],[[T1]],0xffff
1941 ; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
1942 ; MIPS32: sll [[T2]],[[T2]],0x10
1943 ; MIPS32: or [[T1]],[[T1]],[[T2]]
1944 ; MIPS32: srl [[T3:.*]],a3,0x10
1945 ; MIPS32: andi [[T3]],[[T3]],0x1
1946 ; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
1947 ; MIPS32: andi [[T4]],[[T4]],0x1
1948 ; MIPS32: sll [[T3]],[[T3]],0x1f
1949 ; MIPS32: sll [[T4]],[[T4]],0x1f
1950 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
1951 ; MIPS32: xori [[T4]],[[T4]],0x1
1952 ; MIPS32: sll [[T4]],[[T4]],0x10
1953 ; MIPS32: sll [[T1]],[[T1]],0x10
1954 ; MIPS32: srl [[T1]],[[T1]],0x10
1955 ; MIPS32: or [[RV_E3:.*]],[[T4]],[[T1]]
291 } 1956 }
292 1957
293 define internal <8 x i1> @test_icmp_v8i1_slt(<8 x i1> %a, <8 x i1> %b) { 1958 define internal <8 x i1> @test_icmp_v8i1_slt(<8 x i1> %a, <8 x i1> %b) {
294 entry: 1959 entry:
295 %res = icmp slt <8 x i1> %a, %b 1960 %res = icmp slt <8 x i1> %a, %b
296 ret <8 x i1> %res 1961 ret <8 x i1> %res
297 ; CHECK-LABEL: test_icmp_v8i1_slt 1962 ; CHECK-LABEL: test_icmp_v8i1_slt
298 ; CHECK: pcmpgtw 1963 ; CHECK: pcmpgtw
1964
1965 ; MIPS32-LABEL: test_icmp_v8i1_slt
1966 ; MIPS32: lw [[BV_E0:.*]],
1967 ; MIPS32: lw [[BV_E1:.*]],
1968 ; MIPS32: lw [[BV_E2:.*]],
1969 ; MIPS32: lw [[BV_E3:.*]],
1970 ; MIPS32: move [[TV_E0:.*]],zero
1971 ; MIPS32: move [[TV_E1:.*]],zero
1972 ; MIPS32: move [[TV_E2:.*]],zero
1973 ; MIPS32: move [[TV_E3:.*]],zero
1974 ; MIPS32: andi [[T0:.*]],a0,0xffff
1975 ; MIPS32: andi [[T0]],[[T0]],0x1
1976 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff
1977 ; MIPS32: andi [[T1]],[[T1]],0x1
1978 ; MIPS32: sll [[T0]],[[T0]],0x1f
1979 ; MIPS32: sll [[T1]],[[T1]],0x1f
1980 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
1981 ; MIPS32: andi [[T0]],[[T0]],0xffff
1982 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10
1983 ; MIPS32: sll [[T2]],[[T2]],0x10
1984 ; MIPS32: or [[T0]],[[T0]],[[T2]]
1985 ; MIPS32: srl [[T3:.*]],a0,0x10
1986 ; MIPS32: andi [[T3]],[[T3]],0x1
1987 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10
1988 ; MIPS32: andi [[T4]],[[T4]],0x1
1989 ; MIPS32: sll [[T3]],[[T3]],0x1f
1990 ; MIPS32: sll [[T4]],[[T4]],0x1f
1991 ; MIPS32: slt [[T3]],[[T3]],[[T4]]
1992 ; MIPS32: sll [[T3]],[[T3]],0x10
1993 ; MIPS32: sll [[T0]],[[T0]],0x10
1994 ; MIPS32: srl [[T0]],[[T0]],0x10
1995 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
1996 ; MIPS32: andi [[T0:.*]],a1,0xffff
1997 ; MIPS32: andi [[T0]],[[T0]],0x1
1998 ; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
1999 ; MIPS32: andi [[T1]],[[T1]],0x1
2000 ; MIPS32: sll [[T0]],[[T0]],0x1f
2001 ; MIPS32: sll [[T1]],[[T1]],0x1f
2002 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
2003 ; MIPS32: andi [[T0]],[[T0]],0xffff
2004 ; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
2005 ; MIPS32: sll [[T2]],[[T2]],0x10
2006 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2007 ; MIPS32: srl [[T3:.*]],a1,0x10
2008 ; MIPS32: andi [[T3]],[[T3]],0x1
2009 ; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
2010 ; MIPS32: andi [[T4]],[[T4]],0x1
2011 ; MIPS32: sll [[T3]],[[T3]],0x1f
2012 ; MIPS32: sll [[T4]],[[T4]],0x1f
2013 ; MIPS32: slt [[T3]],[[T3]],[[T4]]
2014 ; MIPS32: sll [[T3]],[[T3]],0x10
2015 ; MIPS32: sll [[T0]],[[T0]],0x10
2016 ; MIPS32: srl [[T0]],[[T0]],0x10
2017 ; MIPS32: or [[RV_E1:.*]],[[T3]],[[T0]]
2018 ; MIPS32: andi [[T0:.*]],a2,0xffff
2019 ; MIPS32: andi [[T0]],[[T0]],0x1
2020 ; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
2021 ; MIPS32: andi [[T1]],[[T1]],0x1
2022 ; MIPS32: sll [[T0]],[[T0]],0x1f
2023 ; MIPS32: sll [[T1]],[[T1]],0x1f
2024 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
2025 ; MIPS32: andi [[T0]],[[T0]],0xffff
2026 ; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
2027 ; MIPS32: sll [[T2]],[[T2]],0x10
2028 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2029 ; MIPS32: srl [[T3:.*]],a2,0x10
2030 ; MIPS32: andi [[T3]],[[T3]],0x1
2031 ; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
2032 ; MIPS32: andi [[T4]],[[T4]],0x1
2033 ; MIPS32: sll [[T3]],[[T3]],0x1f
2034 ; MIPS32: sll [[T4]],[[T4]],0x1f
2035 ; MIPS32: slt [[T3]],[[T3]],[[T4]]
2036 ; MIPS32: sll [[T3]],[[T3]],0x10
2037 ; MIPS32: sll [[T0]],[[T0]],0x10
2038 ; MIPS32: srl [[T0]],[[T0]],0x10
2039 ; MIPS32: or [[RV_E2:.*]],[[T3]],[[T0]]
2040 ; MIPS32: andi [[T0:.*]],a3,0xffff
2041 ; MIPS32: andi [[T0]],[[T0]],0x1
2042 ; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
2043 ; MIPS32: andi [[T1]],[[T1]],0x1
2044 ; MIPS32: sll [[T0]],[[T0]],0x1f
2045 ; MIPS32: sll [[T1]],[[T1]],0x1f
2046 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
2047 ; MIPS32: andi [[T0]],[[T0]],0xffff
2048 ; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
2049 ; MIPS32: sll [[T2]],[[T2]],0x10
2050 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2051 ; MIPS32: srl [[T3:.*]],a3,0x10
2052 ; MIPS32: andi [[T3]],[[T3]],0x1
2053 ; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
2054 ; MIPS32: andi [[T4]],[[T4]],0x1
2055 ; MIPS32: sll [[T3]],[[T3]],0x1f
2056 ; MIPS32: sll [[T4]],[[T4]],0x1f
2057 ; MIPS32: slt [[T3]],[[T3]],[[T4]]
2058 ; MIPS32: sll [[T3]],[[T3]],0x10
2059 ; MIPS32: sll [[T0]],[[T0]],0x10
2060 ; MIPS32: srl [[T0]],[[T0]],0x10
2061 ; MIPS32: or [[RV_E3:.*]],[[T3]],[[T0]]
299 } 2062 }
300 2063
301 define internal <8 x i1> @test_icmp_v8i1_uge(<8 x i1> %a, <8 x i1> %b) { 2064 define internal <8 x i1> @test_icmp_v8i1_uge(<8 x i1> %a, <8 x i1> %b) {
302 entry: 2065 entry:
303 %res = icmp uge <8 x i1> %a, %b 2066 %res = icmp uge <8 x i1> %a, %b
304 ret <8 x i1> %res 2067 ret <8 x i1> %res
305 ; CHECK-LABEL: test_icmp_v8i1_uge 2068 ; CHECK-LABEL: test_icmp_v8i1_uge
306 ; CHECK: pxor 2069 ; CHECK: pxor
307 ; CHECK: pcmpgtw 2070 ; CHECK: pcmpgtw
308 ; CHECK: pxor 2071 ; CHECK: pxor
2072
2073 ; MIPS32-LABEL: test_icmp_v8i1_uge
2074 ; MIPS32: lw [[BV_E0:.*]],
2075 ; MIPS32: lw [[BV_E1:.*]],
2076 ; MIPS32: lw [[BV_E2:.*]],
2077 ; MIPS32: lw [[BV_E3:.*]],
2078 ; MIPS32: move [[TV_E0:.*]],zero
2079 ; MIPS32: move [[TV_E1:.*]],zero
2080 ; MIPS32: move [[TV_E2:.*]],zero
2081 ; MIPS32: move [[TV_E3:.*]],zero
2082 ; MIPS32: andi [[T0:.*]],a0,0xffff
2083 ; MIPS32: andi [[T0]],[[T0]],0x1
2084 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff
2085 ; MIPS32: andi [[T1]],[[T1]],0x1
2086 ; MIPS32: sll [[T0]],[[T0]],0x1f
2087 ; MIPS32: sll [[T1]],[[T1]],0x1f
2088 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
2089 ; MIPS32: xori [[T0]],[[T0]],0x1
2090 ; MIPS32: andi [[T0]],[[T0]],0xffff
2091 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10
2092 ; MIPS32: sll [[T2]],[[T2]],0x10
2093 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2094 ; MIPS32: srl [[T3:.*]],a0,0x10
2095 ; MIPS32: andi [[T3]],[[T3]],0x1
2096 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10
2097 ; MIPS32: andi [[T4]],[[T4]],0x1
2098 ; MIPS32: sll [[T3]],[[T3]],0x1f
2099 ; MIPS32: sll [[T4]],[[T4]],0x1f
2100 ; MIPS32: sltu [[T3]],[[T3]],[[T4]]
2101 ; MIPS32: xori [[T3]],[[T3]],0x1
2102 ; MIPS32: sll [[T3]],[[T3]],0x10
2103 ; MIPS32: sll [[T0]],[[T0]],0x10
2104 ; MIPS32: srl [[T0]],[[T0]],0x10
2105 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
2106 ; MIPS32: andi [[T0:.*]],a1,0xffff
2107 ; MIPS32: andi [[T0]],[[T0]],0x1
2108 ; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
2109 ; MIPS32: andi [[T1]],[[T1]],0x1
2110 ; MIPS32: sll [[T0]],[[T0]],0x1f
2111 ; MIPS32: sll [[T1]],[[T1]],0x1f
2112 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
2113 ; MIPS32: xori [[T0]],[[T0]],0x1
2114 ; MIPS32: andi [[T0]],[[T0]],0xffff
2115 ; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
2116 ; MIPS32: sll [[T2]],[[T2]],0x10
2117 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2118 ; MIPS32: srl [[T3:.*]],a1,0x10
2119 ; MIPS32: andi [[T3]],[[T3]],0x1
2120 ; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
2121 ; MIPS32: andi [[T4]],[[T4]],0x1
2122 ; MIPS32: sll [[T3]],[[T3]],0x1f
2123 ; MIPS32: sll [[T4]],[[T4]],0x1f
2124 ; MIPS32: sltu [[T3]],[[T3]],[[T4]]
2125 ; MIPS32: xori [[T3]],[[T3]],0x1
2126 ; MIPS32: sll [[T3]],[[T3]],0x10
2127 ; MIPS32: sll [[T0]],[[T0]],0x10
2128 ; MIPS32: srl [[T0]],[[T0]],0x10
2129 ; MIPS32: or [[RV_E1:.*]],[[T3]],[[T0]]
2130 ; MIPS32: andi [[T0:.*]],a2,0xffff
2131 ; MIPS32: andi [[T0]],[[T0]],0x1
2132 ; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
2133 ; MIPS32: andi [[T1]],[[T1]],0x1
2134 ; MIPS32: sll [[T0]],[[T0]],0x1f
2135 ; MIPS32: sll [[T1]],[[T1]],0x1f
2136 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
2137 ; MIPS32: xori [[T0]],[[T0]],0x1
2138 ; MIPS32: andi [[T0]],[[T0]],0xffff
2139 ; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
2140 ; MIPS32: sll [[T2]],[[T2]],0x10
2141 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2142 ; MIPS32: srl [[T3:.*]],a2,0x10
2143 ; MIPS32: andi [[T3]],[[T3]],0x1
2144 ; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
2145 ; MIPS32: andi [[T4]],[[T4]],0x1
2146 ; MIPS32: sll [[T3]],[[T3]],0x1f
2147 ; MIPS32: sll [[T4]],[[T4]],0x1f
2148 ; MIPS32: sltu [[T3]],[[T3]],[[T4]]
2149 ; MIPS32: xori [[T3]],[[T3]],0x1
2150 ; MIPS32: sll [[T3]],[[T3]],0x10
2151 ; MIPS32: sll [[T0]],[[T0]],0x10
2152 ; MIPS32: srl [[T0]],[[T0]],0x10
2153 ; MIPS32: or [[RV_E2:.*]],[[T3]],[[T0]]
2154 ; MIPS32: andi [[T0:.*]],a3,0xffff
2155 ; MIPS32: andi [[T0]],[[T0]],0x1
2156 ; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
2157 ; MIPS32: andi [[T1]],[[T1]],0x1
2158 ; MIPS32: sll [[T0]],[[T0]],0x1f
2159 ; MIPS32: sll [[T1]],[[T1]],0x1f
2160 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
2161 ; MIPS32: xori [[T0]],[[T0]],0x1
2162 ; MIPS32: andi [[T0]],[[T0]],0xffff
2163 ; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
2164 ; MIPS32: sll [[T2]],[[T2]],0x10
2165 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2166 ; MIPS32: srl [[T3:.*]],a3,0x10
2167 ; MIPS32: andi [[T3]],[[T3]],0x1
2168 ; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
2169 ; MIPS32: andi [[T4]],[[T4]],0x1
2170 ; MIPS32: sll [[T3]],[[T3]],0x1f
2171 ; MIPS32: sll [[T4]],[[T4]],0x1f
2172 ; MIPS32: sltu [[T3]],[[T3]],[[T4]]
2173 ; MIPS32: xori [[T3]],[[T3]],0x1
2174 ; MIPS32: sll [[T3]],[[T3]],0x10
2175 ; MIPS32: sll [[T0]],[[T0]],0x10
2176 ; MIPS32: srl [[T0]],[[T0]],0x10
2177 ; MIPS32: or [[RV_E3:.*]],[[T3]],[[T0]]
309 } 2178 }
310 2179
311 define internal <8 x i1> @test_icmp_v8i1_ugt(<8 x i1> %a, <8 x i1> %b) { 2180 define internal <8 x i1> @test_icmp_v8i1_ugt(<8 x i1> %a, <8 x i1> %b) {
312 entry: 2181 entry:
313 %res = icmp ugt <8 x i1> %a, %b 2182 %res = icmp ugt <8 x i1> %a, %b
314 ret <8 x i1> %res 2183 ret <8 x i1> %res
315 ; CHECK-LABEL: test_icmp_v8i1_ugt 2184 ; CHECK-LABEL: test_icmp_v8i1_ugt
316 ; CHECK: pxor 2185 ; CHECK: pxor
317 ; CHECK: pcmpgtw 2186 ; CHECK: pcmpgtw
2187
2188 ; MIPS32-LABEL: test_icmp_v8i1_ugt
2189 ; MIPS32: lw [[BV_E0:.*]],
2190 ; MIPS32: lw [[BV_E1:.*]],
2191 ; MIPS32: lw [[BV_E2:.*]],
2192 ; MIPS32: lw [[BV_E3:.*]],
2193 ; MIPS32: move [[TV_E0:.*]],zero
2194 ; MIPS32: move [[TV_E1:.*]],zero
2195 ; MIPS32: move [[TV_E2:.*]],zero
2196 ; MIPS32: move [[TV_E3:.*]],zero
2197 ; MIPS32: andi [[T0:.*]],a0,0xffff
2198 ; MIPS32: andi [[T0]],[[T0]],0x1
2199 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff
2200 ; MIPS32: andi [[T1]],[[T1]],0x1
2201 ; MIPS32: sll [[T0]],[[T0]],0x1f
2202 ; MIPS32: sll [[T1]],[[T1]],0x1f
2203 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
2204 ; MIPS32: andi [[T1]],[[T1]],0xffff
2205 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10
2206 ; MIPS32: sll [[T2]],[[T2]],0x10
2207 ; MIPS32: or [[T1]],[[T1]],[[T2]]
2208 ; MIPS32: srl [[T3:.*]],a0,0x10
2209 ; MIPS32: andi [[T3]],[[T3]],0x1
2210 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10
2211 ; MIPS32: andi [[T4]],[[T4]],0x1
2212 ; MIPS32: sll [[T3]],[[T3]],0x1f
2213 ; MIPS32: sll [[T4]],[[T4]],0x1f
2214 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
2215 ; MIPS32: sll [[T4]],[[T4]],0x10
2216 ; MIPS32: sll [[T1]],[[T1]],0x10
2217 ; MIPS32: srl [[T1]],[[T1]],0x10
2218 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
2219 ; MIPS32: andi [[T0:.*]],a1,0xffff
2220 ; MIPS32: andi [[T0]],[[T0]],0x1
2221 ; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
2222 ; MIPS32: andi [[T1]],[[T1]],0x1
2223 ; MIPS32: sll [[T0]],[[T0]],0x1f
2224 ; MIPS32: sll [[T1]],[[T1]],0x1f
2225 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
2226 ; MIPS32: andi [[T1]],[[T1]],0xffff
2227 ; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
2228 ; MIPS32: sll [[T2]],[[T2]],0x10
2229 ; MIPS32: or [[T1]],[[T1]],[[T2]]
2230 ; MIPS32: srl [[T3:.*]],a1,0x10
2231 ; MIPS32: andi [[T3]],[[T3]],0x1
2232 ; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
2233 ; MIPS32: andi [[T4]],[[T4]],0x1
2234 ; MIPS32: sll [[T3]],[[T3]],0x1f
2235 ; MIPS32: sll [[T4]],[[T4]],0x1f
2236 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
2237 ; MIPS32: sll [[T4]],[[T4]],0x10
2238 ; MIPS32: sll [[T1]],[[T1]],0x10
2239 ; MIPS32: srl [[T1]],[[T1]],0x10
2240 ; MIPS32: or [[RV_E1:.*]],[[T4]],[[T1]]
2241 ; MIPS32: andi [[T0:.*]],a2,0xffff
2242 ; MIPS32: andi [[T0]],[[T0]],0x1
2243 ; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
2244 ; MIPS32: andi [[T1]],[[T1]],0x1
2245 ; MIPS32: sll [[T0]],[[T0]],0x1f
2246 ; MIPS32: sll [[T1]],[[T1]],0x1f
2247 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
2248 ; MIPS32: andi [[T1]],[[T1]],0xffff
2249 ; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
2250 ; MIPS32: sll [[T2]],[[T2]],0x10
2251 ; MIPS32: or [[T1]],[[T1]],[[T2]]
2252 ; MIPS32: srl [[T3:.*]],a2,0x10
2253 ; MIPS32: andi [[T3]],[[T3]],0x1
2254 ; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
2255 ; MIPS32: andi [[T4]],[[T4]],0x1
2256 ; MIPS32: sll [[T3]],[[T3]],0x1f
2257 ; MIPS32: sll [[T4]],[[T4]],0x1f
2258 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
2259 ; MIPS32: sll [[T4]],[[T4]],0x10
2260 ; MIPS32: sll [[T1]],[[T1]],0x10
2261 ; MIPS32: srl [[T1]],[[T1]],0x10
2262 ; MIPS32: or [[RV_E2:.*]],[[T4]],[[T1]]
2263 ; MIPS32: andi [[T0:.*]],a3,0xffff
2264 ; MIPS32: andi [[T0]],[[T0]],0x1
2265 ; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
2266 ; MIPS32: andi [[T1]],[[T1]],0x1
2267 ; MIPS32: sll [[T0]],[[T0]],0x1f
2268 ; MIPS32: sll [[T1]],[[T1]],0x1f
2269 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
2270 ; MIPS32: andi [[T1]],[[T1]],0xffff
2271 ; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
2272 ; MIPS32: sll [[T2]],[[T2]],0x10
2273 ; MIPS32: or [[T1]],[[T1]],[[T2]]
2274 ; MIPS32: srl [[T3:.*]],a3,0x10
2275 ; MIPS32: andi [[T3]],[[T3]],0x1
2276 ; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
2277 ; MIPS32: andi [[T4]],[[T4]],0x1
2278 ; MIPS32: sll [[T3]],[[T3]],0x1f
2279 ; MIPS32: sll [[T4]],[[T4]],0x1f
2280 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
2281 ; MIPS32: sll [[T4]],[[T4]],0x10
2282 ; MIPS32: sll [[T1]],[[T1]],0x10
2283 ; MIPS32: srl [[T1]],[[T1]],0x10
2284 ; MIPS32: or [[RV_E3:.*]],[[T4]],[[T1]]
318 } 2285 }
319 2286
320 define internal <8 x i1> @test_icmp_v8i1_ule(<8 x i1> %a, <8 x i1> %b) { 2287 define internal <8 x i1> @test_icmp_v8i1_ule(<8 x i1> %a, <8 x i1> %b) {
321 entry: 2288 entry:
322 %res = icmp ule <8 x i1> %a, %b 2289 %res = icmp ule <8 x i1> %a, %b
323 ret <8 x i1> %res 2290 ret <8 x i1> %res
324 ; CHECK-LABEL: test_icmp_v8i1_ule 2291 ; CHECK-LABEL: test_icmp_v8i1_ule
325 ; CHECK: pxor 2292 ; CHECK: pxor
326 ; CHECK: pcmpgtw 2293 ; CHECK: pcmpgtw
327 ; CHECK: pxor 2294 ; CHECK: pxor
2295
2296 ; MIPS32-LABEL: test_icmp_v8i1_ule
2297 ; MIPS32: lw [[BV_E0:.*]],
2298 ; MIPS32: lw [[BV_E1:.*]],
2299 ; MIPS32: lw [[BV_E2:.*]],
2300 ; MIPS32: lw [[BV_E3:.*]],
2301 ; MIPS32: move [[TV_E0:.*]],zero
2302 ; MIPS32: move [[TV_E1:.*]],zero
2303 ; MIPS32: move [[TV_E2:.*]],zero
2304 ; MIPS32: move [[TV_E3:.*]],zero
2305 ; MIPS32: andi [[T0:.*]],a0,0xffff
2306 ; MIPS32: andi [[T0]],[[T0]],0x1
2307 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff
2308 ; MIPS32: andi [[T1]],[[T1]],0x1
2309 ; MIPS32: sll [[T0]],[[T0]],0x1f
2310 ; MIPS32: sll [[T1]],[[T1]],0x1f
2311 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
2312 ; MIPS32: xori [[T1]],[[T1]],0x1
2313 ; MIPS32: andi [[T1]],[[T1]],0xffff
2314 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10
2315 ; MIPS32: sll [[T2]],[[T2]],0x10
2316 ; MIPS32: or [[T1]],[[T1]],[[T2]]
2317 ; MIPS32: srl [[T3:.*]],a0,0x10
2318 ; MIPS32: andi [[T3]],[[T3]],0x1
2319 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10
2320 ; MIPS32: andi [[T4]],[[T4]],0x1
2321 ; MIPS32: sll [[T3]],[[T3]],0x1f
2322 ; MIPS32: sll [[T4]],[[T4]],0x1f
2323 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
2324 ; MIPS32: xori [[T4]],[[T4]],0x1
2325 ; MIPS32: sll [[T4]],[[T4]],0x10
2326 ; MIPS32: sll [[T1]],[[T1]],0x10
2327 ; MIPS32: srl [[T1]],[[T1]],0x10
2328 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
2329 ; MIPS32: andi [[T0:.*]],a1,0xffff
2330 ; MIPS32: andi [[T0]],[[T0]],0x1
2331 ; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
2332 ; MIPS32: andi [[T1]],[[T1]],0x1
2333 ; MIPS32: sll [[T0]],[[T0]],0x1f
2334 ; MIPS32: sll [[T1]],[[T1]],0x1f
2335 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
2336 ; MIPS32: xori [[T1]],[[T1]],0x1
2337 ; MIPS32: andi [[T1]],[[T1]],0xffff
2338 ; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
2339 ; MIPS32: sll [[T2]],[[T2]],0x10
2340 ; MIPS32: or [[T1]],[[T1]],[[T2]]
2341 ; MIPS32: srl [[T3:.*]],a1,0x10
2342 ; MIPS32: andi [[T3]],[[T3]],0x1
2343 ; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
2344 ; MIPS32: andi [[T4]],[[T4]],0x1
2345 ; MIPS32: sll [[T3]],[[T3]],0x1f
2346 ; MIPS32: sll [[T4]],[[T4]],0x1f
2347 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
2348 ; MIPS32: xori [[T4]],[[T4]],0x1
2349 ; MIPS32: sll [[T4]],[[T4]],0x10
2350 ; MIPS32: sll [[T1]],[[T1]],0x10
2351 ; MIPS32: srl [[T1]],[[T1]],0x10
2352 ; MIPS32: or [[RV_E1:.*]],[[T4]],[[T1]]
2353 ; MIPS32: andi [[T0:.*]],a2,0xffff
2354 ; MIPS32: andi [[T0]],[[T0]],0x1
2355 ; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
2356 ; MIPS32: andi [[T1]],[[T1]],0x1
2357 ; MIPS32: sll [[T0]],[[T0]],0x1f
2358 ; MIPS32: sll [[T1]],[[T1]],0x1f
2359 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
2360 ; MIPS32: xori [[T1]],[[T1]],0x1
2361 ; MIPS32: andi [[T1]],[[T1]],0xffff
2362 ; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
2363 ; MIPS32: sll [[T2]],[[T2]],0x10
2364 ; MIPS32: or [[T1]],[[T1]],[[T2]]
2365 ; MIPS32: srl [[T3:.*]],a2,0x10
2366 ; MIPS32: andi [[T3]],[[T3]],0x1
2367 ; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
2368 ; MIPS32: andi [[T4]],[[T4]],0x1
2369 ; MIPS32: sll [[T3]],[[T3]],0x1f
2370 ; MIPS32: sll [[T4]],[[T4]],0x1f
2371 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
2372 ; MIPS32: xori [[T4]],[[T4]],0x1
2373 ; MIPS32: sll [[T4]],[[T4]],0x10
2374 ; MIPS32: sll [[T1]],[[T1]],0x10
2375 ; MIPS32: srl [[T1]],[[T1]],0x10
2376 ; MIPS32: or [[RV_E2:.*]],[[T4]],[[T1]]
2377 ; MIPS32: andi [[T0:.*]],a3,0xffff
2378 ; MIPS32: andi [[T0]],[[T0]],0x1
2379 ; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
2380 ; MIPS32: andi [[T1]],[[T1]],0x1
2381 ; MIPS32: sll [[T0]],[[T0]],0x1f
2382 ; MIPS32: sll [[T1]],[[T1]],0x1f
2383 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
2384 ; MIPS32: xori [[T1]],[[T1]],0x1
2385 ; MIPS32: andi [[T1]],[[T1]],0xffff
2386 ; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
2387 ; MIPS32: sll [[T2]],[[T2]],0x10
2388 ; MIPS32: or [[T1]],[[T1]],[[T2]]
2389 ; MIPS32: srl [[T3:.*]],a3,0x10
2390 ; MIPS32: andi [[T3]],[[T3]],0x1
2391 ; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
2392 ; MIPS32: andi [[T4]],[[T4]],0x1
2393 ; MIPS32: sll [[T3]],[[T3]],0x1f
2394 ; MIPS32: sll [[T4]],[[T4]],0x1f
2395 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
2396 ; MIPS32: xori [[T4]],[[T4]],0x1
2397 ; MIPS32: sll [[T4]],[[T4]],0x10
2398 ; MIPS32: sll [[T1]],[[T1]],0x10
2399 ; MIPS32: srl [[T1]],[[T1]],0x10
2400 ; MIPS32: or [[RV_E3:.*]],[[T4]],[[T1]]
328 } 2401 }
329 2402
330 define internal <8 x i1> @test_icmp_v8i1_ult(<8 x i1> %a, <8 x i1> %b) { 2403 define internal <8 x i1> @test_icmp_v8i1_ult(<8 x i1> %a, <8 x i1> %b) {
331 entry: 2404 entry:
332 %res = icmp ult <8 x i1> %a, %b 2405 %res = icmp ult <8 x i1> %a, %b
333 ret <8 x i1> %res 2406 ret <8 x i1> %res
334 ; CHECK-LABEL: test_icmp_v8i1_ult 2407 ; CHECK-LABEL: test_icmp_v8i1_ult
335 ; CHECK: pxor 2408 ; CHECK: pxor
336 ; CHECK: pcmpgtw 2409 ; CHECK: pcmpgtw
2410
2411 ; MIPS32-LABEL: test_icmp_v8i1_ult
2412 ; MIPS32: lw [[BV_E0:.*]],
2413 ; MIPS32: lw [[BV_E1:.*]],
2414 ; MIPS32: lw [[BV_E2:.*]],
2415 ; MIPS32: lw [[BV_E3:.*]],
2416 ; MIPS32: move [[TV_E0:.*]],zero
2417 ; MIPS32: move [[TV_E1:.*]],zero
2418 ; MIPS32: move [[TV_E2:.*]],zero
2419 ; MIPS32: move [[TV_E3:.*]],zero
2420 ; MIPS32: andi [[T0:.*]],a0,0xffff
2421 ; MIPS32: andi [[T0]],[[T0]],0x1
2422 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff
2423 ; MIPS32: andi [[T1]],[[T1]],0x1
2424 ; MIPS32: sll [[T0]],[[T0]],0x1f
2425 ; MIPS32: sll [[T1]],[[T1]],0x1f
2426 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
2427 ; MIPS32: andi [[T0]],[[T0]],0xffff
2428 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10
2429 ; MIPS32: sll [[T2]],[[T2]],0x10
2430 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2431 ; MIPS32: srl [[T3:.*]],a0,0x10
2432 ; MIPS32: andi [[T3]],[[T3]],0x1
2433 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10
2434 ; MIPS32: andi [[T4]],[[T4]],0x1
2435 ; MIPS32: sll [[T3]],[[T3]],0x1f
2436 ; MIPS32: sll [[T4]],[[T4]],0x1f
2437 ; MIPS32: sltu [[T3]],[[T3]],[[T4]]
2438 ; MIPS32: sll [[T3]],[[T3]],0x10
2439 ; MIPS32: sll [[T0]],[[T0]],0x10
2440 ; MIPS32: srl [[T0]],[[T0]],0x10
2441 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
2442 ; MIPS32: andi [[T0:.*]],a1,0xffff
2443 ; MIPS32: andi [[T0]],[[T0]],0x1
2444 ; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
2445 ; MIPS32: andi [[T1]],[[T1]],0x1
2446 ; MIPS32: sll [[T0]],[[T0]],0x1f
2447 ; MIPS32: sll [[T1]],[[T1]],0x1f
2448 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
2449 ; MIPS32: andi [[T0]],[[T0]],0xffff
2450 ; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
2451 ; MIPS32: sll [[T2]],[[T2]],0x10
2452 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2453 ; MIPS32: srl [[T3:.*]],a1,0x10
2454 ; MIPS32: andi [[T3]],[[T3]],0x1
2455 ; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
2456 ; MIPS32: andi [[T4]],[[T4]],0x1
2457 ; MIPS32: sll [[T3]],[[T3]],0x1f
2458 ; MIPS32: sll [[T4]],[[T4]],0x1f
2459 ; MIPS32: sltu [[T3]],[[T3]],[[T4]]
2460 ; MIPS32: sll [[T3]],[[T3]],0x10
2461 ; MIPS32: sll [[T0]],[[T0]],0x10
2462 ; MIPS32: srl [[T0]],[[T0]],0x10
2463 ; MIPS32: or [[RV_E1:.*]],[[T3]],[[T0]]
2464 ; MIPS32: andi [[T0:.*]],a2,0xffff
2465 ; MIPS32: andi [[T0]],[[T0]],0x1
2466 ; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
2467 ; MIPS32: andi [[T1]],[[T1]],0x1
2468 ; MIPS32: sll [[T0]],[[T0]],0x1f
2469 ; MIPS32: sll [[T1]],[[T1]],0x1f
2470 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
2471 ; MIPS32: andi [[T0]],[[T0]],0xffff
2472 ; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
2473 ; MIPS32: sll [[T2]],[[T2]],0x10
2474 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2475 ; MIPS32: srl [[T3:.*]],a2,0x10
2476 ; MIPS32: andi [[T3]],[[T3]],0x1
2477 ; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
2478 ; MIPS32: andi [[T4]],[[T4]],0x1
2479 ; MIPS32: sll [[T3]],[[T3]],0x1f
2480 ; MIPS32: sll [[T4]],[[T4]],0x1f
2481 ; MIPS32: sltu [[T3]],[[T3]],[[T4]]
2482 ; MIPS32: sll [[T3]],[[T3]],0x10
2483 ; MIPS32: sll [[T0]],[[T0]],0x10
2484 ; MIPS32: srl [[T0]],[[T0]],0x10
2485 ; MIPS32: or [[RV_E2:.*]],[[T3]],[[T0]]
2486 ; MIPS32: andi [[T0:.*]],a3,0xffff
2487 ; MIPS32: andi [[T0]],[[T0]],0x1
2488 ; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
2489 ; MIPS32: andi [[T1]],[[T1]],0x1
2490 ; MIPS32: sll [[T0]],[[T0]],0x1f
2491 ; MIPS32: sll [[T1]],[[T1]],0x1f
2492 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
2493 ; MIPS32: andi [[T0]],[[T0]],0xffff
2494 ; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
2495 ; MIPS32: sll [[T2]],[[T2]],0x10
2496 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2497 ; MIPS32: srl [[T3:.*]],a3,0x10
2498 ; MIPS32: andi [[T3]],[[T3]],0x1
2499 ; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
2500 ; MIPS32: andi [[T4]],[[T4]],0x1
2501 ; MIPS32: sll [[T3]],[[T3]],0x1f
2502 ; MIPS32: sll [[T4]],[[T4]],0x1f
2503 ; MIPS32: sltu [[T3]],[[T3]],[[T4]]
2504 ; MIPS32: sll [[T3]],[[T3]],0x10
2505 ; MIPS32: sll [[T0]],[[T0]],0x10
2506 ; MIPS32: srl [[T0]],[[T0]],0x10
2507 ; MIPS32: or [[RV_E3:.*]],[[T3]],[[T0]]
337 } 2508 }
338 2509
339 define internal <16 x i1> @test_icmp_v16i8_eq(<16 x i8> %a, <16 x i8> %b) { 2510 define internal <16 x i1> @test_icmp_v16i8_eq(<16 x i8> %a, <16 x i8> %b) {
340 entry: 2511 entry:
341 %res = icmp eq <16 x i8> %a, %b 2512 %res = icmp eq <16 x i8> %a, %b
342 ret <16 x i1> %res 2513 ret <16 x i1> %res
343 ; CHECK-LABEL: test_icmp_v16i8_eq 2514 ; CHECK-LABEL: test_icmp_v16i8_eq
344 ; CHECK: pcmpeqb 2515 ; CHECK: pcmpeqb
2516
2517 ; MIPS32-LABEL: test_icmp_v16i8_eq
2518 ; MIPS32: lw [[BV_E0:.*]],
2519 ; MIPS32: lw [[BV_E1:.*]],
2520 ; MIPS32: lw [[BV_E2:.*]],
2521 ; MIPS32: lw [[BV_E3:.*]],
2522 ; MIPS32: move [[TV_E0:.*]],zero
2523 ; MIPS32: move [[TV_E1:.*]],zero
2524 ; MIPS32: move [[TV_E2:.*]],zero
2525 ; MIPS32: move [[TV_E3:.*]],zero
2526 ; MIPS32: andi [[T0:.*]],a0,0xff
2527 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
2528 ; MIPS32: sll [[T0]],[[T0]],0x18
2529 ; MIPS32: sll [[T1]],[[T1]],0x18
2530 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
2531 ; MIPS32: sltiu [[T0]],[[T0]],1
2532 ; MIPS32: andi [[T0]],[[T0]],0xff
2533 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
2534 ; MIPS32: sll [[T2]],[[TV_E0]],0x8
2535 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2536 ; MIPS32: srl [[T2]],a0,0x8
2537 ; MIPS32: andi [[T2]],[[T2]],0xff
2538 ; MIPS32: srl [[T1]],[[BV_E0]],0x8
2539 ; MIPS32: andi [[T1]],[[T1]],0xff
2540 ; MIPS32: sll [[T2]],[[T2]],0x18
2541 ; MIPS32: sll [[T1]],[[T1]],0x18
2542 ; MIPS32: xor [[T2]],[[T2]],[[T1]]
2543 ; MIPS32: sltiu [[T2]],[[T2]],1
2544 ; MIPS32: andi [[T2]],[[T2]],0xff
2545 ; MIPS32: sll [[T2]],[[T2]],0x8
2546 ; MIPS32: lui [[T1]],0xffff
2547 ; MIPS32: ori [[T1]],[[T1]],0xff
2548 ; MIPS32: and [[T0]],[[T0]],[[T1]]
2549 ; MIPS32: or [[T2]],[[T2]],[[T0]]
2550 ; MIPS32: srl [[T0]],a0,0x10
2551 ; MIPS32: andi [[T0]],[[T0]],0xff
2552 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
2553 ; MIPS32: andi [[T1]],[[T1]],0xff
2554 ; MIPS32: sll [[T0]],[[T0]],0x18
2555 ; MIPS32: sll [[T1]],[[T1]],0x18
2556 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
2557 ; MIPS32: sltiu [[T0]],[[T0]],1
2558 ; MIPS32: andi [[T0]],[[T0]],0xff
2559 ; MIPS32: sll [[T0]],[[T0]],0x10
2560 ; MIPS32: lui [[T1]],0xff00
2561 ; MIPS32: ori [[T1]],[[T1]],0xffff
2562 ; MIPS32: and [[T2]],[[T2]],[[T1]]
2563 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2564 ; MIPS32: srl [[T3:.*]],a0,0x18
2565 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
2566 ; MIPS32: sll [[T3]],[[T3]],0x18
2567 ; MIPS32: sll [[T4]],[[T4]],0x18
2568 ; MIPS32: xor [[T3]],[[T3]],[[T4]]
2569 ; MIPS32: sltiu [[T3]],[[T3]],1
2570 ; MIPS32: srl [[T3]],[[T3]],0x18
2571 ; MIPS32: sll [[T0]],[[T0]],0x8
2572 ; MIPS32: srl [[T0]],[[T0]],0x8
2573 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
2574 ; MIPS32: andi [[T4]],a1,0xff
2575 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
2576 ; MIPS32: sll [[T4]],[[T4]],0x18
2577 ; MIPS32: sll [[T2]],[[T2]],0x18
2578 ; MIPS32: xor [[T4]],[[T4]],[[T2]]
2579 ; MIPS32: sltiu [[T4]],[[T4]],1
2580 ; MIPS32: andi [[T4]],[[T4]],0xff
2581 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
2582 ; MIPS32: sll [[T5]],[[TV_E1]],0x8
2583 ; MIPS32: or [[T4]],[[T4]],[[T5]]
2584 ; MIPS32: srl [[T2]],a1,0x8
2585 ; MIPS32: andi [[T2]],[[T2]],0xff
2586 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
2587 ; MIPS32: andi [[T5]],[[T5]],0xff
2588 ; MIPS32: sll [[T2]],[[T2]],0x18
2589 ; MIPS32: sll [[T5]],[[T5]],0x18
2590 ; MIPS32: xor [[T2]],[[T2]],[[T5]]
2591 ; MIPS32: sltiu [[T2]],[[T2]],1
2592 ; MIPS32: andi [[T2]],[[T2]],0xff
2593 ; MIPS32: sll [[T2]],[[T2]],0x8
2594 ; MIPS32: lui [[T5]],0xffff
2595 ; MIPS32: ori [[T5]],[[T5]],0xff
2596 ; MIPS32: and [[T4]],[[T4]],[[T5]]
2597 ; MIPS32: or [[T2]],[[T2]],[[T4]]
2598 ; MIPS32: srl [[T4]],a1,0x10
2599 ; MIPS32: andi [[T4]],[[T4]],0xff
2600 ; MIPS32: srl [[T5]],[[BV_E1]],0x10
2601 ; MIPS32: andi [[T5]],[[T5]],0xff
2602 ; MIPS32: sll [[T4]],[[T4]],0x18
2603 ; MIPS32: sll [[T5]],[[T5]],0x18
2604 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
2605 ; MIPS32: sltiu [[T4]],[[T4]],1
2606 ; MIPS32: andi [[T4]],[[T4]],0xff
2607 ; MIPS32: sll [[T4]],[[T4]],0x10
2608 ; MIPS32: lui [[T5]],0xff00
2609 ; MIPS32: ori [[T5]],[[T5]],0xffff
2610 ; MIPS32: and [[T2]],[[T2]],[[T5]]
2611 ; MIPS32: or [[T4]],[[T4]],[[T2]]
2612 ; MIPS32: srl [[T6:.*]],a1,0x18
2613 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
2614 ; MIPS32: sll [[T6]],[[T6]],0x18
2615 ; MIPS32: sll [[T7]],[[T7]],0x18
2616 ; MIPS32: xor [[T6]],[[T6]],[[T7]]
2617 ; MIPS32: sltiu [[T6]],[[T6]],1
2618 ; MIPS32: srl [[T6]],[[T6]],0x18
2619 ; MIPS32: sll [[T4]],[[T4]],0x8
2620 ; MIPS32: srl [[T4]],[[T4]],0x8
2621 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
2622 ; MIPS32: andi [[T4]],a2,0xff
2623 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
2624 ; MIPS32: sll [[T4]],[[T4]],0x18
2625 ; MIPS32: sll [[T7]],[[T7]],0x18
2626 ; MIPS32: xor [[T4]],[[T4]],[[T7]]
2627 ; MIPS32: sltiu [[T4]],[[T4]],1
2628 ; MIPS32: andi [[T4]],[[T4]],0xff
2629 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
2630 ; MIPS32: sll [[T8]],[[TV_E2]],0x8
2631 ; MIPS32: or [[T4]],[[T4]],[[T8]]
2632 ; MIPS32: srl [[T7]],a2,0x8
2633 ; MIPS32: andi [[T7]],[[T7]],0xff
2634 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
2635 ; MIPS32: andi [[T2]],[[T2]],0xff
2636 ; MIPS32: sll [[T7]],[[T7]],0x18
2637 ; MIPS32: sll [[T2]],[[T2]],0x18
2638 ; MIPS32: xor [[T7]],[[T7]],[[T2]]
2639 ; MIPS32: sltiu [[T7]],[[T7]],1
2640 ; MIPS32: andi [[T7]],[[T7]],0xff
2641 ; MIPS32: sll [[T7]],[[T7]],0x8
2642 ; MIPS32: lui [[T2]],0xffff
2643 ; MIPS32: ori [[T2]],[[T2]],0xff
2644 ; MIPS32: and [[T4]],[[T4]],[[T2]]
2645 ; MIPS32: or [[T7]],[[T7]],[[T4]]
2646 ; MIPS32: srl [[T4]],a2,0x10
2647 ; MIPS32: andi [[T4]],[[T4]],0xff
2648 ; MIPS32: srl [[T2]],[[BV_E2]],0x10
2649 ; MIPS32: andi [[T2]],[[T2]],0xff
2650 ; MIPS32: sll [[T4]],[[T4]],0x18
2651 ; MIPS32: sll [[T2]],[[T2]],0x18
2652 ; MIPS32: xor [[T4]],[[T4]],[[T2]]
2653 ; MIPS32: sltiu [[T4]],[[T4]],1
2654 ; MIPS32: andi [[T4]],[[T4]],0xff
2655 ; MIPS32: sll [[T4]],[[T4]],0x10
2656 ; MIPS32: lui [[T2]],0xff00
2657 ; MIPS32: ori [[T2]],[[T2]],0xffff
2658 ; MIPS32: and [[T7]],[[T7]],[[T2]]
2659 ; MIPS32: or [[T4]],[[T4]],[[T7]]
2660 ; MIPS32: srl [[T9:.*]],a2,0x18
2661 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
2662 ; MIPS32: sll [[T9]],[[T9]],0x18
2663 ; MIPS32: sll [[T10]],[[T10]],0x18
2664 ; MIPS32: xor [[T9]],[[T9]],[[T10]]
2665 ; MIPS32: sltiu [[T9]],[[T9]],1
2666 ; MIPS32: srl [[T9]],[[T9]],0x18
2667 ; MIPS32: sll [[T4]],[[T4]],0x8
2668 ; MIPS32: srl [[T4]],[[T4]],0x8
2669 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
2670 ; MIPS32: andi [[T4]],a3,0xff
2671 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
2672 ; MIPS32: sll [[T4]],[[T4]],0x18
2673 ; MIPS32: sll [[T7]],[[T7]],0x18
2674 ; MIPS32: xor [[T4]],[[T4]],[[T7]]
2675 ; MIPS32: sltiu [[T4]],[[T4]],1
2676 ; MIPS32: andi [[T4]],[[T4]],0xff
2677 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
2678 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
2679 ; MIPS32: or [[T4]],[[T4]],[[T11]]
2680 ; MIPS32: srl [[T7]],a3,0x8
2681 ; MIPS32: andi [[T7]],[[T7]],0xff
2682 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
2683 ; MIPS32: andi [[T10]],[[T10]],0xff
2684 ; MIPS32: sll [[T7]],[[T7]],0x18
2685 ; MIPS32: sll [[T10]],[[T10]],0x18
2686 ; MIPS32: xor [[T7]],[[T7]],[[T10]]
2687 ; MIPS32: sltiu [[T7]],[[T7]],1
2688 ; MIPS32: andi [[T7]],[[T7]],0xff
2689 ; MIPS32: sll [[T7]],[[T7]],0x8
2690 ; MIPS32: lui [[T10]],0xffff
2691 ; MIPS32: ori [[T10]],[[T10]],0xff
2692 ; MIPS32: and [[T4]],[[T4]],[[T10]]
2693 ; MIPS32: or [[T7]],[[T7]],[[T4]]
2694 ; MIPS32: srl [[T4]],a3,0x10
2695 ; MIPS32: andi [[T4]],[[T4]],0xff
2696 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
2697 ; MIPS32: andi [[T10]],[[T10]],0xff
2698 ; MIPS32: sll [[T4]],[[T4]],0x18
2699 ; MIPS32: sll [[T10]],[[T10]],0x18
2700 ; MIPS32: xor [[T4]],[[T4]],[[T10]]
2701 ; MIPS32: sltiu [[T4]],[[T4]],1
2702 ; MIPS32: andi [[T4]],[[T4]],0xff
2703 ; MIPS32: sll [[T4]],[[T4]],0x10
2704 ; MIPS32: lui [[T10]],0xff00
2705 ; MIPS32: ori [[T10]],[[T10]],0xffff
2706 ; MIPS32: and [[T7]],[[T7]],[[T10]]
2707 ; MIPS32: or [[T4]],[[T4]],[[T7]]
2708 ; MIPS32: srl [[T12:.*]],a3,0x18
2709 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
2710 ; MIPS32: sll [[T12]],[[T12]],0x18
2711 ; MIPS32: sll [[T13]],[[T13]],0x18
2712 ; MIPS32: xor [[T12]],[[T12]],[[T13]]
2713 ; MIPS32: sltiu [[T12]],[[T12]],1
2714 ; MIPS32: srl [[T12]],[[T12]],0x18
2715 ; MIPS32: sll [[T4]],[[T4]],0x8
2716 ; MIPS32: srl [[T4]],[[T4]],0x8
2717 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
345 } 2718 }
346 2719
347 define internal <16 x i1> @test_icmp_v16i8_ne(<16 x i8> %a, <16 x i8> %b) { 2720 define internal <16 x i1> @test_icmp_v16i8_ne(<16 x i8> %a, <16 x i8> %b) {
348 entry: 2721 entry:
349 %res = icmp ne <16 x i8> %a, %b 2722 %res = icmp ne <16 x i8> %a, %b
350 ret <16 x i1> %res 2723 ret <16 x i1> %res
351 ; CHECK-LABEL: test_icmp_v16i8_ne 2724 ; CHECK-LABEL: test_icmp_v16i8_ne
352 ; CHECK: pcmpeqb 2725 ; CHECK: pcmpeqb
353 ; CHECK: pxor 2726 ; CHECK: pxor
2727
2728 ; MIPS32-LABEL: test_icmp_v16i8_ne
2729 ; MIPS32: lw [[BV_E0:.*]],
2730 ; MIPS32: lw [[BV_E1:.*]],
2731 ; MIPS32: lw [[BV_E2:.*]],
2732 ; MIPS32: lw [[BV_E3:.*]],
2733 ; MIPS32: move [[TV_E0:.*]],zero
2734 ; MIPS32: move [[TV_E1:.*]],zero
2735 ; MIPS32: move [[TV_E2:.*]],zero
2736 ; MIPS32: move [[TV_E3:.*]],zero
2737 ; MIPS32: andi [[T0:.*]],a0,0xff
2738 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
2739 ; MIPS32: sll [[T0]],[[T0]],0x18
2740 ; MIPS32: sll [[T1]],[[T1]],0x18
2741 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
2742 ; MIPS32: sltu [[T0]],zero,[[T0]]
2743 ; MIPS32: andi [[T0]],[[T0]],0xff
2744 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
2745 ; MIPS32: sll [[T2]],[[TV_E0]],0x8
2746 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2747 ; MIPS32: srl [[T2]],a0,0x8
2748 ; MIPS32: andi [[T2]],[[T2]],0xff
2749 ; MIPS32: srl [[T1]],[[BV_E0]],0x8
2750 ; MIPS32: andi [[T1]],[[T1]],0xff
2751 ; MIPS32: sll [[T2]],[[T2]],0x18
2752 ; MIPS32: sll [[T1]],[[T1]],0x18
2753 ; MIPS32: xor [[T2]],[[T2]],[[T1]]
2754 ; MIPS32: sltu [[T2]],zero,[[T2]]
2755 ; MIPS32: andi [[T2]],[[T2]],0xff
2756 ; MIPS32: sll [[T2]],[[T2]],0x8
2757 ; MIPS32: lui [[T1]],0xffff
2758 ; MIPS32: ori [[T1]],[[T1]],0xff
2759 ; MIPS32: and [[T0]],[[T0]],[[T1]]
2760 ; MIPS32: or [[T2]],[[T2]],[[T0]]
2761 ; MIPS32: srl [[T0]],a0,0x10
2762 ; MIPS32: andi [[T0]],[[T0]],0xff
2763 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
2764 ; MIPS32: andi [[T1]],[[T1]],0xff
2765 ; MIPS32: sll [[T0]],[[T0]],0x18
2766 ; MIPS32: sll [[T1]],[[T1]],0x18
2767 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
2768 ; MIPS32: sltu [[T0]],zero,[[T0]]
2769 ; MIPS32: andi [[T0]],[[T0]],0xff
2770 ; MIPS32: sll [[T0]],[[T0]],0x10
2771 ; MIPS32: lui [[T1]],0xff00
2772 ; MIPS32: ori [[T1]],[[T1]],0xffff
2773 ; MIPS32: and [[T2]],[[T2]],[[T1]]
2774 ; MIPS32: or [[T0]],[[T0]],[[T2]]
2775 ; MIPS32: srl [[T3:.*]],a0,0x18
2776 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
2777 ; MIPS32: sll [[T3]],[[T3]],0x18
2778 ; MIPS32: sll [[T4]],[[T4]],0x18
2779 ; MIPS32: xor [[T3]],[[T3]],[[T4]]
2780 ; MIPS32: sltu [[T3]],zero,[[T3]]
2781 ; MIPS32: srl [[T3]],[[T3]],0x18
2782 ; MIPS32: sll [[T0]],[[T0]],0x8
2783 ; MIPS32: srl [[T0]],[[T0]],0x8
2784 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
2785 ; MIPS32: andi [[T4]],a1,0xff
2786 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
2787 ; MIPS32: sll [[T4]],[[T4]],0x18
2788 ; MIPS32: sll [[T2]],[[T2]],0x18
2789 ; MIPS32: xor [[T4]],[[T4]],[[T2]]
2790 ; MIPS32: sltu [[T4]],zero,[[T4]]
2791 ; MIPS32: andi [[T4]],[[T4]],0xff
2792 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
2793 ; MIPS32: sll [[T5]],[[TV_E1]],0x8
2794 ; MIPS32: or [[T4]],[[T4]],[[T5]]
2795 ; MIPS32: srl [[T2]],a1,0x8
2796 ; MIPS32: andi [[T2]],[[T2]],0xff
2797 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
2798 ; MIPS32: andi [[T5]],[[T5]],0xff
2799 ; MIPS32: sll [[T2]],[[T2]],0x18
2800 ; MIPS32: sll [[T5]],[[T5]],0x18
2801 ; MIPS32: xor [[T2]],[[T2]],[[T5]]
2802 ; MIPS32: sltu [[T2]],zero,[[T2]]
2803 ; MIPS32: andi [[T2]],[[T2]],0xff
2804 ; MIPS32: sll [[T2]],[[T2]],0x8
2805 ; MIPS32: lui [[T5]],0xffff
2806 ; MIPS32: ori [[T5]],[[T5]],0xff
2807 ; MIPS32: and [[T4]],[[T4]],[[T5]]
2808 ; MIPS32: or [[T2]],[[T2]],[[T4]]
2809 ; MIPS32: srl [[T4]],a1,0x10
2810 ; MIPS32: andi [[T4]],[[T4]],0xff
2811 ; MIPS32: srl [[T5]],[[BV_E1]],0x10
2812 ; MIPS32: andi [[T5]],[[T5]],0xff
2813 ; MIPS32: sll [[T4]],[[T4]],0x18
2814 ; MIPS32: sll [[T5]],[[T5]],0x18
2815 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
2816 ; MIPS32: sltu [[T4]],zero,[[T4]]
2817 ; MIPS32: andi [[T4]],[[T4]],0xff
2818 ; MIPS32: sll [[T4]],[[T4]],0x10
2819 ; MIPS32: lui [[T5]],0xff00
2820 ; MIPS32: ori [[T5]],[[T5]],0xffff
2821 ; MIPS32: and [[T2]],[[T2]],[[T5]]
2822 ; MIPS32: or [[T4]],[[T4]],[[T2]]
2823 ; MIPS32: srl [[T6:.*]],a1,0x18
2824 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
2825 ; MIPS32: sll [[T6]],[[T6]],0x18
2826 ; MIPS32: sll [[T7]],[[T7]],0x18
2827 ; MIPS32: xor [[T6]],[[T6]],[[T7]]
2828 ; MIPS32: sltu [[T6]],zero,[[T6]]
2829 ; MIPS32: srl [[T6]],[[T6]],0x18
2830 ; MIPS32: sll [[T4]],[[T4]],0x8
2831 ; MIPS32: srl [[T4]],[[T4]],0x8
2832 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
2833 ; MIPS32: andi [[T4]],a2,0xff
2834 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
2835 ; MIPS32: sll [[T4]],[[T4]],0x18
2836 ; MIPS32: sll [[T7]],[[T7]],0x18
2837 ; MIPS32: xor [[T4]],[[T4]],[[T7]]
2838 ; MIPS32: sltu [[T4]],zero,[[T4]]
2839 ; MIPS32: andi [[T4]],[[T4]],0xff
2840 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
2841 ; MIPS32: sll [[T8]],[[TV_E2]],0x8
2842 ; MIPS32: or [[T4]],[[T4]],[[T8]]
2843 ; MIPS32: srl [[T7]],a2,0x8
2844 ; MIPS32: andi [[T7]],[[T7]],0xff
2845 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
2846 ; MIPS32: andi [[T2]],[[T2]],0xff
2847 ; MIPS32: sll [[T7]],[[T7]],0x18
2848 ; MIPS32: sll [[T2]],[[T2]],0x18
2849 ; MIPS32: xor [[T7]],[[T7]],[[T2]]
2850 ; MIPS32: sltu [[T7]],zero,[[T7]]
2851 ; MIPS32: andi [[T7]],[[T7]],0xff
2852 ; MIPS32: sll [[T7]],[[T7]],0x8
2853 ; MIPS32: lui [[T2]],0xffff
2854 ; MIPS32: ori [[T2]],[[T2]],0xff
2855 ; MIPS32: and [[T4]],[[T4]],[[T2]]
2856 ; MIPS32: or [[T7]],[[T7]],[[T4]]
2857 ; MIPS32: srl [[T4]],a2,0x10
2858 ; MIPS32: andi [[T4]],[[T4]],0xff
2859 ; MIPS32: srl [[T2]],[[BV_E2]],0x10
2860 ; MIPS32: andi [[T2]],[[T2]],0xff
2861 ; MIPS32: sll [[T4]],[[T4]],0x18
2862 ; MIPS32: sll [[T2]],[[T2]],0x18
2863 ; MIPS32: xor [[T4]],[[T4]],[[T2]]
2864 ; MIPS32: sltu [[T4]],zero,[[T4]]
2865 ; MIPS32: andi [[T4]],[[T4]],0xff
2866 ; MIPS32: sll [[T4]],[[T4]],0x10
2867 ; MIPS32: lui [[T2]],0xff00
2868 ; MIPS32: ori [[T2]],[[T2]],0xffff
2869 ; MIPS32: and [[T7]],[[T7]],[[T2]]
2870 ; MIPS32: or [[T4]],[[T4]],[[T7]]
2871 ; MIPS32: srl [[T9:.*]],a2,0x18
2872 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
2873 ; MIPS32: sll [[T9]],[[T9]],0x18
2874 ; MIPS32: sll [[T10]],[[T10]],0x18
2875 ; MIPS32: xor [[T9]],[[T9]],[[T10]]
2876 ; MIPS32: sltu [[T9]],zero,[[T9]]
2877 ; MIPS32: srl [[T9]],[[T9]],0x18
2878 ; MIPS32: sll [[T4]],[[T4]],0x8
2879 ; MIPS32: srl [[T4]],[[T4]],0x8
2880 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
2881 ; MIPS32: andi [[T4]],a3,0xff
2882 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
2883 ; MIPS32: sll [[T4]],[[T4]],0x18
2884 ; MIPS32: sll [[T7]],[[T7]],0x18
2885 ; MIPS32: xor [[T4]],[[T4]],[[T7]]
2886 ; MIPS32: sltu [[T4]],zero,[[T4]]
2887 ; MIPS32: andi [[T4]],[[T4]],0xff
2888 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
2889 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
2890 ; MIPS32: or [[T4]],[[T4]],[[T11]]
2891 ; MIPS32: srl [[T7]],a3,0x8
2892 ; MIPS32: andi [[T7]],[[T7]],0xff
2893 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
2894 ; MIPS32: andi [[T10]],[[T10]],0xff
2895 ; MIPS32: sll [[T7]],[[T7]],0x18
2896 ; MIPS32: sll [[T10]],[[T10]],0x18
2897 ; MIPS32: xor [[T7]],[[T7]],[[T10]]
2898 ; MIPS32: sltu [[T7]],zero,[[T7]]
2899 ; MIPS32: andi [[T7]],[[T7]],0xff
2900 ; MIPS32: sll [[T7]],[[T7]],0x8
2901 ; MIPS32: lui [[T10]],0xffff
2902 ; MIPS32: ori [[T10]],[[T10]],0xff
2903 ; MIPS32: and [[T4]],[[T4]],[[T10]]
2904 ; MIPS32: or [[T7]],[[T7]],[[T4]]
2905 ; MIPS32: srl [[T4]],a3,0x10
2906 ; MIPS32: andi [[T4]],[[T4]],0xff
2907 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
2908 ; MIPS32: andi [[T10]],[[T10]],0xff
2909 ; MIPS32: sll [[T4]],[[T4]],0x18
2910 ; MIPS32: sll [[T10]],[[T10]],0x18
2911 ; MIPS32: xor [[T4]],[[T4]],[[T10]]
2912 ; MIPS32: sltu [[T4]],zero,[[T4]]
2913 ; MIPS32: andi [[T4]],[[T4]],0xff
2914 ; MIPS32: sll [[T4]],[[T4]],0x10
2915 ; MIPS32: lui [[T10]],0xff00
2916 ; MIPS32: ori [[T10]],[[T10]],0xffff
2917 ; MIPS32: and [[T7]],[[T7]],[[T10]]
2918 ; MIPS32: or [[T4]],[[T4]],[[T7]]
2919 ; MIPS32: srl [[T12:.*]],a3,0x18
2920 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
2921 ; MIPS32: sll [[T12]],[[T12]],0x18
2922 ; MIPS32: sll [[T13]],[[T13]],0x18
2923 ; MIPS32: xor [[T12]],[[T12]],[[T13]]
2924 ; MIPS32: sltu [[T12]],zero,[[T12]]
2925 ; MIPS32: srl [[T12]],[[T12]],0x18
2926 ; MIPS32: sll [[T4]],[[T4]],0x8
2927 ; MIPS32: srl [[T4]],[[T4]],0x8
2928 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
354 } 2929 }
355 2930
356 define internal <16 x i1> @test_icmp_v16i8_sgt(<16 x i8> %a, <16 x i8> %b) { 2931 define internal <16 x i1> @test_icmp_v16i8_sgt(<16 x i8> %a, <16 x i8> %b) {
357 entry: 2932 entry:
358 %res = icmp sgt <16 x i8> %a, %b 2933 %res = icmp sgt <16 x i8> %a, %b
359 ret <16 x i1> %res 2934 ret <16 x i1> %res
360 ; CHECK-LABEL: test_icmp_v16i8_sgt 2935 ; CHECK-LABEL: test_icmp_v16i8_sgt
361 ; CHECK: pcmpgtb 2936 ; CHECK: pcmpgtb
2937
2938 ; MIPS32-LABEL: test_icmp_v16i8_sgt
2939 ; MIPS32: lw [[BV_E0:.*]],
2940 ; MIPS32: lw [[BV_E1:.*]],
2941 ; MIPS32: lw [[BV_E2:.*]],
2942 ; MIPS32: lw [[BV_E3:.*]],
2943 ; MIPS32: move [[TV_E0:.*]],zero
2944 ; MIPS32: move [[TV_E1:.*]],zero
2945 ; MIPS32: move [[TV_E2:.*]],zero
2946 ; MIPS32: move [[TV_E3:.*]],zero
2947 ; MIPS32: andi [[T0:.*]],a0,0xff
2948 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
2949 ; MIPS32: sll [[T0]],[[T0]],0x18
2950 ; MIPS32: sll [[T1]],[[T1]],0x18
2951 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
2952 ; MIPS32: andi [[T1]],[[T1]],0xff
2953 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
2954 ; MIPS32: sll [[T2]],[[TV_E0]],0x8
2955 ; MIPS32: or [[T1]],[[T1]],[[T2]]
2956 ; MIPS32: srl [[T2]],a0,0x8
2957 ; MIPS32: andi [[T2]],[[T2]],0xff
2958 ; MIPS32: srl [[T0]],[[BV_E0]],0x8
2959 ; MIPS32: andi [[T0]],[[T0]],0xff
2960 ; MIPS32: sll [[T2]],[[T2]],0x18
2961 ; MIPS32: sll [[T0]],[[T0]],0x18
2962 ; MIPS32: slt [[T0]],[[T0]],[[T2]]
2963 ; MIPS32: andi [[T0]],[[T0]],0xff
2964 ; MIPS32: sll [[T0]],[[T0]],0x8
2965 ; MIPS32: lui [[T2]],0xffff
2966 ; MIPS32: ori [[T2]],[[T2]],0xff
2967 ; MIPS32: and [[T1]],[[T1]],[[T2]]
2968 ; MIPS32: or [[T0]],[[T0]],[[T1]]
2969 ; MIPS32: srl [[T2]],a0,0x10
2970 ; MIPS32: andi [[T2]],[[T2]],0xff
2971 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
2972 ; MIPS32: andi [[T1]],[[T1]],0xff
2973 ; MIPS32: sll [[T2]],[[T2]],0x18
2974 ; MIPS32: sll [[T1]],[[T1]],0x18
2975 ; MIPS32: slt [[T1]],[[T1]],[[T2]]
2976 ; MIPS32: andi [[T1]],[[T1]],0xff
2977 ; MIPS32: sll [[T1]],[[T1]],0x10
2978 ; MIPS32: lui [[T2]],0xff00
2979 ; MIPS32: ori [[T2]],[[T2]],0xffff
2980 ; MIPS32: and [[T0]],[[T0]],[[T2]]
2981 ; MIPS32: or [[T1]],[[T1]],[[T0]]
2982 ; MIPS32: srl [[T3:.*]],a0,0x18
2983 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
2984 ; MIPS32: sll [[T3]],[[T3]],0x18
2985 ; MIPS32: sll [[T4]],[[T4]],0x18
2986 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
2987 ; MIPS32: srl [[T4]],[[T4]],0x18
2988 ; MIPS32: sll [[T1]],[[T1]],0x8
2989 ; MIPS32: srl [[T1]],[[T1]],0x8
2990 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
2991 ; MIPS32: andi [[T3]],a1,0xff
2992 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
2993 ; MIPS32: sll [[T3]],[[T3]],0x18
2994 ; MIPS32: sll [[T2]],[[T2]],0x18
2995 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
2996 ; MIPS32: andi [[T2]],[[T2]],0xff
2997 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
2998 ; MIPS32: sll [[T5]],[[TV_E1]],0x8
2999 ; MIPS32: or [[T2]],[[T2]],[[T5]]
3000 ; MIPS32: srl [[T3]],a1,0x8
3001 ; MIPS32: andi [[T3]],[[T3]],0xff
3002 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
3003 ; MIPS32: andi [[T5]],[[T5]],0xff
3004 ; MIPS32: sll [[T3]],[[T3]],0x18
3005 ; MIPS32: sll [[T5]],[[T5]],0x18
3006 ; MIPS32: slt [[T5]],[[T5]],[[T3]]
3007 ; MIPS32: andi [[T5]],[[T5]],0xff
3008 ; MIPS32: sll [[T5]],[[T5]],0x8
3009 ; MIPS32: lui [[T3]],0xffff
3010 ; MIPS32: ori [[T3]],[[T3]],0xff
3011 ; MIPS32: and [[T2]],[[T2]],[[T3]]
3012 ; MIPS32: or [[T5]],[[T5]],[[T2]]
3013 ; MIPS32: srl [[T3]],a1,0x10
3014 ; MIPS32: andi [[T3]],[[T3]],0xff
3015 ; MIPS32: srl [[T2]],[[BV_E1]],0x10
3016 ; MIPS32: andi [[T2]],[[T2]],0xff
3017 ; MIPS32: sll [[T3]],[[T3]],0x18
3018 ; MIPS32: sll [[T2]],[[T2]],0x18
3019 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
3020 ; MIPS32: andi [[T2]],[[T2]],0xff
3021 ; MIPS32: sll [[T2]],[[T2]],0x10
3022 ; MIPS32: lui [[T3]],0xff00
3023 ; MIPS32: ori [[T3]],[[T3]],0xffff
3024 ; MIPS32: and [[T5]],[[T5]],[[T3]]
3025 ; MIPS32: or [[T2]],[[T2]],[[T5]]
3026 ; MIPS32: srl [[T6:.*]],a1,0x18
3027 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
3028 ; MIPS32: sll [[T6]],[[T6]],0x18
3029 ; MIPS32: sll [[T7]],[[T7]],0x18
3030 ; MIPS32: slt [[T7]],[[T7]],[[T6]]
3031 ; MIPS32: srl [[T7]],[[T7]],0x18
3032 ; MIPS32: sll [[T2]],[[T2]],0x8
3033 ; MIPS32: srl [[T2]],[[T2]],0x8
3034 ; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
3035 ; MIPS32: andi [[T3]],a2,0xff
3036 ; MIPS32: andi [[T6]],[[BV_E2]],0xff
3037 ; MIPS32: sll [[T3]],[[T3]],0x18
3038 ; MIPS32: sll [[T6]],[[T6]],0x18
3039 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
3040 ; MIPS32: andi [[T6]],[[T6]],0xff
3041 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
3042 ; MIPS32: sll [[T8]],[[TV_E2]],0x8
3043 ; MIPS32: or [[T6]],[[T6]],[[T8]]
3044 ; MIPS32: srl [[T3]],a2,0x8
3045 ; MIPS32: andi [[T3]],[[T3]],0xff
3046 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
3047 ; MIPS32: andi [[T2]],[[T2]],0xff
3048 ; MIPS32: sll [[T3]],[[T3]],0x18
3049 ; MIPS32: sll [[T2]],[[T2]],0x18
3050 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
3051 ; MIPS32: andi [[T2]],[[T2]],0xff
3052 ; MIPS32: sll [[T2]],[[T2]],0x8
3053 ; MIPS32: lui [[T3]],0xffff
3054 ; MIPS32: ori [[T3]],[[T3]],0xff
3055 ; MIPS32: and [[T6]],[[T6]],[[T3]]
3056 ; MIPS32: or [[T2]],[[T2]],[[T6]]
3057 ; MIPS32: srl [[T3]],a2,0x10
3058 ; MIPS32: andi [[T3]],[[T3]],0xff
3059 ; MIPS32: srl [[T6]],[[BV_E2]],0x10
3060 ; MIPS32: andi [[T6]],[[T6]],0xff
3061 ; MIPS32: sll [[T3]],[[T3]],0x18
3062 ; MIPS32: sll [[T6]],[[T6]],0x18
3063 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
3064 ; MIPS32: andi [[T6]],[[T6]],0xff
3065 ; MIPS32: sll [[T6]],[[T6]],0x10
3066 ; MIPS32: lui [[T3]],0xff00
3067 ; MIPS32: ori [[T3]],[[T3]],0xffff
3068 ; MIPS32: and [[T2]],[[T2]],[[T3]]
3069 ; MIPS32: or [[T6]],[[T6]],[[T2]]
3070 ; MIPS32: srl [[T9:.*]],a2,0x18
3071 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
3072 ; MIPS32: sll [[T9]],[[T9]],0x18
3073 ; MIPS32: sll [[T10]],[[T10]],0x18
3074 ; MIPS32: slt [[T10]],[[T10]],[[T9]]
3075 ; MIPS32: srl [[T10]],[[T10]],0x18
3076 ; MIPS32: sll [[T6]],[[T6]],0x8
3077 ; MIPS32: srl [[T6]],[[T6]],0x8
3078 ; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
3079 ; MIPS32: andi [[T3]],a3,0xff
3080 ; MIPS32: andi [[T6]],[[BV_E3]],0xff
3081 ; MIPS32: sll [[T3]],[[T3]],0x18
3082 ; MIPS32: sll [[T6]],[[T6]],0x18
3083 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
3084 ; MIPS32: andi [[T6]],[[T6]],0xff
3085 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
3086 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
3087 ; MIPS32: or [[T6]],[[T6]],[[T11]]
3088 ; MIPS32: srl [[T3]],a3,0x8
3089 ; MIPS32: andi [[T3]],[[T3]],0xff
3090 ; MIPS32: srl [[T9]],[[BV_E3]],0x8
3091 ; MIPS32: andi [[T9]],[[T9]],0xff
3092 ; MIPS32: sll [[T3]],[[T3]],0x18
3093 ; MIPS32: sll [[T9]],[[T9]],0x18
3094 ; MIPS32: slt [[T9]],[[T9]],[[T3]]
3095 ; MIPS32: andi [[T9]],[[T9]],0xff
3096 ; MIPS32: sll [[T9]],[[T9]],0x8
3097 ; MIPS32: lui [[T3]],0xffff
3098 ; MIPS32: ori [[T3]],[[T3]],0xff
3099 ; MIPS32: and [[T6]],[[T6]],[[T3]]
3100 ; MIPS32: or [[T9]],[[T9]],[[T6]]
3101 ; MIPS32: srl [[T3]],a3,0x10
3102 ; MIPS32: andi [[T3]],[[T3]],0xff
3103 ; MIPS32: srl [[T6]],[[BV_E3]],0x10
3104 ; MIPS32: andi [[T6]],[[T6]],0xff
3105 ; MIPS32: sll [[T3]],[[T3]],0x18
3106 ; MIPS32: sll [[T6]],[[T6]],0x18
3107 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
3108 ; MIPS32: andi [[T6]],[[T6]],0xff
3109 ; MIPS32: sll [[T6]],[[T6]],0x10
3110 ; MIPS32: lui [[T3]],0xff00
3111 ; MIPS32: ori [[T3]],[[T3]],0xffff
3112 ; MIPS32: and [[T9]],[[T9]],[[T3]]
3113 ; MIPS32: or [[T6]],[[T6]],[[T9]]
3114 ; MIPS32: srl [[T12:.*]],a3,0x18
3115 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
3116 ; MIPS32: sll [[T12]],[[T12]],0x18
3117 ; MIPS32: sll [[T13]],[[T13]],0x18
3118 ; MIPS32: slt [[T13]],[[T13]],[[T12]]
3119 ; MIPS32: srl [[T13]],[[T13]],0x18
3120 ; MIPS32: sll [[T6]],[[T6]],0x8
3121 ; MIPS32: srl [[T6]],[[T6]],0x8
3122 ; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
362 } 3123 }
363 3124
364 define internal <16 x i1> @test_icmp_v16i8_sle(<16 x i8> %a, <16 x i8> %b) { 3125 define internal <16 x i1> @test_icmp_v16i8_sle(<16 x i8> %a, <16 x i8> %b) {
365 entry: 3126 entry:
366 %res = icmp sle <16 x i8> %a, %b 3127 %res = icmp sle <16 x i8> %a, %b
367 ret <16 x i1> %res 3128 ret <16 x i1> %res
368 ; CHECK-LABEL: test_icmp_v16i8_sle 3129 ; CHECK-LABEL: test_icmp_v16i8_sle
369 ; CHECK: pcmpgtb 3130 ; CHECK: pcmpgtb
370 ; CHECK: pxor 3131 ; CHECK: pxor
3132
3133 ; MIPS32-LABEL: test_icmp_v16i8_sle
3134 ; MIPS32: lw [[BV_E0:.*]],
3135 ; MIPS32: lw [[BV_E1:.*]],
3136 ; MIPS32: lw [[BV_E2:.*]],
3137 ; MIPS32: lw [[BV_E3:.*]],
3138 ; MIPS32: move [[TV_E0:.*]],zero
3139 ; MIPS32: move [[TV_E1:.*]],zero
3140 ; MIPS32: move [[TV_E2:.*]],zero
3141 ; MIPS32: move [[TV_E3:.*]],zero
3142 ; MIPS32: andi [[T0:.*]],a0,0xff
3143 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
3144 ; MIPS32: sll [[T0]],[[T0]],0x18
3145 ; MIPS32: sll [[T1]],[[T1]],0x18
3146 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
3147 ; MIPS32: xori [[T1]],[[T1]],0x1
3148 ; MIPS32: andi [[T1]],[[T1]],0xff
3149 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
3150 ; MIPS32: sll [[T2]],[[TV_E0]],0x8
3151 ; MIPS32: or [[T1]],[[T1]],[[T2]]
3152 ; MIPS32: srl [[T2]],a0,0x8
3153 ; MIPS32: andi [[T2]],[[T2]],0xff
3154 ; MIPS32: srl [[T0]],[[BV_E0]],0x8
3155 ; MIPS32: andi [[T0]],[[T0]],0xff
3156 ; MIPS32: sll [[T2]],[[T2]],0x18
3157 ; MIPS32: sll [[T0]],[[T0]],0x18
3158 ; MIPS32: slt [[T0]],[[T0]],[[T2]]
3159 ; MIPS32: xori [[T0]],[[T0]],0x1
3160 ; MIPS32: andi [[T0]],[[T0]],0xff
3161 ; MIPS32: sll [[T0]],[[T0]],0x8
3162 ; MIPS32: lui [[T2]],0xffff
3163 ; MIPS32: ori [[T2]],[[T2]],0xff
3164 ; MIPS32: and [[T1]],[[T1]],[[T2]]
3165 ; MIPS32: or [[T0]],[[T0]],[[T1]]
3166 ; MIPS32: srl [[T2]],a0,0x10
3167 ; MIPS32: andi [[T2]],[[T2]],0xff
3168 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
3169 ; MIPS32: andi [[T1]],[[T1]],0xff
3170 ; MIPS32: sll [[T2]],[[T2]],0x18
3171 ; MIPS32: sll [[T1]],[[T1]],0x18
3172 ; MIPS32: slt [[T1]],[[T1]],[[T2]]
3173 ; MIPS32: xori [[T1]],[[T1]],0x1
3174 ; MIPS32: andi [[T1]],[[T1]],0xff
3175 ; MIPS32: sll [[T1]],[[T1]],0x10
3176 ; MIPS32: lui [[T2]],0xff00
3177 ; MIPS32: ori [[T2]],[[T2]],0xffff
3178 ; MIPS32: and [[T0]],[[T0]],[[T2]]
3179 ; MIPS32: or [[T1]],[[T1]],[[T0]]
3180 ; MIPS32: srl [[T3:.*]],a0,0x18
3181 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
3182 ; MIPS32: sll [[T3]],[[T3]],0x18
3183 ; MIPS32: sll [[T4]],[[T4]],0x18
3184 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
3185 ; MIPS32: xori [[T4]],[[T4]],0x1
3186 ; MIPS32: srl [[T4]],[[T4]],0x18
3187 ; MIPS32: sll [[T1]],[[T1]],0x8
3188 ; MIPS32: srl [[T1]],[[T1]],0x8
3189 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
3190 ; MIPS32: andi [[T3]],a1,0xff
3191 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
3192 ; MIPS32: sll [[T3]],[[T3]],0x18
3193 ; MIPS32: sll [[T2]],[[T2]],0x18
3194 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
3195 ; MIPS32: xori [[T2]],[[T2]],0x1
3196 ; MIPS32: andi [[T2]],[[T2]],0xff
3197 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
3198 ; MIPS32: sll [[T5]],[[TV_E1]],0x8
3199 ; MIPS32: or [[T2]],[[T2]],[[T5]]
3200 ; MIPS32: srl [[T3]],a1,0x8
3201 ; MIPS32: andi [[T3]],[[T3]],0xff
3202 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
3203 ; MIPS32: andi [[T5]],[[T5]],0xff
3204 ; MIPS32: sll [[T3]],[[T3]],0x18
3205 ; MIPS32: sll [[T5]],[[T5]],0x18
3206 ; MIPS32: slt [[T5]],[[T5]],[[T3]]
3207 ; MIPS32: xori [[T5]],[[T5]],0x1
3208 ; MIPS32: andi [[T5]],[[T5]],0xff
3209 ; MIPS32: sll [[T5]],[[T5]],0x8
3210 ; MIPS32: lui [[T3]],0xffff
3211 ; MIPS32: ori [[T3]],[[T3]],0xff
3212 ; MIPS32: and [[T2]],[[T2]],[[T3]]
3213 ; MIPS32: or [[T5]],[[T5]],[[T2]]
3214 ; MIPS32: srl [[T3]],a1,0x10
3215 ; MIPS32: andi [[T3]],[[T3]],0xff
3216 ; MIPS32: srl [[T2]],[[BV_E1]],0x10
3217 ; MIPS32: andi [[T2]],[[T2]],0xff
3218 ; MIPS32: sll [[T3]],[[T3]],0x18
3219 ; MIPS32: sll [[T2]],[[T2]],0x18
3220 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
3221 ; MIPS32: xori [[T2]],[[T2]],0x1
3222 ; MIPS32: andi [[T2]],[[T2]],0xff
3223 ; MIPS32: sll [[T2]],[[T2]],0x10
3224 ; MIPS32: lui [[T3]],0xff00
3225 ; MIPS32: ori [[T3]],[[T3]],0xffff
3226 ; MIPS32: and [[T5]],[[T5]],[[T3]]
3227 ; MIPS32: or [[T2]],[[T2]],[[T5]]
3228 ; MIPS32: srl [[T6:.*]],a1,0x18
3229 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
3230 ; MIPS32: sll [[T6]],[[T6]],0x18
3231 ; MIPS32: sll [[T7]],[[T7]],0x18
3232 ; MIPS32: slt [[T7]],[[T7]],[[T6]]
3233 ; MIPS32: xori [[T7]],[[T7]],0x1
3234 ; MIPS32: srl [[T7]],[[T7]],0x18
3235 ; MIPS32: sll [[T2]],[[T2]],0x8
3236 ; MIPS32: srl [[T2]],[[T2]],0x8
3237 ; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
3238 ; MIPS32: andi [[T3]],a2,0xff
3239 ; MIPS32: andi [[T6]],[[BV_E2]],0xff
3240 ; MIPS32: sll [[T3]],[[T3]],0x18
3241 ; MIPS32: sll [[T6]],[[T6]],0x18
3242 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
3243 ; MIPS32: xori [[T6]],[[T6]],0x1
3244 ; MIPS32: andi [[T6]],[[T6]],0xff
3245 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
3246 ; MIPS32: sll [[T8]],[[TV_E2]],0x8
3247 ; MIPS32: or [[T6]],[[T6]],[[T8]]
3248 ; MIPS32: srl [[T3]],a2,0x8
3249 ; MIPS32: andi [[T3]],[[T3]],0xff
3250 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
3251 ; MIPS32: andi [[T2]],[[T2]],0xff
3252 ; MIPS32: sll [[T3]],[[T3]],0x18
3253 ; MIPS32: sll [[T2]],[[T2]],0x18
3254 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
3255 ; MIPS32: xori [[T2]],[[T2]],0x1
3256 ; MIPS32: andi [[T2]],[[T2]],0xff
3257 ; MIPS32: sll [[T2]],[[T2]],0x8
3258 ; MIPS32: lui [[T3]],0xffff
3259 ; MIPS32: ori [[T3]],[[T3]],0xff
3260 ; MIPS32: and [[T6]],[[T6]],[[T3]]
3261 ; MIPS32: or [[T2]],[[T2]],[[T6]]
3262 ; MIPS32: srl [[T3]],a2,0x10
3263 ; MIPS32: andi [[T3]],[[T3]],0xff
3264 ; MIPS32: srl [[T6]],[[BV_E2]],0x10
3265 ; MIPS32: andi [[T6]],[[T6]],0xff
3266 ; MIPS32: sll [[T3]],[[T3]],0x18
3267 ; MIPS32: sll [[T6]],[[T6]],0x18
3268 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
3269 ; MIPS32: xori [[T6]],[[T6]],0x1
3270 ; MIPS32: andi [[T6]],[[T6]],0xff
3271 ; MIPS32: sll [[T6]],[[T6]],0x10
3272 ; MIPS32: lui [[T3]],0xff00
3273 ; MIPS32: ori [[T3]],[[T3]],0xffff
3274 ; MIPS32: and [[T2]],[[T2]],[[T3]]
3275 ; MIPS32: or [[T6]],[[T6]],[[T2]]
3276 ; MIPS32: srl [[T9:.*]],a2,0x18
3277 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
3278 ; MIPS32: sll [[T9]],[[T9]],0x18
3279 ; MIPS32: sll [[T10]],[[T10]],0x18
3280 ; MIPS32: slt [[T10]],[[T10]],[[T9]]
3281 ; MIPS32: xori [[T10]],[[T10]],0x1
3282 ; MIPS32: srl [[T10]],[[T10]],0x18
3283 ; MIPS32: sll [[T6]],[[T6]],0x8
3284 ; MIPS32: srl [[T6]],[[T6]],0x8
3285 ; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
3286 ; MIPS32: andi [[T3]],a3,0xff
3287 ; MIPS32: andi [[T6]],[[BV_E3]],0xff
3288 ; MIPS32: sll [[T3]],[[T3]],0x18
3289 ; MIPS32: sll [[T6]],[[T6]],0x18
3290 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
3291 ; MIPS32: xori [[T6]],[[T6]],0x1
3292 ; MIPS32: andi [[T6]],[[T6]],0xff
3293 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
3294 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
3295 ; MIPS32: or [[T6]],[[T6]],[[T11]]
3296 ; MIPS32: srl [[T3]],a3,0x8
3297 ; MIPS32: andi [[T3]],[[T3]],0xff
3298 ; MIPS32: srl [[T9]],[[BV_E3]],0x8
3299 ; MIPS32: andi [[T9]],[[T9]],0xff
3300 ; MIPS32: sll [[T3]],[[T3]],0x18
3301 ; MIPS32: sll [[T9]],[[T9]],0x18
3302 ; MIPS32: slt [[T9]],[[T9]],[[T3]]
3303 ; MIPS32: xori [[T9]],[[T9]],0x1
3304 ; MIPS32: andi [[T9]],[[T9]],0xff
3305 ; MIPS32: sll [[T9]],[[T9]],0x8
3306 ; MIPS32: lui [[T3]],0xffff
3307 ; MIPS32: ori [[T3]],[[T3]],0xff
3308 ; MIPS32: and [[T6]],[[T6]],[[T3]]
3309 ; MIPS32: or [[T9]],[[T9]],[[T6]]
3310 ; MIPS32: srl [[T3]],a3,0x10
3311 ; MIPS32: andi [[T3]],[[T3]],0xff
3312 ; MIPS32: srl [[T6]],[[BV_E3]],0x10
3313 ; MIPS32: andi [[T6]],[[T6]],0xff
3314 ; MIPS32: sll [[T3]],[[T3]],0x18
3315 ; MIPS32: sll [[T6]],[[T6]],0x18
3316 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
3317 ; MIPS32: xori [[T6]],[[T6]],0x1
3318 ; MIPS32: andi [[T6]],[[T6]],0xff
3319 ; MIPS32: sll [[T6]],[[T6]],0x10
3320 ; MIPS32: lui [[T3]],0xff00
3321 ; MIPS32: ori [[T3]],[[T3]],0xffff
3322 ; MIPS32: and [[T9]],[[T9]],[[T3]]
3323 ; MIPS32: or [[T6]],[[T6]],[[T9]]
3324 ; MIPS32: srl [[T12:.*]],a3,0x18
3325 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
3326 ; MIPS32: sll [[T12]],[[T12]],0x18
3327 ; MIPS32: sll [[T13]],[[T13]],0x18
3328 ; MIPS32: slt [[T13]],[[T13]],[[T12]]
3329 ; MIPS32: xori [[T13]],[[T13]],0x1
3330 ; MIPS32: srl [[T13]],[[T13]],0x18
3331 ; MIPS32: sll [[T6]],[[T6]],0x8
3332 ; MIPS32: srl [[T6]],[[T6]],0x8
3333 ; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
371 } 3334 }
372 3335
373 define internal <16 x i1> @test_icmp_v16i8_slt(<16 x i8> %a, <16 x i8> %b) { 3336 define internal <16 x i1> @test_icmp_v16i8_slt(<16 x i8> %a, <16 x i8> %b) {
374 entry: 3337 entry:
375 %res = icmp slt <16 x i8> %a, %b 3338 %res = icmp slt <16 x i8> %a, %b
376 ret <16 x i1> %res 3339 ret <16 x i1> %res
377 ; CHECK-LABEL: test_icmp_v16i8_slt 3340 ; CHECK-LABEL: test_icmp_v16i8_slt
378 ; CHECK: pcmpgtb 3341 ; CHECK: pcmpgtb
3342
3343 ; MIPS32-LABEL: test_icmp_v16i8_slt
3344 ; MIPS32: lw [[BV_E0:.*]],
3345 ; MIPS32: lw [[BV_E1:.*]],
3346 ; MIPS32: lw [[BV_E2:.*]],
3347 ; MIPS32: lw [[BV_E3:.*]],
3348 ; MIPS32: move [[TV_E0:.*]],zero
3349 ; MIPS32: move [[TV_E1:.*]],zero
3350 ; MIPS32: move [[TV_E2:.*]],zero
3351 ; MIPS32: move [[TV_E3:.*]],zero
3352 ; MIPS32: andi [[T0:.*]],a0,0xff
3353 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
3354 ; MIPS32: sll [[T0]],[[T0]],0x18
3355 ; MIPS32: sll [[T1]],[[T1]],0x18
3356 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
3357 ; MIPS32: andi [[T0]],[[T0]],0xff
3358 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
3359 ; MIPS32: sll [[T2]],[[TV_E0]],0x8
3360 ; MIPS32: or [[T0]],[[T0]],[[T2]]
3361 ; MIPS32: srl [[T2]],a0,0x8
3362 ; MIPS32: andi [[T2]],[[T2]],0xff
3363 ; MIPS32: srl [[T1]],[[BV_E0]],0x8
3364 ; MIPS32: andi [[T1]],[[T1]],0xff
3365 ; MIPS32: sll [[T2]],[[T2]],0x18
3366 ; MIPS32: sll [[T1]],[[T1]],0x18
3367 ; MIPS32: slt [[T2]],[[T2]],[[T1]]
3368 ; MIPS32: andi [[T2]],[[T2]],0xff
3369 ; MIPS32: sll [[T2]],[[T2]],0x8
3370 ; MIPS32: lui [[T1]],0xffff
3371 ; MIPS32: ori [[T1]],[[T1]],0xff
3372 ; MIPS32: and [[T0]],[[T0]],[[T1]]
3373 ; MIPS32: or [[T2]],[[T2]],[[T0]]
3374 ; MIPS32: srl [[T0]],a0,0x10
3375 ; MIPS32: andi [[T0]],[[T0]],0xff
3376 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
3377 ; MIPS32: andi [[T1]],[[T1]],0xff
3378 ; MIPS32: sll [[T0]],[[T0]],0x18
3379 ; MIPS32: sll [[T1]],[[T1]],0x18
3380 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
3381 ; MIPS32: andi [[T0]],[[T0]],0xff
3382 ; MIPS32: sll [[T0]],[[T0]],0x10
3383 ; MIPS32: lui [[T1]],0xff00
3384 ; MIPS32: ori [[T1]],[[T1]],0xffff
3385 ; MIPS32: and [[T2]],[[T2]],[[T1]]
3386 ; MIPS32: or [[T0]],[[T0]],[[T2]]
3387 ; MIPS32: srl [[T3:.*]],a0,0x18
3388 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
3389 ; MIPS32: sll [[T3]],[[T3]],0x18
3390 ; MIPS32: sll [[T4]],[[T4]],0x18
3391 ; MIPS32: slt [[T3]],[[T3]],[[T4]]
3392 ; MIPS32: srl [[T3]],[[T3]],0x18
3393 ; MIPS32: sll [[T0]],[[T0]],0x8
3394 ; MIPS32: srl [[T0]],[[T0]],0x8
3395 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
3396 ; MIPS32: andi [[T4]],a1,0xff
3397 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
3398 ; MIPS32: sll [[T4]],[[T4]],0x18
3399 ; MIPS32: sll [[T2]],[[T2]],0x18
3400 ; MIPS32: slt [[T4]],[[T4]],[[T2]]
3401 ; MIPS32: andi [[T4]],[[T4]],0xff
3402 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
3403 ; MIPS32: sll [[T5]],[[TV_E1]],0x8
3404 ; MIPS32: or [[T4]],[[T4]],[[T5]]
3405 ; MIPS32: srl [[T2]],a1,0x8
3406 ; MIPS32: andi [[T2]],[[T2]],0xff
3407 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
3408 ; MIPS32: andi [[T5]],[[T5]],0xff
3409 ; MIPS32: sll [[T2]],[[T2]],0x18
3410 ; MIPS32: sll [[T5]],[[T5]],0x18
3411 ; MIPS32: slt [[T2]],[[T2]],[[T5]]
3412 ; MIPS32: andi [[T2]],[[T2]],0xff
3413 ; MIPS32: sll [[T2]],[[T2]],0x8
3414 ; MIPS32: lui [[T5]],0xffff
3415 ; MIPS32: ori [[T5]],[[T5]],0xff
3416 ; MIPS32: and [[T4]],[[T4]],[[T5]]
3417 ; MIPS32: or [[T2]],[[T2]],[[T4]]
3418 ; MIPS32: srl [[T4]],a1,0x10
3419 ; MIPS32: andi [[T4]],[[T4]],0xff
3420 ; MIPS32: srl [[T5]],[[BV_E1]],0x10
3421 ; MIPS32: andi [[T5]],[[T5]],0xff
3422 ; MIPS32: sll [[T4]],[[T4]],0x18
3423 ; MIPS32: sll [[T5]],[[T5]],0x18
3424 ; MIPS32: slt [[T4]],[[T4]],[[T5]]
3425 ; MIPS32: andi [[T4]],[[T4]],0xff
3426 ; MIPS32: sll [[T4]],[[T4]],0x10
3427 ; MIPS32: lui [[T5]],0xff00
3428 ; MIPS32: ori [[T5]],[[T5]],0xffff
3429 ; MIPS32: and [[T2]],[[T2]],[[T5]]
3430 ; MIPS32: or [[T4]],[[T4]],[[T2]]
3431 ; MIPS32: srl [[T6:.*]],a1,0x18
3432 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
3433 ; MIPS32: sll [[T6]],[[T6]],0x18
3434 ; MIPS32: sll [[T7]],[[T7]],0x18
3435 ; MIPS32: slt [[T6]],[[T6]],[[T7]]
3436 ; MIPS32: srl [[T6]],[[T6]],0x18
3437 ; MIPS32: sll [[T4]],[[T4]],0x8
3438 ; MIPS32: srl [[T4]],[[T4]],0x8
3439 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
3440 ; MIPS32: andi [[T4]],a2,0xff
3441 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
3442 ; MIPS32: sll [[T4]],[[T4]],0x18
3443 ; MIPS32: sll [[T7]],[[T7]],0x18
3444 ; MIPS32: slt [[T4]],[[T4]],[[T7]]
3445 ; MIPS32: andi [[T4]],[[T4]],0xff
3446 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
3447 ; MIPS32: sll [[T8]],[[TV_E2]],0x8
3448 ; MIPS32: or [[T4]],[[T4]],[[T8]]
3449 ; MIPS32: srl [[T7]],a2,0x8
3450 ; MIPS32: andi [[T7]],[[T7]],0xff
3451 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
3452 ; MIPS32: andi [[T2]],[[T2]],0xff
3453 ; MIPS32: sll [[T7]],[[T7]],0x18
3454 ; MIPS32: sll [[T2]],[[T2]],0x18
3455 ; MIPS32: slt [[T7]],[[T7]],[[T2]]
3456 ; MIPS32: andi [[T7]],[[T7]],0xff
3457 ; MIPS32: sll [[T7]],[[T7]],0x8
3458 ; MIPS32: lui [[T2]],0xffff
3459 ; MIPS32: ori [[T2]],[[T2]],0xff
3460 ; MIPS32: and [[T4]],[[T4]],[[T2]]
3461 ; MIPS32: or [[T7]],[[T7]],[[T4]]
3462 ; MIPS32: srl [[T4]],a2,0x10
3463 ; MIPS32: andi [[T4]],[[T4]],0xff
3464 ; MIPS32: srl [[T2]],[[BV_E2]],0x10
3465 ; MIPS32: andi [[T2]],[[T2]],0xff
3466 ; MIPS32: sll [[T4]],[[T4]],0x18
3467 ; MIPS32: sll [[T2]],[[T2]],0x18
3468 ; MIPS32: slt [[T4]],[[T4]],[[T2]]
3469 ; MIPS32: andi [[T4]],[[T4]],0xff
3470 ; MIPS32: sll [[T4]],[[T4]],0x10
3471 ; MIPS32: lui [[T2]],0xff00
3472 ; MIPS32: ori [[T2]],[[T2]],0xffff
3473 ; MIPS32: and [[T7]],[[T7]],[[T2]]
3474 ; MIPS32: or [[T4]],[[T4]],[[T7]]
3475 ; MIPS32: srl [[T9:.*]],a2,0x18
3476 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
3477 ; MIPS32: sll [[T9]],[[T9]],0x18
3478 ; MIPS32: sll [[T10]],[[T10]],0x18
3479 ; MIPS32: slt [[T9]],[[T9]],[[T10]]
3480 ; MIPS32: srl [[T9]],[[T9]],0x18
3481 ; MIPS32: sll [[T4]],[[T4]],0x8
3482 ; MIPS32: srl [[T4]],[[T4]],0x8
3483 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
3484 ; MIPS32: andi [[T4]],a3,0xff
3485 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
3486 ; MIPS32: sll [[T4]],[[T4]],0x18
3487 ; MIPS32: sll [[T7]],[[T7]],0x18
3488 ; MIPS32: slt [[T4]],[[T4]],[[T7]]
3489 ; MIPS32: andi [[T4]],[[T4]],0xff
3490 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
3491 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
3492 ; MIPS32: or [[T4]],[[T4]],[[T11]]
3493 ; MIPS32: srl [[T7]],a3,0x8
3494 ; MIPS32: andi [[T7]],[[T7]],0xff
3495 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
3496 ; MIPS32: andi [[T10]],[[T10]],0xff
3497 ; MIPS32: sll [[T7]],[[T7]],0x18
3498 ; MIPS32: sll [[T10]],[[T10]],0x18
3499 ; MIPS32: slt [[T7]],[[T7]],[[T10]]
3500 ; MIPS32: andi [[T7]],[[T7]],0xff
3501 ; MIPS32: sll [[T7]],[[T7]],0x8
3502 ; MIPS32: lui [[T10]],0xffff
3503 ; MIPS32: ori [[T10]],[[T10]],0xff
3504 ; MIPS32: and [[T4]],[[T4]],[[T10]]
3505 ; MIPS32: or [[T7]],[[T7]],[[T4]]
3506 ; MIPS32: srl [[T4]],a3,0x10
3507 ; MIPS32: andi [[T4]],[[T4]],0xff
3508 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
3509 ; MIPS32: andi [[T10]],[[T10]],0xff
3510 ; MIPS32: sll [[T4]],[[T4]],0x18
3511 ; MIPS32: sll [[T10]],[[T10]],0x18
3512 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
3513 ; MIPS32: andi [[T4]],[[T4]],0xff
3514 ; MIPS32: sll [[T4]],[[T4]],0x10
3515 ; MIPS32: lui [[T10]],0xff00
3516 ; MIPS32: ori [[T10]],[[T10]],0xffff
3517 ; MIPS32: and [[T7]],[[T7]],[[T10]]
3518 ; MIPS32: or [[T4]],[[T4]],[[T7]]
3519 ; MIPS32: srl [[T12:.*]],a3,0x18
3520 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
3521 ; MIPS32: sll [[T12]],[[T12]],0x18
3522 ; MIPS32: sll [[T13]],[[T13]],0x18
3523 ; MIPS32: slt [[T12]],[[T12]],[[T13]]
3524 ; MIPS32: srl [[T12]],[[T12]],0x18
3525 ; MIPS32: sll [[T4]],[[T4]],0x8
3526 ; MIPS32: srl [[T4]],[[T4]],0x8
3527 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
379 } 3528 }
380 3529
381 define internal <16 x i1> @test_icmp_v16i8_uge(<16 x i8> %a, <16 x i8> %b) { 3530 define internal <16 x i1> @test_icmp_v16i8_uge(<16 x i8> %a, <16 x i8> %b) {
382 entry: 3531 entry:
383 %res = icmp uge <16 x i8> %a, %b 3532 %res = icmp uge <16 x i8> %a, %b
384 ret <16 x i1> %res 3533 ret <16 x i1> %res
385 ; CHECK-LABEL: test_icmp_v16i8_uge 3534 ; CHECK-LABEL: test_icmp_v16i8_uge
386 ; CHECK: pxor 3535 ; CHECK: pxor
387 ; CHECK: pcmpgtb 3536 ; CHECK: pcmpgtb
388 ; CHECK: pxor 3537 ; CHECK: pxor
3538
3539 ; MIPS32-LABEL: test_icmp_v16i8_uge
3540 ; MIPS32: lw [[BV_E0:.*]],
3541 ; MIPS32: lw [[BV_E1:.*]],
3542 ; MIPS32: lw [[BV_E2:.*]],
3543 ; MIPS32: lw [[BV_E3:.*]],
3544 ; MIPS32: move [[TV_E0:.*]],zero
3545 ; MIPS32: move [[TV_E1:.*]],zero
3546 ; MIPS32: move [[TV_E2:.*]],zero
3547 ; MIPS32: move [[TV_E3:.*]],zero
3548 ; MIPS32: andi [[T0:.*]],a0,0xff
3549 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
3550 ; MIPS32: sll [[T0]],[[T0]],0x18
3551 ; MIPS32: sll [[T1]],[[T1]],0x18
3552 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
3553 ; MIPS32: xori [[T0]],[[T0]],0x1
3554 ; MIPS32: andi [[T0]],[[T0]],0xff
3555 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
3556 ; MIPS32: sll [[T2]],[[TV_E0]],0x8
3557 ; MIPS32: or [[T0]],[[T0]],[[T2]]
3558 ; MIPS32: srl [[T2]],a0,0x8
3559 ; MIPS32: andi [[T2]],[[T2]],0xff
3560 ; MIPS32: srl [[T1]],[[BV_E0]],0x8
3561 ; MIPS32: andi [[T1]],[[T1]],0xff
3562 ; MIPS32: sll [[T2]],[[T2]],0x18
3563 ; MIPS32: sll [[T1]],[[T1]],0x18
3564 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
3565 ; MIPS32: xori [[T2]],[[T2]],0x1
3566 ; MIPS32: andi [[T2]],[[T2]],0xff
3567 ; MIPS32: sll [[T2]],[[T2]],0x8
3568 ; MIPS32: lui [[T1]],0xffff
3569 ; MIPS32: ori [[T1]],[[T1]],0xff
3570 ; MIPS32: and [[T0]],[[T0]],[[T1]]
3571 ; MIPS32: or [[T2]],[[T2]],[[T0]]
3572 ; MIPS32: srl [[T0]],a0,0x10
3573 ; MIPS32: andi [[T0]],[[T0]],0xff
3574 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
3575 ; MIPS32: andi [[T1]],[[T1]],0xff
3576 ; MIPS32: sll [[T0]],[[T0]],0x18
3577 ; MIPS32: sll [[T1]],[[T1]],0x18
3578 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
3579 ; MIPS32: xori [[T0]],[[T0]],0x1
3580 ; MIPS32: andi [[T0]],[[T0]],0xff
3581 ; MIPS32: sll [[T0]],[[T0]],0x10
3582 ; MIPS32: lui [[T1]],0xff00
3583 ; MIPS32: ori [[T1]],[[T1]],0xffff
3584 ; MIPS32: and [[T2]],[[T2]],[[T1]]
3585 ; MIPS32: or [[T0]],[[T0]],[[T2]]
3586 ; MIPS32: srl [[T3:.*]],a0,0x18
3587 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
3588 ; MIPS32: sll [[T3]],[[T3]],0x18
3589 ; MIPS32: sll [[T4]],[[T4]],0x18
3590 ; MIPS32: sltu [[T3]],[[T3]],[[T4]]
3591 ; MIPS32: xori [[T3]],[[T3]],0x1
3592 ; MIPS32: srl [[T3]],[[T3]],0x18
3593 ; MIPS32: sll [[T0]],[[T0]],0x8
3594 ; MIPS32: srl [[T0]],[[T0]],0x8
3595 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
3596 ; MIPS32: andi [[T4]],a1,0xff
3597 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
3598 ; MIPS32: sll [[T4]],[[T4]],0x18
3599 ; MIPS32: sll [[T2]],[[T2]],0x18
3600 ; MIPS32: sltu [[T4]],[[T4]],[[T2]]
3601 ; MIPS32: xori [[T4]],[[T4]],0x1
3602 ; MIPS32: andi [[T4]],[[T4]],0xff
3603 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
3604 ; MIPS32: sll [[T5]],[[TV_E1]],0x8
3605 ; MIPS32: or [[T4]],[[T4]],[[T5]]
3606 ; MIPS32: srl [[T2]],a1,0x8
3607 ; MIPS32: andi [[T2]],[[T2]],0xff
3608 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
3609 ; MIPS32: andi [[T5]],[[T5]],0xff
3610 ; MIPS32: sll [[T2]],[[T2]],0x18
3611 ; MIPS32: sll [[T5]],[[T5]],0x18
3612 ; MIPS32: sltu [[T2]],[[T2]],[[T5]]
3613 ; MIPS32: xori [[T2]],[[T2]],0x1
3614 ; MIPS32: andi [[T2]],[[T2]],0xff
3615 ; MIPS32: sll [[T2]],[[T2]],0x8
3616 ; MIPS32: lui [[T5]],0xffff
3617 ; MIPS32: ori [[T5]],[[T5]],0xff
3618 ; MIPS32: and [[T4]],[[T4]],[[T5]]
3619 ; MIPS32: or [[T2]],[[T2]],[[T4]]
3620 ; MIPS32: srl [[T4]],a1,0x10
3621 ; MIPS32: andi [[T4]],[[T4]],0xff
3622 ; MIPS32: srl [[T5]],[[BV_E1]],0x10
3623 ; MIPS32: andi [[T5]],[[T5]],0xff
3624 ; MIPS32: sll [[T4]],[[T4]],0x18
3625 ; MIPS32: sll [[T5]],[[T5]],0x18
3626 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
3627 ; MIPS32: xori [[T4]],[[T4]],0x1
3628 ; MIPS32: andi [[T4]],[[T4]],0xff
3629 ; MIPS32: sll [[T4]],[[T4]],0x10
3630 ; MIPS32: lui [[T5]],0xff00
3631 ; MIPS32: ori [[T5]],[[T5]],0xffff
3632 ; MIPS32: and [[T2]],[[T2]],[[T5]]
3633 ; MIPS32: or [[T4]],[[T4]],[[T2]]
3634 ; MIPS32: srl [[T6:.*]],a1,0x18
3635 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
3636 ; MIPS32: sll [[T6]],[[T6]],0x18
3637 ; MIPS32: sll [[T7]],[[T7]],0x18
3638 ; MIPS32: sltu [[T6]],[[T6]],[[T7]]
3639 ; MIPS32: xori [[T6]],[[T6]],0x1
3640 ; MIPS32: srl [[T6]],[[T6]],0x18
3641 ; MIPS32: sll [[T4]],[[T4]],0x8
3642 ; MIPS32: srl [[T4]],[[T4]],0x8
3643 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
3644 ; MIPS32: andi [[T4]],a2,0xff
3645 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
3646 ; MIPS32: sll [[T4]],[[T4]],0x18
3647 ; MIPS32: sll [[T7]],[[T7]],0x18
3648 ; MIPS32: sltu [[T4]],[[T4]],[[T7]]
3649 ; MIPS32: xori [[T4]],[[T4]],0x1
3650 ; MIPS32: andi [[T4]],[[T4]],0xff
3651 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
3652 ; MIPS32: sll [[T8]],[[TV_E2]],0x8
3653 ; MIPS32: or [[T4]],[[T4]],[[T8]]
3654 ; MIPS32: srl [[T7]],a2,0x8
3655 ; MIPS32: andi [[T7]],[[T7]],0xff
3656 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
3657 ; MIPS32: andi [[T2]],[[T2]],0xff
3658 ; MIPS32: sll [[T7]],[[T7]],0x18
3659 ; MIPS32: sll [[T2]],[[T2]],0x18
3660 ; MIPS32: sltu [[T7]],[[T7]],[[T2]]
3661 ; MIPS32: xori [[T7]],[[T7]],0x1
3662 ; MIPS32: andi [[T7]],[[T7]],0xff
3663 ; MIPS32: sll [[T7]],[[T7]],0x8
3664 ; MIPS32: lui [[T2]],0xffff
3665 ; MIPS32: ori [[T2]],[[T2]],0xff
3666 ; MIPS32: and [[T4]],[[T4]],[[T2]]
3667 ; MIPS32: or [[T7]],[[T7]],[[T4]]
3668 ; MIPS32: srl [[T4]],a2,0x10
3669 ; MIPS32: andi [[T4]],[[T4]],0xff
3670 ; MIPS32: srl [[T2]],[[BV_E2]],0x10
3671 ; MIPS32: andi [[T2]],[[T2]],0xff
3672 ; MIPS32: sll [[T4]],[[T4]],0x18
3673 ; MIPS32: sll [[T2]],[[T2]],0x18
3674 ; MIPS32: sltu [[T4]],[[T4]],[[T2]]
3675 ; MIPS32: xori [[T4]],[[T4]],0x1
3676 ; MIPS32: andi [[T4]],[[T4]],0xff
3677 ; MIPS32: sll [[T4]],[[T4]],0x10
3678 ; MIPS32: lui [[T2]],0xff00
3679 ; MIPS32: ori [[T2]],[[T2]],0xffff
3680 ; MIPS32: and [[T7]],[[T7]],[[T2]]
3681 ; MIPS32: or [[T4]],[[T4]],[[T7]]
3682 ; MIPS32: srl [[T9:.*]],a2,0x18
3683 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
3684 ; MIPS32: sll [[T9]],[[T9]],0x18
3685 ; MIPS32: sll [[T10]],[[T10]],0x18
3686 ; MIPS32: sltu [[T9]],[[T9]],[[T10]]
3687 ; MIPS32: xori [[T9]],[[T9]],0x1
3688 ; MIPS32: srl [[T9]],[[T9]],0x18
3689 ; MIPS32: sll [[T4]],[[T4]],0x8
3690 ; MIPS32: srl [[T4]],[[T4]],0x8
3691 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
3692 ; MIPS32: andi [[T4]],a3,0xff
3693 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
3694 ; MIPS32: sll [[T4]],[[T4]],0x18
3695 ; MIPS32: sll [[T7]],[[T7]],0x18
3696 ; MIPS32: sltu [[T4]],[[T4]],[[T7]]
3697 ; MIPS32: xori [[T4]],[[T4]],0x1
3698 ; MIPS32: andi [[T4]],[[T4]],0xff
3699 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
3700 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
3701 ; MIPS32: or [[T4]],[[T4]],[[T11]]
3702 ; MIPS32: srl [[T7]],a3,0x8
3703 ; MIPS32: andi [[T7]],[[T7]],0xff
3704 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
3705 ; MIPS32: andi [[T10]],[[T10]],0xff
3706 ; MIPS32: sll [[T7]],[[T7]],0x18
3707 ; MIPS32: sll [[T10]],[[T10]],0x18
3708 ; MIPS32: sltu [[T7]],[[T7]],[[T10]]
3709 ; MIPS32: xori [[T7]],[[T7]],0x1
3710 ; MIPS32: andi [[T7]],[[T7]],0xff
3711 ; MIPS32: sll [[T7]],[[T7]],0x8
3712 ; MIPS32: lui [[T10]],0xffff
3713 ; MIPS32: ori [[T10]],[[T10]],0xff
3714 ; MIPS32: and [[T4]],[[T4]],[[T10]]
3715 ; MIPS32: or [[T7]],[[T7]],[[T4]]
3716 ; MIPS32: srl [[T4]],a3,0x10
3717 ; MIPS32: andi [[T4]],[[T4]],0xff
3718 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
3719 ; MIPS32: andi [[T10]],[[T10]],0xff
3720 ; MIPS32: sll [[T4]],[[T4]],0x18
3721 ; MIPS32: sll [[T10]],[[T10]],0x18
3722 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
3723 ; MIPS32: xori [[T4]],[[T4]],0x1
3724 ; MIPS32: andi [[T4]],[[T4]],0xff
3725 ; MIPS32: sll [[T4]],[[T4]],0x10
3726 ; MIPS32: lui [[T10]],0xff00
3727 ; MIPS32: ori [[T10]],[[T10]],0xffff
3728 ; MIPS32: and [[T7]],[[T7]],[[T10]]
3729 ; MIPS32: or [[T4]],[[T4]],[[T7]]
3730 ; MIPS32: srl [[T12:.*]],a3,0x18
3731 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
3732 ; MIPS32: sll [[T12]],[[T12]],0x18
3733 ; MIPS32: sll [[T13]],[[T13]],0x18
3734 ; MIPS32: sltu [[T12]],[[T12]],[[T13]]
3735 ; MIPS32: xori [[T12]],[[T12]],0x1
3736 ; MIPS32: srl [[T12]],[[T12]],0x18
3737 ; MIPS32: sll [[T4]],[[T4]],0x8
3738 ; MIPS32: srl [[T4]],[[T4]],0x8
3739 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
389 } 3740 }
390 3741
391 define internal <16 x i1> @test_icmp_v16i8_ugt(<16 x i8> %a, <16 x i8> %b) { 3742 define internal <16 x i1> @test_icmp_v16i8_ugt(<16 x i8> %a, <16 x i8> %b) {
392 entry: 3743 entry:
393 %res = icmp ugt <16 x i8> %a, %b 3744 %res = icmp ugt <16 x i8> %a, %b
394 ret <16 x i1> %res 3745 ret <16 x i1> %res
395 ; CHECK-LABEL: test_icmp_v16i8_ugt 3746 ; CHECK-LABEL: test_icmp_v16i8_ugt
396 ; CHECK: pxor 3747 ; CHECK: pxor
397 ; CHECK: pcmpgtb 3748 ; CHECK: pcmpgtb
3749
3750 ; MIPS32-LABEL: test_icmp_v16i8_ugt
3751 ; MIPS32: lw [[BV_E0:.*]],
3752 ; MIPS32: lw [[BV_E1:.*]],
3753 ; MIPS32: lw [[BV_E2:.*]],
3754 ; MIPS32: lw [[BV_E3:.*]],
3755 ; MIPS32: move [[TV_E0:.*]],zero
3756 ; MIPS32: move [[TV_E1:.*]],zero
3757 ; MIPS32: move [[TV_E2:.*]],zero
3758 ; MIPS32: move [[TV_E3:.*]],zero
3759 ; MIPS32: andi [[T0:.*]],a0,0xff
3760 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
3761 ; MIPS32: sll [[T0]],[[T0]],0x18
3762 ; MIPS32: sll [[T1]],[[T1]],0x18
3763 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
3764 ; MIPS32: andi [[T1]],[[T1]],0xff
3765 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
3766 ; MIPS32: sll [[T2]],[[TV_E0]],0x8
3767 ; MIPS32: or [[T1]],[[T1]],[[T2]]
3768 ; MIPS32: srl [[T2]],a0,0x8
3769 ; MIPS32: andi [[T2]],[[T2]],0xff
3770 ; MIPS32: srl [[T0]],[[BV_E0]],0x8
3771 ; MIPS32: andi [[T0]],[[T0]],0xff
3772 ; MIPS32: sll [[T2]],[[T2]],0x18
3773 ; MIPS32: sll [[T0]],[[T0]],0x18
3774 ; MIPS32: sltu [[T0]],[[T0]],[[T2]]
3775 ; MIPS32: andi [[T0]],[[T0]],0xff
3776 ; MIPS32: sll [[T0]],[[T0]],0x8
3777 ; MIPS32: lui [[T2]],0xffff
3778 ; MIPS32: ori [[T2]],[[T2]],0xff
3779 ; MIPS32: and [[T1]],[[T1]],[[T2]]
3780 ; MIPS32: or [[T0]],[[T0]],[[T1]]
3781 ; MIPS32: srl [[T2]],a0,0x10
3782 ; MIPS32: andi [[T2]],[[T2]],0xff
3783 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
3784 ; MIPS32: andi [[T1]],[[T1]],0xff
3785 ; MIPS32: sll [[T2]],[[T2]],0x18
3786 ; MIPS32: sll [[T1]],[[T1]],0x18
3787 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
3788 ; MIPS32: andi [[T1]],[[T1]],0xff
3789 ; MIPS32: sll [[T1]],[[T1]],0x10
3790 ; MIPS32: lui [[T2]],0xff00
3791 ; MIPS32: ori [[T2]],[[T2]],0xffff
3792 ; MIPS32: and [[T0]],[[T0]],[[T2]]
3793 ; MIPS32: or [[T1]],[[T1]],[[T0]]
3794 ; MIPS32: srl [[T3:.*]],a0,0x18
3795 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
3796 ; MIPS32: sll [[T3]],[[T3]],0x18
3797 ; MIPS32: sll [[T4]],[[T4]],0x18
3798 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
3799 ; MIPS32: srl [[T4]],[[T4]],0x18
3800 ; MIPS32: sll [[T1]],[[T1]],0x8
3801 ; MIPS32: srl [[T1]],[[T1]],0x8
3802 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
3803 ; MIPS32: andi [[T3]],a1,0xff
3804 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
3805 ; MIPS32: sll [[T3]],[[T3]],0x18
3806 ; MIPS32: sll [[T2]],[[T2]],0x18
3807 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
3808 ; MIPS32: andi [[T2]],[[T2]],0xff
3809 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
3810 ; MIPS32: sll [[T5]],[[TV_E1]],0x8
3811 ; MIPS32: or [[T2]],[[T2]],[[T5]]
3812 ; MIPS32: srl [[T3]],a1,0x8
3813 ; MIPS32: andi [[T3]],[[T3]],0xff
3814 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
3815 ; MIPS32: andi [[T5]],[[T5]],0xff
3816 ; MIPS32: sll [[T3]],[[T3]],0x18
3817 ; MIPS32: sll [[T5]],[[T5]],0x18
3818 ; MIPS32: sltu [[T5]],[[T5]],[[T3]]
3819 ; MIPS32: andi [[T5]],[[T5]],0xff
3820 ; MIPS32: sll [[T5]],[[T5]],0x8
3821 ; MIPS32: lui [[T3]],0xffff
3822 ; MIPS32: ori [[T3]],[[T3]],0xff
3823 ; MIPS32: and [[T2]],[[T2]],[[T3]]
3824 ; MIPS32: or [[T5]],[[T5]],[[T2]]
3825 ; MIPS32: srl [[T3]],a1,0x10
3826 ; MIPS32: andi [[T3]],[[T3]],0xff
3827 ; MIPS32: srl [[T2]],[[BV_E1]],0x10
3828 ; MIPS32: andi [[T2]],[[T2]],0xff
3829 ; MIPS32: sll [[T3]],[[T3]],0x18
3830 ; MIPS32: sll [[T2]],[[T2]],0x18
3831 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
3832 ; MIPS32: andi [[T2]],[[T2]],0xff
3833 ; MIPS32: sll [[T2]],[[T2]],0x10
3834 ; MIPS32: lui [[T3]],0xff00
3835 ; MIPS32: ori [[T3]],[[T3]],0xffff
3836 ; MIPS32: and [[T5]],[[T5]],[[T3]]
3837 ; MIPS32: or [[T2]],[[T2]],[[T5]]
3838 ; MIPS32: srl [[T6:.*]],a1,0x18
3839 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
3840 ; MIPS32: sll [[T6]],[[T6]],0x18
3841 ; MIPS32: sll [[T7]],[[T7]],0x18
3842 ; MIPS32: sltu [[T7]],[[T7]],[[T6]]
3843 ; MIPS32: srl [[T7]],[[T7]],0x18
3844 ; MIPS32: sll [[T2]],[[T2]],0x8
3845 ; MIPS32: srl [[T2]],[[T2]],0x8
3846 ; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
3847 ; MIPS32: andi [[T3]],a2,0xff
3848 ; MIPS32: andi [[T6]],[[BV_E2]],0xff
3849 ; MIPS32: sll [[T3]],[[T3]],0x18
3850 ; MIPS32: sll [[T6]],[[T6]],0x18
3851 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
3852 ; MIPS32: andi [[T6]],[[T6]],0xff
3853 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
3854 ; MIPS32: sll [[T8]],[[TV_E2]],0x8
3855 ; MIPS32: or [[T6]],[[T6]],[[T8]]
3856 ; MIPS32: srl [[T3]],a2,0x8
3857 ; MIPS32: andi [[T3]],[[T3]],0xff
3858 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
3859 ; MIPS32: andi [[T2]],[[T2]],0xff
3860 ; MIPS32: sll [[T3]],[[T3]],0x18
3861 ; MIPS32: sll [[T2]],[[T2]],0x18
3862 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
3863 ; MIPS32: andi [[T2]],[[T2]],0xff
3864 ; MIPS32: sll [[T2]],[[T2]],0x8
3865 ; MIPS32: lui [[T3]],0xffff
3866 ; MIPS32: ori [[T3]],[[T3]],0xff
3867 ; MIPS32: and [[T6]],[[T6]],[[T3]]
3868 ; MIPS32: or [[T2]],[[T2]],[[T6]]
3869 ; MIPS32: srl [[T3]],a2,0x10
3870 ; MIPS32: andi [[T3]],[[T3]],0xff
3871 ; MIPS32: srl [[T6]],[[BV_E2]],0x10
3872 ; MIPS32: andi [[T6]],[[T6]],0xff
3873 ; MIPS32: sll [[T3]],[[T3]],0x18
3874 ; MIPS32: sll [[T6]],[[T6]],0x18
3875 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
3876 ; MIPS32: andi [[T6]],[[T6]],0xff
3877 ; MIPS32: sll [[T6]],[[T6]],0x10
3878 ; MIPS32: lui [[T3]],0xff00
3879 ; MIPS32: ori [[T3]],[[T3]],0xffff
3880 ; MIPS32: and [[T2]],[[T2]],[[T3]]
3881 ; MIPS32: or [[T6]],[[T6]],[[T2]]
3882 ; MIPS32: srl [[T9:.*]],a2,0x18
3883 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
3884 ; MIPS32: sll [[T9]],[[T9]],0x18
3885 ; MIPS32: sll [[T10]],[[T10]],0x18
3886 ; MIPS32: sltu [[T10]],[[T10]],[[T9]]
3887 ; MIPS32: srl [[T10]],[[T10]],0x18
3888 ; MIPS32: sll [[T6]],[[T6]],0x8
3889 ; MIPS32: srl [[T6]],[[T6]],0x8
3890 ; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
3891 ; MIPS32: andi [[T3]],a3,0xff
3892 ; MIPS32: andi [[T6]],[[BV_E3]],0xff
3893 ; MIPS32: sll [[T3]],[[T3]],0x18
3894 ; MIPS32: sll [[T6]],[[T6]],0x18
3895 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
3896 ; MIPS32: andi [[T6]],[[T6]],0xff
3897 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
3898 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
3899 ; MIPS32: or [[T6]],[[T6]],[[T11]]
3900 ; MIPS32: srl [[T3]],a3,0x8
3901 ; MIPS32: andi [[T3]],[[T3]],0xff
3902 ; MIPS32: srl [[T9]],[[BV_E3]],0x8
3903 ; MIPS32: andi [[T9]],[[T9]],0xff
3904 ; MIPS32: sll [[T3]],[[T3]],0x18
3905 ; MIPS32: sll [[T9]],[[T9]],0x18
3906 ; MIPS32: sltu [[T9]],[[T9]],[[T3]]
3907 ; MIPS32: andi [[T9]],[[T9]],0xff
3908 ; MIPS32: sll [[T9]],[[T9]],0x8
3909 ; MIPS32: lui [[T3]],0xffff
3910 ; MIPS32: ori [[T3]],[[T3]],0xff
3911 ; MIPS32: and [[T6]],[[T6]],[[T3]]
3912 ; MIPS32: or [[T9]],[[T9]],[[T6]]
3913 ; MIPS32: srl [[T3]],a3,0x10
3914 ; MIPS32: andi [[T3]],[[T3]],0xff
3915 ; MIPS32: srl [[T6]],[[BV_E3]],0x10
3916 ; MIPS32: andi [[T6]],[[T6]],0xff
3917 ; MIPS32: sll [[T3]],[[T3]],0x18
3918 ; MIPS32: sll [[T6]],[[T6]],0x18
3919 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
3920 ; MIPS32: andi [[T6]],[[T6]],0xff
3921 ; MIPS32: sll [[T6]],[[T6]],0x10
3922 ; MIPS32: lui [[T3]],0xff00
3923 ; MIPS32: ori [[T3]],[[T3]],0xffff
3924 ; MIPS32: and [[T9]],[[T9]],[[T3]]
3925 ; MIPS32: or [[T6]],[[T6]],[[T9]]
3926 ; MIPS32: srl [[T12:.*]],a3,0x18
3927 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
3928 ; MIPS32: sll [[T12]],[[T12]],0x18
3929 ; MIPS32: sll [[T13]],[[T13]],0x18
3930 ; MIPS32: sltu [[T13]],[[T13]],[[T12]]
3931 ; MIPS32: srl [[T13]],[[T13]],0x18
3932 ; MIPS32: sll [[T6]],[[T6]],0x8
3933 ; MIPS32: srl [[T6]],[[T6]],0x8
3934 ; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
398 } 3935 }
399 3936
400 define internal <16 x i1> @test_icmp_v16i8_ule(<16 x i8> %a, <16 x i8> %b) { 3937 define internal <16 x i1> @test_icmp_v16i8_ule(<16 x i8> %a, <16 x i8> %b) {
401 entry: 3938 entry:
402 %res = icmp ule <16 x i8> %a, %b 3939 %res = icmp ule <16 x i8> %a, %b
403 ret <16 x i1> %res 3940 ret <16 x i1> %res
404 ; CHECK-LABEL: test_icmp_v16i8_ule 3941 ; CHECK-LABEL: test_icmp_v16i8_ule
405 ; CHECK: pxor 3942 ; CHECK: pxor
406 ; CHECK: pcmpgtb 3943 ; CHECK: pcmpgtb
407 ; CHECK: pxor 3944 ; CHECK: pxor
3945
3946 ; MIPS32-LABEL: test_icmp_v16i8_ule
3947 ; MIPS32: lw [[BV_E0:.*]],
3948 ; MIPS32: lw [[BV_E1:.*]],
3949 ; MIPS32: lw [[BV_E2:.*]],
3950 ; MIPS32: lw [[BV_E3:.*]],
3951 ; MIPS32: move [[TV_E0:.*]],zero
3952 ; MIPS32: move [[TV_E1:.*]],zero
3953 ; MIPS32: move [[TV_E2:.*]],zero
3954 ; MIPS32: move [[TV_E3:.*]],zero
3955 ; MIPS32: andi [[T0:.*]],a0,0xff
3956 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
3957 ; MIPS32: sll [[T0]],[[T0]],0x18
3958 ; MIPS32: sll [[T1]],[[T1]],0x18
3959 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
3960 ; MIPS32: xori [[T1]],[[T1]],0x1
3961 ; MIPS32: andi [[T1]],[[T1]],0xff
3962 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
3963 ; MIPS32: sll [[T2]],[[TV_E0]],0x8
3964 ; MIPS32: or [[T1]],[[T1]],[[T2]]
3965 ; MIPS32: srl [[T2]],a0,0x8
3966 ; MIPS32: andi [[T2]],[[T2]],0xff
3967 ; MIPS32: srl [[T0]],[[BV_E0]],0x8
3968 ; MIPS32: andi [[T0]],[[T0]],0xff
3969 ; MIPS32: sll [[T2]],[[T2]],0x18
3970 ; MIPS32: sll [[T0]],[[T0]],0x18
3971 ; MIPS32: sltu [[T0]],[[T0]],[[T2]]
3972 ; MIPS32: xori [[T0]],[[T0]],0x1
3973 ; MIPS32: andi [[T0]],[[T0]],0xff
3974 ; MIPS32: sll [[T0]],[[T0]],0x8
3975 ; MIPS32: lui [[T2]],0xffff
3976 ; MIPS32: ori [[T2]],[[T2]],0xff
3977 ; MIPS32: and [[T1]],[[T1]],[[T2]]
3978 ; MIPS32: or [[T0]],[[T0]],[[T1]]
3979 ; MIPS32: srl [[T2]],a0,0x10
3980 ; MIPS32: andi [[T2]],[[T2]],0xff
3981 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
3982 ; MIPS32: andi [[T1]],[[T1]],0xff
3983 ; MIPS32: sll [[T2]],[[T2]],0x18
3984 ; MIPS32: sll [[T1]],[[T1]],0x18
3985 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
3986 ; MIPS32: xori [[T1]],[[T1]],0x1
3987 ; MIPS32: andi [[T1]],[[T1]],0xff
3988 ; MIPS32: sll [[T1]],[[T1]],0x10
3989 ; MIPS32: lui [[T2]],0xff00
3990 ; MIPS32: ori [[T2]],[[T2]],0xffff
3991 ; MIPS32: and [[T0]],[[T0]],[[T2]]
3992 ; MIPS32: or [[T1]],[[T1]],[[T0]]
3993 ; MIPS32: srl [[T3:.*]],a0,0x18
3994 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
3995 ; MIPS32: sll [[T3]],[[T3]],0x18
3996 ; MIPS32: sll [[T4]],[[T4]],0x18
3997 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
3998 ; MIPS32: xori [[T4]],[[T4]],0x1
3999 ; MIPS32: srl [[T4]],[[T4]],0x18
4000 ; MIPS32: sll [[T1]],[[T1]],0x8
4001 ; MIPS32: srl [[T1]],[[T1]],0x8
4002 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
4003 ; MIPS32: andi [[T3]],a1,0xff
4004 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
4005 ; MIPS32: sll [[T3]],[[T3]],0x18
4006 ; MIPS32: sll [[T2]],[[T2]],0x18
4007 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
4008 ; MIPS32: xori [[T2]],[[T2]],0x1
4009 ; MIPS32: andi [[T2]],[[T2]],0xff
4010 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
4011 ; MIPS32: sll [[T5]],[[TV_E1]],0x8
4012 ; MIPS32: or [[T2]],[[T2]],[[T5]]
4013 ; MIPS32: srl [[T3]],a1,0x8
4014 ; MIPS32: andi [[T3]],[[T3]],0xff
4015 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
4016 ; MIPS32: andi [[T5]],[[T5]],0xff
4017 ; MIPS32: sll [[T3]],[[T3]],0x18
4018 ; MIPS32: sll [[T5]],[[T5]],0x18
4019 ; MIPS32: sltu [[T5]],[[T5]],[[T3]]
4020 ; MIPS32: xori [[T5]],[[T5]],0x1
4021 ; MIPS32: andi [[T5]],[[T5]],0xff
4022 ; MIPS32: sll [[T5]],[[T5]],0x8
4023 ; MIPS32: lui [[T3]],0xffff
4024 ; MIPS32: ori [[T3]],[[T3]],0xff
4025 ; MIPS32: and [[T2]],[[T2]],[[T3]]
4026 ; MIPS32: or [[T5]],[[T5]],[[T2]]
4027 ; MIPS32: srl [[T3]],a1,0x10
4028 ; MIPS32: andi [[T3]],[[T3]],0xff
4029 ; MIPS32: srl [[T2]],[[BV_E1]],0x10
4030 ; MIPS32: andi [[T2]],[[T2]],0xff
4031 ; MIPS32: sll [[T3]],[[T3]],0x18
4032 ; MIPS32: sll [[T2]],[[T2]],0x18
4033 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
4034 ; MIPS32: xori [[T2]],[[T2]],0x1
4035 ; MIPS32: andi [[T2]],[[T2]],0xff
4036 ; MIPS32: sll [[T2]],[[T2]],0x10
4037 ; MIPS32: lui [[T3]],0xff00
4038 ; MIPS32: ori [[T3]],[[T3]],0xffff
4039 ; MIPS32: and [[T5]],[[T5]],[[T3]]
4040 ; MIPS32: or [[T2]],[[T2]],[[T5]]
4041 ; MIPS32: srl [[T6:.*]],a1,0x18
4042 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
4043 ; MIPS32: sll [[T6]],[[T6]],0x18
4044 ; MIPS32: sll [[T7]],[[T7]],0x18
4045 ; MIPS32: sltu [[T7]],[[T7]],[[T6]]
4046 ; MIPS32: xori [[T7]],[[T7]],0x1
4047 ; MIPS32: srl [[T7]],[[T7]],0x18
4048 ; MIPS32: sll [[T2]],[[T2]],0x8
4049 ; MIPS32: srl [[T2]],[[T2]],0x8
4050 ; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
4051 ; MIPS32: andi [[T3]],a2,0xff
4052 ; MIPS32: andi [[T6]],[[BV_E2]],0xff
4053 ; MIPS32: sll [[T3]],[[T3]],0x18
4054 ; MIPS32: sll [[T6]],[[T6]],0x18
4055 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
4056 ; MIPS32: xori [[T6]],[[T6]],0x1
4057 ; MIPS32: andi [[T6]],[[T6]],0xff
4058 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
4059 ; MIPS32: sll [[T8]],[[TV_E2]],0x8
4060 ; MIPS32: or [[T6]],[[T6]],[[T8]]
4061 ; MIPS32: srl [[T3]],a2,0x8
4062 ; MIPS32: andi [[T3]],[[T3]],0xff
4063 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
4064 ; MIPS32: andi [[T2]],[[T2]],0xff
4065 ; MIPS32: sll [[T3]],[[T3]],0x18
4066 ; MIPS32: sll [[T2]],[[T2]],0x18
4067 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
4068 ; MIPS32: xori [[T2]],[[T2]],0x1
4069 ; MIPS32: andi [[T2]],[[T2]],0xff
4070 ; MIPS32: sll [[T2]],[[T2]],0x8
4071 ; MIPS32: lui [[T3]],0xffff
4072 ; MIPS32: ori [[T3]],[[T3]],0xff
4073 ; MIPS32: and [[T6]],[[T6]],[[T3]]
4074 ; MIPS32: or [[T2]],[[T2]],[[T6]]
4075 ; MIPS32: srl [[T3]],a2,0x10
4076 ; MIPS32: andi [[T3]],[[T3]],0xff
4077 ; MIPS32: srl [[T6]],[[BV_E2]],0x10
4078 ; MIPS32: andi [[T6]],[[T6]],0xff
4079 ; MIPS32: sll [[T3]],[[T3]],0x18
4080 ; MIPS32: sll [[T6]],[[T6]],0x18
4081 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
4082 ; MIPS32: xori [[T6]],[[T6]],0x1
4083 ; MIPS32: andi [[T6]],[[T6]],0xff
4084 ; MIPS32: sll [[T6]],[[T6]],0x10
4085 ; MIPS32: lui [[T3]],0xff00
4086 ; MIPS32: ori [[T3]],[[T3]],0xffff
4087 ; MIPS32: and [[T2]],[[T2]],[[T3]]
4088 ; MIPS32: or [[T6]],[[T6]],[[T2]]
4089 ; MIPS32: srl [[T9:.*]],a2,0x18
4090 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
4091 ; MIPS32: sll [[T9]],[[T9]],0x18
4092 ; MIPS32: sll [[T10]],[[T10]],0x18
4093 ; MIPS32: sltu [[T10]],[[T10]],[[T9]]
4094 ; MIPS32: xori [[T10]],[[T10]],0x1
4095 ; MIPS32: srl [[T10]],[[T10]],0x18
4096 ; MIPS32: sll [[T6]],[[T6]],0x8
4097 ; MIPS32: srl [[T6]],[[T6]],0x8
4098 ; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
4099 ; MIPS32: andi [[T3]],a3,0xff
4100 ; MIPS32: andi [[T6]],[[BV_E3]],0xff
4101 ; MIPS32: sll [[T3]],[[T3]],0x18
4102 ; MIPS32: sll [[T6]],[[T6]],0x18
4103 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
4104 ; MIPS32: xori [[T6]],[[T6]],0x1
4105 ; MIPS32: andi [[T6]],[[T6]],0xff
4106 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
4107 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
4108 ; MIPS32: or [[T6]],[[T6]],[[T11]]
4109 ; MIPS32: srl [[T3]],a3,0x8
4110 ; MIPS32: andi [[T3]],[[T3]],0xff
4111 ; MIPS32: srl [[T9]],[[BV_E3]],0x8
4112 ; MIPS32: andi [[T9]],[[T9]],0xff
4113 ; MIPS32: sll [[T3]],[[T3]],0x18
4114 ; MIPS32: sll [[T9]],[[T9]],0x18
4115 ; MIPS32: sltu [[T9]],[[T9]],[[T3]]
4116 ; MIPS32: xori [[T9]],[[T9]],0x1
4117 ; MIPS32: andi [[T9]],[[T9]],0xff
4118 ; MIPS32: sll [[T9]],[[T9]],0x8
4119 ; MIPS32: lui [[T3]],0xffff
4120 ; MIPS32: ori [[T3]],[[T3]],0xff
4121 ; MIPS32: and [[T6]],[[T6]],[[T3]]
4122 ; MIPS32: or [[T9]],[[T9]],[[T6]]
4123 ; MIPS32: srl [[T3]],a3,0x10
4124 ; MIPS32: andi [[T3]],[[T3]],0xff
4125 ; MIPS32: srl [[T6]],[[BV_E3]],0x10
4126 ; MIPS32: andi [[T6]],[[T6]],0xff
4127 ; MIPS32: sll [[T3]],[[T3]],0x18
4128 ; MIPS32: sll [[T6]],[[T6]],0x18
4129 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
4130 ; MIPS32: xori [[T6]],[[T6]],0x1
4131 ; MIPS32: andi [[T6]],[[T6]],0xff
4132 ; MIPS32: sll [[T6]],[[T6]],0x10
4133 ; MIPS32: lui [[T3]],0xff00
4134 ; MIPS32: ori [[T3]],[[T3]],0xffff
4135 ; MIPS32: and [[T9]],[[T9]],[[T3]]
4136 ; MIPS32: or [[T6]],[[T6]],[[T9]]
4137 ; MIPS32: srl [[T12:.*]],a3,0x18
4138 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
4139 ; MIPS32: sll [[T12]],[[T12]],0x18
4140 ; MIPS32: sll [[T13]],[[T13]],0x18
4141 ; MIPS32: sltu [[T13]],[[T13]],[[T12]]
4142 ; MIPS32: xori [[T13]],[[T13]],0x1
4143 ; MIPS32: srl [[T13]],[[T13]],0x18
4144 ; MIPS32: sll [[T6]],[[T6]],0x8
4145 ; MIPS32: srl [[T6]],[[T6]],0x8
4146 ; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
408 } 4147 }
409 4148
410 define internal <16 x i1> @test_icmp_v16i8_ult(<16 x i8> %a, <16 x i8> %b) { 4149 define internal <16 x i1> @test_icmp_v16i8_ult(<16 x i8> %a, <16 x i8> %b) {
411 entry: 4150 entry:
412 %res = icmp ult <16 x i8> %a, %b 4151 %res = icmp ult <16 x i8> %a, %b
413 ret <16 x i1> %res 4152 ret <16 x i1> %res
414 ; CHECK-LABEL: test_icmp_v16i8_ult 4153 ; CHECK-LABEL: test_icmp_v16i8_ult
415 ; CHECK: pxor 4154 ; CHECK: pxor
416 ; CHECK: pcmpgtb 4155 ; CHECK: pcmpgtb
4156
4157 ; MIPS32-LABEL: test_icmp_v16i8_ult
4158 ; MIPS32: lw [[BV_E0:.*]],
4159 ; MIPS32: lw [[BV_E1:.*]],
4160 ; MIPS32: lw [[BV_E2:.*]],
4161 ; MIPS32: lw [[BV_E3:.*]],
4162 ; MIPS32: move [[TV_E0:.*]],zero
4163 ; MIPS32: move [[TV_E1:.*]],zero
4164 ; MIPS32: move [[TV_E2:.*]],zero
4165 ; MIPS32: move [[TV_E3:.*]],zero
4166 ; MIPS32: andi [[T0:.*]],a0,0xff
4167 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
4168 ; MIPS32: sll [[T0]],[[T0]],0x18
4169 ; MIPS32: sll [[T1]],[[T1]],0x18
4170 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
4171 ; MIPS32: andi [[T0]],[[T0]],0xff
4172 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
4173 ; MIPS32: sll [[T2]],[[TV_E0]],0x8
4174 ; MIPS32: or [[T0]],[[T0]],[[T2]]
4175 ; MIPS32: srl [[T2]],a0,0x8
4176 ; MIPS32: andi [[T2]],[[T2]],0xff
4177 ; MIPS32: srl [[T1]],[[BV_E0]],0x8
4178 ; MIPS32: andi [[T1]],[[T1]],0xff
4179 ; MIPS32: sll [[T2]],[[T2]],0x18
4180 ; MIPS32: sll [[T1]],[[T1]],0x18
4181 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
4182 ; MIPS32: andi [[T2]],[[T2]],0xff
4183 ; MIPS32: sll [[T2]],[[T2]],0x8
4184 ; MIPS32: lui [[T1]],0xffff
4185 ; MIPS32: ori [[T1]],[[T1]],0xff
4186 ; MIPS32: and [[T0]],[[T0]],[[T1]]
4187 ; MIPS32: or [[T2]],[[T2]],[[T0]]
4188 ; MIPS32: srl [[T0]],a0,0x10
4189 ; MIPS32: andi [[T0]],[[T0]],0xff
4190 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
4191 ; MIPS32: andi [[T1]],[[T1]],0xff
4192 ; MIPS32: sll [[T0]],[[T0]],0x18
4193 ; MIPS32: sll [[T1]],[[T1]],0x18
4194 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
4195 ; MIPS32: andi [[T0]],[[T0]],0xff
4196 ; MIPS32: sll [[T0]],[[T0]],0x10
4197 ; MIPS32: lui [[T1]],0xff00
4198 ; MIPS32: ori [[T1]],[[T1]],0xffff
4199 ; MIPS32: and [[T2]],[[T2]],[[T1]]
4200 ; MIPS32: or [[T0]],[[T0]],[[T2]]
4201 ; MIPS32: srl [[T3:.*]],a0,0x18
4202 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
4203 ; MIPS32: sll [[T3]],[[T3]],0x18
4204 ; MIPS32: sll [[T4]],[[T4]],0x18
4205 ; MIPS32: sltu [[T3]],[[T3]],[[T4]]
4206 ; MIPS32: srl [[T3]],[[T3]],0x18
4207 ; MIPS32: sll [[T0]],[[T0]],0x8
4208 ; MIPS32: srl [[T0]],[[T0]],0x8
4209 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
4210 ; MIPS32: andi [[T4]],a1,0xff
4211 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
4212 ; MIPS32: sll [[T4]],[[T4]],0x18
4213 ; MIPS32: sll [[T2]],[[T2]],0x18
4214 ; MIPS32: sltu [[T4]],[[T4]],[[T2]]
4215 ; MIPS32: andi [[T4]],[[T4]],0xff
4216 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
4217 ; MIPS32: sll [[T5]],[[TV_E1]],0x8
4218 ; MIPS32: or [[T4]],[[T4]],[[T5]]
4219 ; MIPS32: srl [[T2]],a1,0x8
4220 ; MIPS32: andi [[T2]],[[T2]],0xff
4221 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
4222 ; MIPS32: andi [[T5]],[[T5]],0xff
4223 ; MIPS32: sll [[T2]],[[T2]],0x18
4224 ; MIPS32: sll [[T5]],[[T5]],0x18
4225 ; MIPS32: sltu [[T2]],[[T2]],[[T5]]
4226 ; MIPS32: andi [[T2]],[[T2]],0xff
4227 ; MIPS32: sll [[T2]],[[T2]],0x8
4228 ; MIPS32: lui [[T5]],0xffff
4229 ; MIPS32: ori [[T5]],[[T5]],0xff
4230 ; MIPS32: and [[T4]],[[T4]],[[T5]]
4231 ; MIPS32: or [[T2]],[[T2]],[[T4]]
4232 ; MIPS32: srl [[T4]],a1,0x10
4233 ; MIPS32: andi [[T4]],[[T4]],0xff
4234 ; MIPS32: srl [[T5]],[[BV_E1]],0x10
4235 ; MIPS32: andi [[T5]],[[T5]],0xff
4236 ; MIPS32: sll [[T4]],[[T4]],0x18
4237 ; MIPS32: sll [[T5]],[[T5]],0x18
4238 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
4239 ; MIPS32: andi [[T4]],[[T4]],0xff
4240 ; MIPS32: sll [[T4]],[[T4]],0x10
4241 ; MIPS32: lui [[T5]],0xff00
4242 ; MIPS32: ori [[T5]],[[T5]],0xffff
4243 ; MIPS32: and [[T2]],[[T2]],[[T5]]
4244 ; MIPS32: or [[T4]],[[T4]],[[T2]]
4245 ; MIPS32: srl [[T6:.*]],a1,0x18
4246 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
4247 ; MIPS32: sll [[T6]],[[T6]],0x18
4248 ; MIPS32: sll [[T7]],[[T7]],0x18
4249 ; MIPS32: sltu [[T6]],[[T6]],[[T7]]
4250 ; MIPS32: srl [[T6]],[[T6]],0x18
4251 ; MIPS32: sll [[T4]],[[T4]],0x8
4252 ; MIPS32: srl [[T4]],[[T4]],0x8
4253 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
4254 ; MIPS32: andi [[T4]],a2,0xff
4255 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
4256 ; MIPS32: sll [[T4]],[[T4]],0x18
4257 ; MIPS32: sll [[T7]],[[T7]],0x18
4258 ; MIPS32: sltu [[T4]],[[T4]],[[T7]]
4259 ; MIPS32: andi [[T4]],[[T4]],0xff
4260 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
4261 ; MIPS32: sll [[T8]],[[TV_E2]],0x8
4262 ; MIPS32: or [[T4]],[[T4]],[[T8]]
4263 ; MIPS32: srl [[T7]],a2,0x8
4264 ; MIPS32: andi [[T7]],[[T7]],0xff
4265 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
4266 ; MIPS32: andi [[T2]],[[T2]],0xff
4267 ; MIPS32: sll [[T7]],[[T7]],0x18
4268 ; MIPS32: sll [[T2]],[[T2]],0x18
4269 ; MIPS32: sltu [[T7]],[[T7]],[[T2]]
4270 ; MIPS32: andi [[T7]],[[T7]],0xff
4271 ; MIPS32: sll [[T7]],[[T7]],0x8
4272 ; MIPS32: lui [[T2]],0xffff
4273 ; MIPS32: ori [[T2]],[[T2]],0xff
4274 ; MIPS32: and [[T4]],[[T4]],[[T2]]
4275 ; MIPS32: or [[T7]],[[T7]],[[T4]]
4276 ; MIPS32: srl [[T4]],a2,0x10
4277 ; MIPS32: andi [[T4]],[[T4]],0xff
4278 ; MIPS32: srl [[T2]],[[BV_E2]],0x10
4279 ; MIPS32: andi [[T2]],[[T2]],0xff
4280 ; MIPS32: sll [[T4]],[[T4]],0x18
4281 ; MIPS32: sll [[T2]],[[T2]],0x18
4282 ; MIPS32: sltu [[T4]],[[T4]],[[T2]]
4283 ; MIPS32: andi [[T4]],[[T4]],0xff
4284 ; MIPS32: sll [[T4]],[[T4]],0x10
4285 ; MIPS32: lui [[T2]],0xff00
4286 ; MIPS32: ori [[T2]],[[T2]],0xffff
4287 ; MIPS32: and [[T7]],[[T7]],[[T2]]
4288 ; MIPS32: or [[T4]],[[T4]],[[T7]]
4289 ; MIPS32: srl [[T9:.*]],a2,0x18
4290 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
4291 ; MIPS32: sll [[T9]],[[T9]],0x18
4292 ; MIPS32: sll [[T10]],[[T10]],0x18
4293 ; MIPS32: sltu [[T9]],[[T9]],[[T10]]
4294 ; MIPS32: srl [[T9]],[[T9]],0x18
4295 ; MIPS32: sll [[T4]],[[T4]],0x8
4296 ; MIPS32: srl [[T4]],[[T4]],0x8
4297 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
4298 ; MIPS32: andi [[T4]],a3,0xff
4299 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
4300 ; MIPS32: sll [[T4]],[[T4]],0x18
4301 ; MIPS32: sll [[T7]],[[T7]],0x18
4302 ; MIPS32: sltu [[T4]],[[T4]],[[T7]]
4303 ; MIPS32: andi [[T4]],[[T4]],0xff
4304 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
4305 ; MIPS32: sll [[T11]],[[TV_E3]],0x8
4306 ; MIPS32: or [[T4]],[[T4]],[[T11]]
4307 ; MIPS32: srl [[T7]],a3,0x8
4308 ; MIPS32: andi [[T7]],[[T7]],0xff
4309 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
4310 ; MIPS32: andi [[T10]],[[T10]],0xff
4311 ; MIPS32: sll [[T7]],[[T7]],0x18
4312 ; MIPS32: sll [[T10]],[[T10]],0x18
4313 ; MIPS32: sltu [[T7]],[[T7]],[[T10]]
4314 ; MIPS32: andi [[T7]],[[T7]],0xff
4315 ; MIPS32: sll [[T7]],[[T7]],0x8
4316 ; MIPS32: lui [[T10]],0xffff
4317 ; MIPS32: ori [[T10]],[[T10]],0xff
4318 ; MIPS32: and [[T4]],[[T4]],[[T10]]
4319 ; MIPS32: or [[T7]],[[T7]],[[T4]]
4320 ; MIPS32: srl [[T4]],a3,0x10
4321 ; MIPS32: andi [[T4]],[[T4]],0xff
4322 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
4323 ; MIPS32: andi [[T10]],[[T10]],0xff
4324 ; MIPS32: sll [[T4]],[[T4]],0x18
4325 ; MIPS32: sll [[T10]],[[T10]],0x18
4326 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
4327 ; MIPS32: andi [[T4]],[[T4]],0xff
4328 ; MIPS32: sll [[T4]],[[T4]],0x10
4329 ; MIPS32: lui [[T10]],0xff00
4330 ; MIPS32: ori [[T10]],[[T10]],0xffff
4331 ; MIPS32: and [[T7]],[[T7]],[[T10]]
4332 ; MIPS32: or [[T4]],[[T4]],[[T7]]
4333 ; MIPS32: srl [[T12:.*]],a3,0x18
4334 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
4335 ; MIPS32: sll [[T12]],[[T12]],0x18
4336 ; MIPS32: sll [[T13]],[[T13]],0x18
4337 ; MIPS32: sltu [[T12]],[[T12]],[[T13]]
4338 ; MIPS32: srl [[T12]],[[T12]],0x18
4339 ; MIPS32: sll [[T4]],[[T4]],0x8
4340 ; MIPS32: srl [[T4]],[[T4]],0x8
4341 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
417 } 4342 }
418 4343
419 define internal <16 x i1> @test_icmp_v16i1_eq(<16 x i1> %a, <16 x i1> %b) { 4344 define internal <16 x i1> @test_icmp_v16i1_eq(<16 x i1> %a, <16 x i1> %b) {
420 entry: 4345 entry:
421 %res = icmp eq <16 x i1> %a, %b 4346 %res = icmp eq <16 x i1> %a, %b
422 ret <16 x i1> %res 4347 ret <16 x i1> %res
423 ; CHECK-LABEL: test_icmp_v16i1_eq 4348 ; CHECK-LABEL: test_icmp_v16i1_eq
424 ; CHECK: pcmpeqb 4349 ; CHECK: pcmpeqb
4350
4351 ; MIPS32-LABEL: test_icmp_v16i1_eq
4352 ; MIPS32: lw [[BV_E0:.*]],
4353 ; MIPS32: lw [[BV_E1:.*]],
4354 ; MIPS32: lw [[BV_E2:.*]],
4355 ; MIPS32: lw [[BV_E3:.*]],
4356 ; MIPS32: move [[TV_E0:.*]],zero
4357 ; MIPS32: move [[TV_E1:.*]],zero
4358 ; MIPS32: move [[TV_E2:.*]],zero
4359 ; MIPS32: move [[TV_E3:.*]],zero
4360 ; MIPS32: andi [[T0:.*]],a0,0xff
4361 ; MIPS32: andi [[T0]],[[T0]],0x1
4362 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
4363 ; MIPS32: andi [[T1]],[[T1]],0x1
4364 ; MIPS32: sll [[T0]],[[T0]],0x1f
4365 ; MIPS32: sll [[T1]],[[T1]],0x1f
4366 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
4367 ; MIPS32: sltiu [[T0]],[[T0]],1
4368 ; MIPS32: andi [[T0]],[[T0]],0xff
4369 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
4370 ; MIPS32: sll [[T2]],[[T2]],0x8
4371 ; MIPS32: or [[T0]],[[T0]],[[T2]]
4372 ; MIPS32: srl [[T2]],a0,0x8
4373 ; MIPS32: andi [[T2]],[[T2]],0xff
4374 ; MIPS32: andi [[T2]],[[T2]],0x1
4375 ; MIPS32: srl [[T1]],[[BV_E0]],0x8
4376 ; MIPS32: andi [[T1]],[[T1]],0xff
4377 ; MIPS32: andi [[T1]],[[T1]],0x1
4378 ; MIPS32: sll [[T2]],[[T2]],0x1f
4379 ; MIPS32: sll [[T1]],[[T1]],0x1f
4380 ; MIPS32: xor [[T2]],[[T2]],[[T1]]
4381 ; MIPS32: sltiu [[T2]],[[T2]],1
4382 ; MIPS32: andi [[T2]],[[T2]],0xff
4383 ; MIPS32: sll [[T2]],[[T2]],0x8
4384 ; MIPS32: lui [[T1]],0xffff
4385 ; MIPS32: ori [[T1]],[[T1]],0xff
4386 ; MIPS32: and [[T0]],[[T0]],[[T1]]
4387 ; MIPS32: or [[T2]],[[T2]],[[T0]]
4388 ; MIPS32: srl [[T0]],a0,0x10
4389 ; MIPS32: andi [[T0]],[[T0]],0xff
4390 ; MIPS32: andi [[T0]],[[T0]],0x1
4391 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
4392 ; MIPS32: andi [[T1]],[[T1]],0xff
4393 ; MIPS32: andi [[T1]],[[T1]],0x1
4394 ; MIPS32: sll [[T0]],[[T0]],0x1f
4395 ; MIPS32: sll [[T1]],[[T1]],0x1f
4396 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
4397 ; MIPS32: sltiu [[T0]],[[T0]],1
4398 ; MIPS32: andi [[T0]],[[T0]],0xff
4399 ; MIPS32: sll [[T0]],[[T0]],0x10
4400 ; MIPS32: lui [[T1]],0xff00
4401 ; MIPS32: ori [[T1]],[[T1]],0xffff
4402 ; MIPS32: and [[T2]],[[T2]],[[T1]]
4403 ; MIPS32: or [[T0]],[[T0]],[[T2]]
4404 ; MIPS32: srl [[T3:.*]],a0,0x18
4405 ; MIPS32: andi [[T3]],[[T3]],0x1
4406 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
4407 ; MIPS32: andi [[T4]],[[T4]],0x1
4408 ; MIPS32: sll [[T3]],[[T3]],0x1f
4409 ; MIPS32: sll [[T4]],[[T4]],0x1f
4410 ; MIPS32: xor [[T3]],[[T3]],[[T4]]
4411 ; MIPS32: sltiu [[T3]],[[T3]],1
4412 ; MIPS32: srl [[T3]],[[T3]],0x18
4413 ; MIPS32: sll [[T0]],[[T0]],0x8
4414 ; MIPS32: srl [[T0]],[[T0]],0x8
4415 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
4416 ; MIPS32: andi [[T4]],a1,0xff
4417 ; MIPS32: andi [[T4]],[[T4]],0x1
4418 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
4419 ; MIPS32: andi [[T2]],[[T2]],0x1
4420 ; MIPS32: sll [[T4]],[[T4]],0x1f
4421 ; MIPS32: sll [[T2]],[[T2]],0x1f
4422 ; MIPS32: xor [[T4]],[[T4]],[[T2]]
4423 ; MIPS32: sltiu [[T4]],[[T4]],1
4424 ; MIPS32: andi [[T4]],[[T4]],0xff
4425 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
4426 ; MIPS32: sll [[T5]],[[T5]],0x8
4427 ; MIPS32: or [[T4]],[[T4]],[[T5]]
4428 ; MIPS32: srl [[T2]],a1,0x8
4429 ; MIPS32: andi [[T2]],[[T2]],0xff
4430 ; MIPS32: andi [[T2]],[[T2]],0x1
4431 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
4432 ; MIPS32: andi [[T5]],[[T5]],0xff
4433 ; MIPS32: andi [[T5]],[[T5]],0x1
4434 ; MIPS32: sll [[T2]],[[T2]],0x1f
4435 ; MIPS32: sll [[T5]],[[T5]],0x1f
4436 ; MIPS32: xor [[T2]],[[T2]],[[T5]]
4437 ; MIPS32: sltiu [[T2]],[[T2]],1
4438 ; MIPS32: andi [[T2]],[[T2]],0xff
4439 ; MIPS32: sll [[T2]],[[T2]],0x8
4440 ; MIPS32: lui [[T5]],0xffff
4441 ; MIPS32: ori [[T5]],[[T5]],0xff
4442 ; MIPS32: and [[T4]],[[T4]],[[T5]]
4443 ; MIPS32: or [[T2]],[[T2]],[[T4]]
4444 ; MIPS32: srl [[T4]],a1,0x10
4445 ; MIPS32: andi [[T4]],[[T4]],0xff
4446 ; MIPS32: andi [[T4]],[[T4]],0x1
4447 ; MIPS32: srl [[T5]],[[BV_E1]],0x10
4448 ; MIPS32: andi [[T5]],[[T5]],0xff
4449 ; MIPS32: andi [[T5]],[[T5]],0x1
4450 ; MIPS32: sll [[T4]],[[T4]],0x1f
4451 ; MIPS32: sll [[T5]],[[T5]],0x1f
4452 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
4453 ; MIPS32: sltiu [[T4]],[[T4]],1
4454 ; MIPS32: andi [[T4]],[[T4]],0xff
4455 ; MIPS32: sll [[T4]],[[T4]],0x10
4456 ; MIPS32: lui [[T5]],0xff00
4457 ; MIPS32: ori [[T5]],[[T5]],0xffff
4458 ; MIPS32: and [[T2]],[[T2]],[[T5]]
4459 ; MIPS32: or [[T4]],[[T4]],[[T2]]
4460 ; MIPS32: srl [[T6:.*]],a1,0x18
4461 ; MIPS32: andi [[T6]],[[T6]],0x1
4462 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
4463 ; MIPS32: andi [[T7]],[[T7]],0x1
4464 ; MIPS32: sll [[T6]],[[T6]],0x1f
4465 ; MIPS32: sll [[T7]],[[T7]],0x1f
4466 ; MIPS32: xor [[T6]],[[T6]],[[T7]]
4467 ; MIPS32: sltiu [[T6]],[[T6]],1
4468 ; MIPS32: srl [[T6]],[[T6]],0x18
4469 ; MIPS32: sll [[T4]],[[T4]],0x8
4470 ; MIPS32: srl [[T4]],[[T4]],0x8
4471 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
4472 ; MIPS32: andi [[T4]],a2,0xff
4473 ; MIPS32: andi [[T4]],[[T4]],0x1
4474 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
4475 ; MIPS32: andi [[T7]],[[T7]],0x1
4476 ; MIPS32: sll [[T4]],[[T4]],0x1f
4477 ; MIPS32: sll [[T7]],[[T7]],0x1f
4478 ; MIPS32: xor [[T4]],[[T4]],[[T7]]
4479 ; MIPS32: sltiu [[T4]],[[T4]],1
4480 ; MIPS32: andi [[T4]],[[T4]],0xff
4481 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
4482 ; MIPS32: sll [[T8]],[[T8]],0x8
4483 ; MIPS32: or [[T4]],[[T4]],[[T8]]
4484 ; MIPS32: srl [[T7]],a2,0x8
4485 ; MIPS32: andi [[T7]],[[T7]],0xff
4486 ; MIPS32: andi [[T7]],[[T7]],0x1
4487 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
4488 ; MIPS32: andi [[T2]],[[T2]],0xff
4489 ; MIPS32: andi [[T2]],[[T2]],0x1
4490 ; MIPS32: sll [[T7]],[[T7]],0x1f
4491 ; MIPS32: sll [[T2]],[[T2]],0x1f
4492 ; MIPS32: xor [[T7]],[[T7]],[[T2]]
4493 ; MIPS32: sltiu [[T7]],[[T7]],1
4494 ; MIPS32: andi [[T7]],[[T7]],0xff
4495 ; MIPS32: sll [[T7]],[[T7]],0x8
4496 ; MIPS32: lui [[T2]],0xffff
4497 ; MIPS32: ori [[T2]],[[T2]],0xff
4498 ; MIPS32: and [[T4]],[[T4]],[[T2]]
4499 ; MIPS32: or [[T7]],[[T7]],[[T4]]
4500 ; MIPS32: srl [[T4]],a2,0x10
4501 ; MIPS32: andi [[T4]],[[T4]],0xff
4502 ; MIPS32: andi [[T4]],[[T4]],0x1
4503 ; MIPS32: srl [[T2]],[[BV_E2]],0x10
4504 ; MIPS32: andi [[T2]],[[T2]],0xff
4505 ; MIPS32: andi [[T2]],[[T2]],0x1
4506 ; MIPS32: sll [[T4]],[[T4]],0x1f
4507 ; MIPS32: sll [[T2]],[[T2]],0x1f
4508 ; MIPS32: xor [[T4]],[[T4]],[[T2]]
4509 ; MIPS32: sltiu [[T4]],[[T4]],1
4510 ; MIPS32: andi [[T4]],[[T4]],0xff
4511 ; MIPS32: sll [[T4]],[[T4]],0x10
4512 ; MIPS32: lui [[T2]],0xff00
4513 ; MIPS32: ori [[T2]],[[T2]],0xffff
4514 ; MIPS32: and [[T7]],[[T7]],[[T2]]
4515 ; MIPS32: or [[T4]],[[T4]],[[T7]]
4516 ; MIPS32: srl [[T9:.*]],a2,0x18
4517 ; MIPS32: andi [[T9]],[[T9]],0x1
4518 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
4519 ; MIPS32: andi [[T10]],[[T10]],0x1
4520 ; MIPS32: sll [[T9]],[[T9]],0x1f
4521 ; MIPS32: sll [[T10]],[[T10]],0x1f
4522 ; MIPS32: xor [[T9]],[[T9]],[[T10]]
4523 ; MIPS32: sltiu [[T9]],[[T9]],1
4524 ; MIPS32: srl [[T9]],[[T9]],0x18
4525 ; MIPS32: sll [[T4]],[[T4]],0x8
4526 ; MIPS32: srl [[T4]],[[T4]],0x8
4527 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
4528 ; MIPS32: andi [[T4]],a3,0xff
4529 ; MIPS32: andi [[T4]],[[T4]],0x1
4530 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
4531 ; MIPS32: andi [[T7]],[[T7]],0x1
4532 ; MIPS32: sll [[T4]],[[T4]],0x1f
4533 ; MIPS32: sll [[T7]],[[T7]],0x1f
4534 ; MIPS32: xor [[T4]],[[T4]],[[T7]]
4535 ; MIPS32: sltiu [[T4]],[[T4]],1
4536 ; MIPS32: andi [[T4]],[[T4]],0xff
4537 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
4538 ; MIPS32: sll [[T11]],[[T11]],0x8
4539 ; MIPS32: or [[T4]],[[T4]],[[T11]]
4540 ; MIPS32: srl [[T7]],a3,0x8
4541 ; MIPS32: andi [[T7]],[[T7]],0xff
4542 ; MIPS32: andi [[T7]],[[T7]],0x1
4543 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
4544 ; MIPS32: andi [[T10]],[[T10]],0xff
4545 ; MIPS32: andi [[T10]],[[T10]],0x1
4546 ; MIPS32: sll [[T7]],[[T7]],0x1f
4547 ; MIPS32: sll [[T10]],[[T10]],0x1f
4548 ; MIPS32: xor [[T7]],[[T7]],[[T10]]
4549 ; MIPS32: sltiu [[T7]],[[T7]],1
4550 ; MIPS32: andi [[T7]],[[T7]],0xff
4551 ; MIPS32: sll [[T7]],[[T7]],0x8
4552 ; MIPS32: lui [[T10]],0xffff
4553 ; MIPS32: ori [[T10]],[[T10]],0xff
4554 ; MIPS32: and [[T4]],[[T4]],[[T10]]
4555 ; MIPS32: or [[T7]],[[T7]],[[T4]]
4556 ; MIPS32: srl [[T4]],a3,0x10
4557 ; MIPS32: andi [[T4]],[[T4]],0xff
4558 ; MIPS32: andi [[T4]],[[T4]],0x1
4559 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
4560 ; MIPS32: andi [[T10]],[[T10]],0xff
4561 ; MIPS32: andi [[T10]],[[T10]],0x1
4562 ; MIPS32: sll [[T4]],[[T4]],0x1f
4563 ; MIPS32: sll [[T10]],[[T10]],0x1f
4564 ; MIPS32: xor [[T4]],[[T4]],[[T10]]
4565 ; MIPS32: sltiu [[T4]],[[T4]],1
4566 ; MIPS32: andi [[T4]],[[T4]],0xff
4567 ; MIPS32: sll [[T4]],[[T4]],0x10
4568 ; MIPS32: lui [[T10]],0xff00
4569 ; MIPS32: ori [[T10]],[[T10]],0xffff
4570 ; MIPS32: and [[T7]],[[T7]],[[T10]]
4571 ; MIPS32: or [[T4]],[[T4]],[[T7]]
4572 ; MIPS32: srl [[T12:.*]],a3,0x18
4573 ; MIPS32: andi [[T12]],[[T12]],0x1
4574 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
4575 ; MIPS32: andi [[T13]],[[T13]],0x1
4576 ; MIPS32: sll [[T12]],[[T12]],0x1f
4577 ; MIPS32: sll [[T13]],[[T13]],0x1f
4578 ; MIPS32: xor [[T12]],[[T12]],[[T13]]
4579 ; MIPS32: sltiu [[T12]],[[T12]],1
4580 ; MIPS32: srl [[T12]],[[T12]],0x18
4581 ; MIPS32: sll [[T4]],[[T4]],0x8
4582 ; MIPS32: srl [[T4]],[[T4]],0x8
4583 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
425 } 4584 }
426 4585
427 define internal <16 x i1> @test_icmp_v16i1_ne(<16 x i1> %a, <16 x i1> %b) { 4586 define internal <16 x i1> @test_icmp_v16i1_ne(<16 x i1> %a, <16 x i1> %b) {
428 entry: 4587 entry:
429 %res = icmp ne <16 x i1> %a, %b 4588 %res = icmp ne <16 x i1> %a, %b
430 ret <16 x i1> %res 4589 ret <16 x i1> %res
431 ; CHECK-LABEL: test_icmp_v16i1_ne 4590 ; CHECK-LABEL: test_icmp_v16i1_ne
432 ; CHECK: pcmpeqb 4591 ; CHECK: pcmpeqb
433 ; CHECK: pxor 4592 ; CHECK: pxor
4593
4594 ; MIPS32-LABEL: test_icmp_v16i1_ne
4595 ; MIPS32: lw [[BV_E0:.*]],
4596 ; MIPS32: lw [[BV_E1:.*]],
4597 ; MIPS32: lw [[BV_E2:.*]],
4598 ; MIPS32: lw [[BV_E3:.*]],
4599 ; MIPS32: move [[TV_E0:.*]],zero
4600 ; MIPS32: move [[TV_E1:.*]],zero
4601 ; MIPS32: move [[TV_E2:.*]],zero
4602 ; MIPS32: move [[TV_E3:.*]],zero
4603 ; MIPS32: andi [[T0:.*]],a0,0xff
4604 ; MIPS32: andi [[T0]],[[T0]],0x1
4605 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
4606 ; MIPS32: andi [[T1]],[[T1]],0x1
4607 ; MIPS32: sll [[T0]],[[T0]],0x1f
4608 ; MIPS32: sll [[T1]],[[T1]],0x1f
4609 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
4610 ; MIPS32: sltu [[T0]],zero,[[T0]]
4611 ; MIPS32: andi [[T0]],[[T0]],0xff
4612 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
4613 ; MIPS32: sll [[T2]],[[T2]],0x8
4614 ; MIPS32: or [[T0]],[[T0]],[[T2]]
4615 ; MIPS32: srl [[T2]],a0,0x8
4616 ; MIPS32: andi [[T2]],[[T2]],0xff
4617 ; MIPS32: andi [[T2]],[[T2]],0x1
4618 ; MIPS32: srl [[T1]],[[BV_E0]],0x8
4619 ; MIPS32: andi [[T1]],[[T1]],0xff
4620 ; MIPS32: andi [[T1]],[[T1]],0x1
4621 ; MIPS32: sll [[T2]],[[T2]],0x1f
4622 ; MIPS32: sll [[T1]],[[T1]],0x1f
4623 ; MIPS32: xor [[T2]],[[T2]],[[T1]]
4624 ; MIPS32: sltu [[T2]],zero,[[T2]]
4625 ; MIPS32: andi [[T2]],[[T2]],0xff
4626 ; MIPS32: sll [[T2]],[[T2]],0x8
4627 ; MIPS32: lui [[T1]],0xffff
4628 ; MIPS32: ori [[T1]],[[T1]],0xff
4629 ; MIPS32: and [[T0]],[[T0]],[[T1]]
4630 ; MIPS32: or [[T2]],[[T2]],[[T0]]
4631 ; MIPS32: srl [[T0]],a0,0x10
4632 ; MIPS32: andi [[T0]],[[T0]],0xff
4633 ; MIPS32: andi [[T0]],[[T0]],0x1
4634 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
4635 ; MIPS32: andi [[T1]],[[T1]],0xff
4636 ; MIPS32: andi [[T1]],[[T1]],0x1
4637 ; MIPS32: sll [[T0]],[[T0]],0x1f
4638 ; MIPS32: sll [[T1]],[[T1]],0x1f
4639 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
4640 ; MIPS32: sltu [[T0]],zero,[[T0]]
4641 ; MIPS32: andi [[T0]],[[T0]],0xff
4642 ; MIPS32: sll [[T0]],[[T0]],0x10
4643 ; MIPS32: lui [[T1]],0xff00
4644 ; MIPS32: ori [[T1]],[[T1]],0xffff
4645 ; MIPS32: and [[T2]],[[T2]],[[T1]]
4646 ; MIPS32: or [[T0]],[[T0]],[[T2]]
4647 ; MIPS32: srl [[T3:.*]],a0,0x18
4648 ; MIPS32: andi [[T3]],[[T3]],0x1
4649 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
4650 ; MIPS32: andi [[T4]],[[T4]],0x1
4651 ; MIPS32: sll [[T3]],[[T3]],0x1f
4652 ; MIPS32: sll [[T4]],[[T4]],0x1f
4653 ; MIPS32: xor [[T3]],[[T3]],[[T4]]
4654 ; MIPS32: sltu [[T3]],zero,[[T3]]
4655 ; MIPS32: srl [[T3]],[[T3]],0x18
4656 ; MIPS32: sll [[T0]],[[T0]],0x8
4657 ; MIPS32: srl [[T0]],[[T0]],0x8
4658 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
4659 ; MIPS32: andi [[T4]],a1,0xff
4660 ; MIPS32: andi [[T4]],[[T4]],0x1
4661 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
4662 ; MIPS32: andi [[T2]],[[T2]],0x1
4663 ; MIPS32: sll [[T4]],[[T4]],0x1f
4664 ; MIPS32: sll [[T2]],[[T2]],0x1f
4665 ; MIPS32: xor [[T4]],[[T4]],[[T2]]
4666 ; MIPS32: sltu [[T4]],zero,[[T4]]
4667 ; MIPS32: andi [[T4]],[[T4]],0xff
4668 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
4669 ; MIPS32: sll [[T5]],[[T5]],0x8
4670 ; MIPS32: or [[T4]],[[T4]],[[T5]]
4671 ; MIPS32: srl [[T2]],a1,0x8
4672 ; MIPS32: andi [[T2]],[[T2]],0xff
4673 ; MIPS32: andi [[T2]],[[T2]],0x1
4674 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
4675 ; MIPS32: andi [[T5]],[[T5]],0xff
4676 ; MIPS32: andi [[T5]],[[T5]],0x1
4677 ; MIPS32: sll [[T2]],[[T2]],0x1f
4678 ; MIPS32: sll [[T5]],[[T5]],0x1f
4679 ; MIPS32: xor [[T2]],[[T2]],[[T5]]
4680 ; MIPS32: sltu [[T2]],zero,[[T2]]
4681 ; MIPS32: andi [[T2]],[[T2]],0xff
4682 ; MIPS32: sll [[T2]],[[T2]],0x8
4683 ; MIPS32: lui [[T5]],0xffff
4684 ; MIPS32: ori [[T5]],[[T5]],0xff
4685 ; MIPS32: and [[T4]],[[T4]],[[T5]]
4686 ; MIPS32: or [[T2]],[[T2]],[[T4]]
4687 ; MIPS32: srl [[T4]],a1,0x10
4688 ; MIPS32: andi [[T4]],[[T4]],0xff
4689 ; MIPS32: andi [[T4]],[[T4]],0x1
4690 ; MIPS32: srl [[T5]],[[BV_E1]],0x10
4691 ; MIPS32: andi [[T5]],[[T5]],0xff
4692 ; MIPS32: andi [[T5]],[[T5]],0x1
4693 ; MIPS32: sll [[T4]],[[T4]],0x1f
4694 ; MIPS32: sll [[T5]],[[T5]],0x1f
4695 ; MIPS32: xor [[T4]],[[T4]],[[T5]]
4696 ; MIPS32: sltu [[T4]],zero,[[T4]]
4697 ; MIPS32: andi [[T4]],[[T4]],0xff
4698 ; MIPS32: sll [[T4]],[[T4]],0x10
4699 ; MIPS32: lui [[T5]],0xff00
4700 ; MIPS32: ori [[T5]],[[T5]],0xffff
4701 ; MIPS32: and [[T2]],[[T2]],[[T5]]
4702 ; MIPS32: or [[T4]],[[T4]],[[T2]]
4703 ; MIPS32: srl [[T6:.*]],a1,0x18
4704 ; MIPS32: andi [[T6]],[[T6]],0x1
4705 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
4706 ; MIPS32: andi [[T7]],[[T7]],0x1
4707 ; MIPS32: sll [[T6]],[[T6]],0x1f
4708 ; MIPS32: sll [[T7]],[[T7]],0x1f
4709 ; MIPS32: xor [[T6]],[[T6]],[[T7]]
4710 ; MIPS32: sltu [[T6]],zero,[[T6]]
4711 ; MIPS32: srl [[T6]],[[T6]],0x18
4712 ; MIPS32: sll [[T4]],[[T4]],0x8
4713 ; MIPS32: srl [[T4]],[[T4]],0x8
4714 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
4715 ; MIPS32: andi [[T4]],a2,0xff
4716 ; MIPS32: andi [[T4]],[[T4]],0x1
4717 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
4718 ; MIPS32: andi [[T7]],[[T7]],0x1
4719 ; MIPS32: sll [[T4]],[[T4]],0x1f
4720 ; MIPS32: sll [[T7]],[[T7]],0x1f
4721 ; MIPS32: xor [[T4]],[[T4]],[[T7]]
4722 ; MIPS32: sltu [[T4]],zero,[[T4]]
4723 ; MIPS32: andi [[T4]],[[T4]],0xff
4724 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
4725 ; MIPS32: sll [[T8]],[[T8]],0x8
4726 ; MIPS32: or [[T4]],[[T4]],[[T8]]
4727 ; MIPS32: srl [[T7]],a2,0x8
4728 ; MIPS32: andi [[T7]],[[T7]],0xff
4729 ; MIPS32: andi [[T7]],[[T7]],0x1
4730 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
4731 ; MIPS32: andi [[T2]],[[T2]],0xff
4732 ; MIPS32: andi [[T2]],[[T2]],0x1
4733 ; MIPS32: sll [[T7]],[[T7]],0x1f
4734 ; MIPS32: sll [[T2]],[[T2]],0x1f
4735 ; MIPS32: xor [[T7]],[[T7]],[[T2]]
4736 ; MIPS32: sltu [[T7]],zero,[[T7]]
4737 ; MIPS32: andi [[T7]],[[T7]],0xff
4738 ; MIPS32: sll [[T7]],[[T7]],0x8
4739 ; MIPS32: lui [[T2]],0xffff
4740 ; MIPS32: ori [[T2]],[[T2]],0xff
4741 ; MIPS32: and [[T4]],[[T4]],[[T2]]
4742 ; MIPS32: or [[T7]],[[T7]],[[T4]]
4743 ; MIPS32: srl [[T4]],a2,0x10
4744 ; MIPS32: andi [[T4]],[[T4]],0xff
4745 ; MIPS32: andi [[T4]],[[T4]],0x1
4746 ; MIPS32: srl [[T2]],[[BV_E2]],0x10
4747 ; MIPS32: andi [[T2]],[[T2]],0xff
4748 ; MIPS32: andi [[T2]],[[T2]],0x1
4749 ; MIPS32: sll [[T4]],[[T4]],0x1f
4750 ; MIPS32: sll [[T2]],[[T2]],0x1f
4751 ; MIPS32: xor [[T4]],[[T4]],[[T2]]
4752 ; MIPS32: sltu [[T4]],zero,[[T4]]
4753 ; MIPS32: andi [[T4]],[[T4]],0xff
4754 ; MIPS32: sll [[T4]],[[T4]],0x10
4755 ; MIPS32: lui [[T2]],0xff00
4756 ; MIPS32: ori [[T2]],[[T2]],0xffff
4757 ; MIPS32: and [[T7]],[[T7]],[[T2]]
4758 ; MIPS32: or [[T4]],[[T4]],[[T7]]
4759 ; MIPS32: srl [[T9:.*]],a2,0x18
4760 ; MIPS32: andi [[T9]],[[T9]],0x1
4761 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
4762 ; MIPS32: andi [[T10]],[[T10]],0x1
4763 ; MIPS32: sll [[T9]],[[T9]],0x1f
4764 ; MIPS32: sll [[T10]],[[T10]],0x1f
4765 ; MIPS32: xor [[T9]],[[T9]],[[T10]]
4766 ; MIPS32: sltu [[T9]],zero,[[T9]]
4767 ; MIPS32: srl [[T9]],[[T9]],0x18
4768 ; MIPS32: sll [[T4]],[[T4]],0x8
4769 ; MIPS32: srl [[T4]],[[T4]],0x8
4770 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
4771 ; MIPS32: andi [[T4]],a3,0xff
4772 ; MIPS32: andi [[T4]],[[T4]],0x1
4773 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
4774 ; MIPS32: andi [[T7]],[[T7]],0x1
4775 ; MIPS32: sll [[T4]],[[T4]],0x1f
4776 ; MIPS32: sll [[T7]],[[T7]],0x1f
4777 ; MIPS32: xor [[T4]],[[T4]],[[T7]]
4778 ; MIPS32: sltu [[T4]],zero,[[T4]]
4779 ; MIPS32: andi [[T4]],[[T4]],0xff
4780 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
4781 ; MIPS32: sll [[T11]],[[T11]],0x8
4782 ; MIPS32: or [[T4]],[[T4]],[[T11]]
4783 ; MIPS32: srl [[T7]],a3,0x8
4784 ; MIPS32: andi [[T7]],[[T7]],0xff
4785 ; MIPS32: andi [[T7]],[[T7]],0x1
4786 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
4787 ; MIPS32: andi [[T10]],[[T10]],0xff
4788 ; MIPS32: andi [[T10]],[[T10]],0x1
4789 ; MIPS32: sll [[T7]],[[T7]],0x1f
4790 ; MIPS32: sll [[T10]],[[T10]],0x1f
4791 ; MIPS32: xor [[T7]],[[T7]],[[T10]]
4792 ; MIPS32: sltu [[T7]],zero,[[T7]]
4793 ; MIPS32: andi [[T7]],[[T7]],0xff
4794 ; MIPS32: sll [[T7]],[[T7]],0x8
4795 ; MIPS32: lui [[T10]],0xffff
4796 ; MIPS32: ori [[T10]],[[T10]],0xff
4797 ; MIPS32: and [[T4]],[[T4]],[[T10]]
4798 ; MIPS32: or [[T7]],[[T7]],[[T4]]
4799 ; MIPS32: srl [[T4]],a3,0x10
4800 ; MIPS32: andi [[T4]],[[T4]],0xff
4801 ; MIPS32: andi [[T4]],[[T4]],0x1
4802 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
4803 ; MIPS32: andi [[T10]],[[T10]],0xff
4804 ; MIPS32: andi [[T10]],[[T10]],0x1
4805 ; MIPS32: sll [[T4]],[[T4]],0x1f
4806 ; MIPS32: sll [[T10]],[[T10]],0x1f
4807 ; MIPS32: xor [[T4]],[[T4]],[[T10]]
4808 ; MIPS32: sltu [[T4]],zero,[[T4]]
4809 ; MIPS32: andi [[T4]],[[T4]],0xff
4810 ; MIPS32: sll [[T4]],[[T4]],0x10
4811 ; MIPS32: lui [[T10]],0xff00
4812 ; MIPS32: ori [[T10]],[[T10]],0xffff
4813 ; MIPS32: and [[T7]],[[T7]],[[T10]]
4814 ; MIPS32: or [[T4]],[[T4]],[[T7]]
4815 ; MIPS32: srl [[T12:.*]],a3,0x18
4816 ; MIPS32: andi [[T12]],[[T12]],0x1
4817 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
4818 ; MIPS32: andi [[T13]],[[T13]],0x1
4819 ; MIPS32: sll [[T12]],[[T12]],0x1f
4820 ; MIPS32: sll [[T13]],[[T13]],0x1f
4821 ; MIPS32: xor [[T12]],[[T12]],[[T13]]
4822 ; MIPS32: sltu [[T12]],zero,[[T12]]
4823 ; MIPS32: srl [[T12]],[[T12]],0x18
4824 ; MIPS32: sll [[T4]],[[T4]],0x8
4825 ; MIPS32: srl [[T4]],[[T4]],0x8
4826 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
434 } 4827 }
435 4828
436 define internal <16 x i1> @test_icmp_v16i1_sgt(<16 x i1> %a, <16 x i1> %b) { 4829 define internal <16 x i1> @test_icmp_v16i1_sgt(<16 x i1> %a, <16 x i1> %b) {
437 entry: 4830 entry:
438 %res = icmp sgt <16 x i1> %a, %b 4831 %res = icmp sgt <16 x i1> %a, %b
439 ret <16 x i1> %res 4832 ret <16 x i1> %res
440 ; CHECK-LABEL: test_icmp_v16i1_sgt 4833 ; CHECK-LABEL: test_icmp_v16i1_sgt
441 ; CHECK: pcmpgtb 4834 ; CHECK: pcmpgtb
4835
4836 ; MIPS32-LABEL: test_icmp_v16i1_sgt
4837 ; MIPS32: lw [[BV_E0:.*]],
4838 ; MIPS32: lw [[BV_E1:.*]],
4839 ; MIPS32: lw [[BV_E2:.*]],
4840 ; MIPS32: lw [[BV_E3:.*]],
4841 ; MIPS32: move [[TV_E0:.*]],zero
4842 ; MIPS32: move [[TV_E1:.*]],zero
4843 ; MIPS32: move [[TV_E2:.*]],zero
4844 ; MIPS32: move [[TV_E3:.*]],zero
4845 ; MIPS32: andi [[T0:.*]],a0,0xff
4846 ; MIPS32: andi [[T0]],[[T0]],0x1
4847 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
4848 ; MIPS32: andi [[T1]],[[T1]],0x1
4849 ; MIPS32: sll [[T0]],[[T0]],0x1f
4850 ; MIPS32: sll [[T1]],[[T1]],0x1f
4851 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
4852 ; MIPS32: andi [[T1]],[[T1]],0xff
4853 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
4854 ; MIPS32: sll [[T2]],[[T2]],0x8
4855 ; MIPS32: or [[T1]],[[T1]],[[T2]]
4856 ; MIPS32: srl [[T2]],a0,0x8
4857 ; MIPS32: andi [[T2]],[[T2]],0xff
4858 ; MIPS32: andi [[T2]],[[T2]],0x1
4859 ; MIPS32: srl [[T0]],[[BV_E0]],0x8
4860 ; MIPS32: andi [[T0]],[[T0]],0xff
4861 ; MIPS32: andi [[T0]],[[T0]],0x1
4862 ; MIPS32: sll [[T2]],[[T2]],0x1f
4863 ; MIPS32: sll [[T0]],[[T0]],0x1f
4864 ; MIPS32: slt [[T0]],[[T0]],[[T2]]
4865 ; MIPS32: andi [[T0]],[[T0]],0xff
4866 ; MIPS32: sll [[T0]],[[T0]],0x8
4867 ; MIPS32: lui [[T2]],0xffff
4868 ; MIPS32: ori [[T2]],[[T2]],0xff
4869 ; MIPS32: and [[T1]],[[T1]],[[T2]]
4870 ; MIPS32: or [[T0]],[[T0]],[[T1]]
4871 ; MIPS32: srl [[T2]],a0,0x10
4872 ; MIPS32: andi [[T2]],[[T2]],0xff
4873 ; MIPS32: andi [[T2]],[[T2]],0x1
4874 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
4875 ; MIPS32: andi [[T1]],[[T1]],0xff
4876 ; MIPS32: andi [[T1]],[[T1]],0x1
4877 ; MIPS32: sll [[T2]],[[T2]],0x1f
4878 ; MIPS32: sll [[T1]],[[T1]],0x1f
4879 ; MIPS32: slt [[T1]],[[T1]],[[T2]]
4880 ; MIPS32: andi [[T1]],[[T1]],0xff
4881 ; MIPS32: sll [[T1]],[[T1]],0x10
4882 ; MIPS32: lui [[T2]],0xff00
4883 ; MIPS32: ori [[T2]],[[T2]],0xffff
4884 ; MIPS32: and [[T0]],[[T0]],[[T2]]
4885 ; MIPS32: or [[T1]],[[T1]],[[T0]]
4886 ; MIPS32: srl [[T3:.*]],a0,0x18
4887 ; MIPS32: andi [[T3]],[[T3]],0x1
4888 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
4889 ; MIPS32: andi [[T4]],[[T4]],0x1
4890 ; MIPS32: sll [[T3]],[[T3]],0x1f
4891 ; MIPS32: sll [[T4]],[[T4]],0x1f
4892 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
4893 ; MIPS32: srl [[T4]],[[T4]],0x18
4894 ; MIPS32: sll [[T1]],[[T1]],0x8
4895 ; MIPS32: srl [[T1]],[[T1]],0x8
4896 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
4897 ; MIPS32: andi [[T3]],a1,0xff
4898 ; MIPS32: andi [[T3]],[[T3]],0x1
4899 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
4900 ; MIPS32: andi [[T2]],[[T2]],0x1
4901 ; MIPS32: sll [[T3]],[[T3]],0x1f
4902 ; MIPS32: sll [[T2]],[[T2]],0x1f
4903 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
4904 ; MIPS32: andi [[T2]],[[T2]],0xff
4905 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
4906 ; MIPS32: sll [[T5]],[[T5]],0x8
4907 ; MIPS32: or [[T2]],[[T2]],[[T5]]
4908 ; MIPS32: srl [[T3]],a1,0x8
4909 ; MIPS32: andi [[T3]],[[T3]],0xff
4910 ; MIPS32: andi [[T3]],[[T3]],0x1
4911 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
4912 ; MIPS32: andi [[T5]],[[T5]],0xff
4913 ; MIPS32: andi [[T5]],[[T5]],0x1
4914 ; MIPS32: sll [[T3]],[[T3]],0x1f
4915 ; MIPS32: sll [[T5]],[[T5]],0x1f
4916 ; MIPS32: slt [[T5]],[[T5]],[[T3]]
4917 ; MIPS32: andi [[T5]],[[T5]],0xff
4918 ; MIPS32: sll [[T5]],[[T5]],0x8
4919 ; MIPS32: lui [[T3]],0xffff
4920 ; MIPS32: ori [[T3]],[[T3]],0xff
4921 ; MIPS32: and [[T2]],[[T2]],[[T3]]
4922 ; MIPS32: or [[T5]],[[T5]],[[T2]]
4923 ; MIPS32: srl [[T3]],a1,0x10
4924 ; MIPS32: andi [[T3]],[[T3]],0xff
4925 ; MIPS32: andi [[T3]],[[T3]],0x1
4926 ; MIPS32: srl [[T2]],[[BV_E1]],0x10
4927 ; MIPS32: andi [[T2]],[[T2]],0xff
4928 ; MIPS32: andi [[T2]],[[T2]],0x1
4929 ; MIPS32: sll [[T3]],[[T3]],0x1f
4930 ; MIPS32: sll [[T2]],[[T2]],0x1f
4931 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
4932 ; MIPS32: andi [[T2]],[[T2]],0xff
4933 ; MIPS32: sll [[T2]],[[T2]],0x10
4934 ; MIPS32: lui [[T3]],0xff00
4935 ; MIPS32: ori [[T3]],[[T3]],0xffff
4936 ; MIPS32: and [[T5]],[[T5]],[[T3]]
4937 ; MIPS32: or [[T2]],[[T2]],[[T5]]
4938 ; MIPS32: srl [[T6:.*]],a1,0x18
4939 ; MIPS32: andi [[T6]],[[T6]],0x1
4940 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
4941 ; MIPS32: andi [[T7]],[[T7]],0x1
4942 ; MIPS32: sll [[T6]],[[T6]],0x1f
4943 ; MIPS32: sll [[T7]],[[T7]],0x1f
4944 ; MIPS32: slt [[T7]],[[T7]],[[T6]]
4945 ; MIPS32: srl [[T7]],[[T7]],0x18
4946 ; MIPS32: sll [[T2]],[[T2]],0x8
4947 ; MIPS32: srl [[T2]],[[T2]],0x8
4948 ; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
4949 ; MIPS32: andi [[T3]],a2,0xff
4950 ; MIPS32: andi [[T3]],[[T3]],0x1
4951 ; MIPS32: andi [[T6]],[[BV_E2]],0xff
4952 ; MIPS32: andi [[T6]],[[T6]],0x1
4953 ; MIPS32: sll [[T3]],[[T3]],0x1f
4954 ; MIPS32: sll [[T6]],[[T6]],0x1f
4955 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
4956 ; MIPS32: andi [[T6]],[[T6]],0xff
4957 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
4958 ; MIPS32: sll [[T8]],[[T8]],0x8
4959 ; MIPS32: or [[T6]],[[T6]],[[T8]]
4960 ; MIPS32: srl [[T3]],a2,0x8
4961 ; MIPS32: andi [[T3]],[[T3]],0xff
4962 ; MIPS32: andi [[T3]],[[T3]],0x1
4963 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
4964 ; MIPS32: andi [[T2]],[[T2]],0xff
4965 ; MIPS32: andi [[T2]],[[T2]],0x1
4966 ; MIPS32: sll [[T3]],[[T3]],0x1f
4967 ; MIPS32: sll [[T2]],[[T2]],0x1f
4968 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
4969 ; MIPS32: andi [[T2]],[[T2]],0xff
4970 ; MIPS32: sll [[T2]],[[T2]],0x8
4971 ; MIPS32: lui [[T3]],0xffff
4972 ; MIPS32: ori [[T3]],[[T3]],0xff
4973 ; MIPS32: and [[T6]],[[T6]],[[T3]]
4974 ; MIPS32: or [[T2]],[[T2]],[[T6]]
4975 ; MIPS32: srl [[T3]],a2,0x10
4976 ; MIPS32: andi [[T3]],[[T3]],0xff
4977 ; MIPS32: andi [[T3]],[[T3]],0x1
4978 ; MIPS32: srl [[T6]],[[BV_E2]],0x10
4979 ; MIPS32: andi [[T6]],[[T6]],0xff
4980 ; MIPS32: andi [[T6]],[[T6]],0x1
4981 ; MIPS32: sll [[T3]],[[T3]],0x1f
4982 ; MIPS32: sll [[T6]],[[T6]],0x1f
4983 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
4984 ; MIPS32: andi [[T6]],[[T6]],0xff
4985 ; MIPS32: sll [[T6]],[[T6]],0x10
4986 ; MIPS32: lui [[T3]],0xff00
4987 ; MIPS32: ori [[T3]],[[T3]],0xffff
4988 ; MIPS32: and [[T2]],[[T2]],[[T3]]
4989 ; MIPS32: or [[T6]],[[T6]],[[T2]]
4990 ; MIPS32: srl [[T9:.*]],a2,0x18
4991 ; MIPS32: andi [[T9]],[[T9]],0x1
4992 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
4993 ; MIPS32: andi [[T10]],[[T10]],0x1
4994 ; MIPS32: sll [[T9]],[[T9]],0x1f
4995 ; MIPS32: sll [[T10]],[[T10]],0x1f
4996 ; MIPS32: slt [[T10]],[[T10]],[[T9]]
4997 ; MIPS32: srl [[T10]],[[T10]],0x18
4998 ; MIPS32: sll [[T6]],[[T6]],0x8
4999 ; MIPS32: srl [[T6]],[[T6]],0x8
5000 ; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
5001 ; MIPS32: andi [[T3]],a3,0xff
5002 ; MIPS32: andi [[T3]],[[T3]],0x1
5003 ; MIPS32: andi [[T6]],[[BV_E3]],0xff
5004 ; MIPS32: andi [[T6]],[[T6]],0x1
5005 ; MIPS32: sll [[T3]],[[T3]],0x1f
5006 ; MIPS32: sll [[T6]],[[T6]],0x1f
5007 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
5008 ; MIPS32: andi [[T6]],[[T6]],0xff
5009 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
5010 ; MIPS32: sll [[T11]],[[T11]],0x8
5011 ; MIPS32: or [[T6]],[[T6]],[[T11]]
5012 ; MIPS32: srl [[T3]],a3,0x8
5013 ; MIPS32: andi [[T3]],[[T3]],0xff
5014 ; MIPS32: andi [[T3]],[[T3]],0x1
5015 ; MIPS32: srl [[T9]],[[BV_E3]],0x8
5016 ; MIPS32: andi [[T9]],[[T9]],0xff
5017 ; MIPS32: andi [[T9]],[[T9]],0x1
5018 ; MIPS32: sll [[T3]],[[T3]],0x1f
5019 ; MIPS32: sll [[T9]],[[T9]],0x1f
5020 ; MIPS32: slt [[T9]],[[T9]],[[T3]]
5021 ; MIPS32: andi [[T9]],[[T9]],0xff
5022 ; MIPS32: sll [[T9]],[[T9]],0x8
5023 ; MIPS32: lui [[T3]],0xffff
5024 ; MIPS32: ori [[T3]],[[T3]],0xff
5025 ; MIPS32: and [[T6]],[[T6]],[[T3]]
5026 ; MIPS32: or [[T9]],[[T9]],[[T6]]
5027 ; MIPS32: srl [[T3]],a3,0x10
5028 ; MIPS32: andi [[T3]],[[T3]],0xff
5029 ; MIPS32: andi [[T3]],[[T3]],0x1
5030 ; MIPS32: srl [[T6]],[[BV_E3]],0x10
5031 ; MIPS32: andi [[T6]],[[T6]],0xff
5032 ; MIPS32: andi [[T6]],[[T6]],0x1
5033 ; MIPS32: sll [[T3]],[[T3]],0x1f
5034 ; MIPS32: sll [[T6]],[[T6]],0x1f
5035 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
5036 ; MIPS32: andi [[T6]],[[T6]],0xff
5037 ; MIPS32: sll [[T6]],[[T6]],0x10
5038 ; MIPS32: lui [[T3]],0xff00
5039 ; MIPS32: ori [[T3]],[[T3]],0xffff
5040 ; MIPS32: and [[T9]],[[T9]],[[T3]]
5041 ; MIPS32: or [[T6]],[[T6]],[[T9]]
5042 ; MIPS32: srl [[T12:.*]],a3,0x18
5043 ; MIPS32: andi [[T12]],[[T12]],0x1
5044 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
5045 ; MIPS32: andi [[T13]],[[T13]],0x1
5046 ; MIPS32: sll [[T12]],[[T12]],0x1f
5047 ; MIPS32: sll [[T13]],[[T13]],0x1f
5048 ; MIPS32: slt [[T13]],[[T13]],[[T12]]
5049 ; MIPS32: srl [[T13]],[[T13]],0x18
5050 ; MIPS32: sll [[T6]],[[T6]],0x8
5051 ; MIPS32: srl [[T6]],[[T6]],0x8
5052 ; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
442 } 5053 }
443 5054
444 define internal <16 x i1> @test_icmp_v16i1_sle(<16 x i1> %a, <16 x i1> %b) { 5055 define internal <16 x i1> @test_icmp_v16i1_sle(<16 x i1> %a, <16 x i1> %b) {
445 entry: 5056 entry:
446 %res = icmp sle <16 x i1> %a, %b 5057 %res = icmp sle <16 x i1> %a, %b
447 ret <16 x i1> %res 5058 ret <16 x i1> %res
448 ; CHECK-LABEL: test_icmp_v16i1_sle 5059 ; CHECK-LABEL: test_icmp_v16i1_sle
449 ; CHECK: pcmpgtb 5060 ; CHECK: pcmpgtb
450 ; CHECK: pxor 5061 ; CHECK: pxor
5062
5063 ; MIPS32-LABEL: test_icmp_v16i1_sle
5064 ; MIPS32: lw [[BV_E0:.*]],
5065 ; MIPS32: lw [[BV_E1:.*]],
5066 ; MIPS32: lw [[BV_E2:.*]],
5067 ; MIPS32: lw [[BV_E3:.*]],
5068 ; MIPS32: move [[TV_E0:.*]],zero
5069 ; MIPS32: move [[TV_E1:.*]],zero
5070 ; MIPS32: move [[TV_E2:.*]],zero
5071 ; MIPS32: move [[TV_E3:.*]],zero
5072 ; MIPS32: andi [[T0:.*]],a0,0xff
5073 ; MIPS32: andi [[T0]],[[T0]],0x1
5074 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
5075 ; MIPS32: andi [[T1]],[[T1]],0x1
5076 ; MIPS32: sll [[T0]],[[T0]],0x1f
5077 ; MIPS32: sll [[T1]],[[T1]],0x1f
5078 ; MIPS32: slt [[T1]],[[T1]],[[T0]]
5079 ; MIPS32: xori [[T1]],[[T1]],0x1
5080 ; MIPS32: andi [[T1]],[[T1]],0xff
5081 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
5082 ; MIPS32: sll [[T2]],[[T2]],0x8
5083 ; MIPS32: or [[T1]],[[T1]],[[T2]]
5084 ; MIPS32: srl [[T2]],a0,0x8
5085 ; MIPS32: andi [[T2]],[[T2]],0xff
5086 ; MIPS32: andi [[T2]],[[T2]],0x1
5087 ; MIPS32: srl [[T0]],[[BV_E0]],0x8
5088 ; MIPS32: andi [[T0]],[[T0]],0xff
5089 ; MIPS32: andi [[T0]],[[T0]],0x1
5090 ; MIPS32: sll [[T2]],[[T2]],0x1f
5091 ; MIPS32: sll [[T0]],[[T0]],0x1f
5092 ; MIPS32: slt [[T0]],[[T0]],[[T2]]
5093 ; MIPS32: xori [[T0]],[[T0]],0x1
5094 ; MIPS32: andi [[T0]],[[T0]],0xff
5095 ; MIPS32: sll [[T0]],[[T0]],0x8
5096 ; MIPS32: lui [[T2]],0xffff
5097 ; MIPS32: ori [[T2]],[[T2]],0xff
5098 ; MIPS32: and [[T1]],[[T1]],[[T2]]
5099 ; MIPS32: or [[T0]],[[T0]],[[T1]]
5100 ; MIPS32: srl [[T2]],a0,0x10
5101 ; MIPS32: andi [[T2]],[[T2]],0xff
5102 ; MIPS32: andi [[T2]],[[T2]],0x1
5103 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
5104 ; MIPS32: andi [[T1]],[[T1]],0xff
5105 ; MIPS32: andi [[T1]],[[T1]],0x1
5106 ; MIPS32: sll [[T2]],[[T2]],0x1f
5107 ; MIPS32: sll [[T1]],[[T1]],0x1f
5108 ; MIPS32: slt [[T1]],[[T1]],[[T2]]
5109 ; MIPS32: xori [[T1]],[[T1]],0x1
5110 ; MIPS32: andi [[T1]],[[T1]],0xff
5111 ; MIPS32: sll [[T1]],[[T1]],0x10
5112 ; MIPS32: lui [[T2]],0xff00
5113 ; MIPS32: ori [[T2]],[[T2]],0xffff
5114 ; MIPS32: and [[T0]],[[T0]],[[T2]]
5115 ; MIPS32: or [[T1]],[[T1]],[[T0]]
5116 ; MIPS32: srl [[T3:.*]],a0,0x18
5117 ; MIPS32: andi [[T3]],[[T3]],0x1
5118 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
5119 ; MIPS32: andi [[T4]],[[T4]],0x1
5120 ; MIPS32: sll [[T3]],[[T3]],0x1f
5121 ; MIPS32: sll [[T4]],[[T4]],0x1f
5122 ; MIPS32: slt [[T4]],[[T4]],[[T3]]
5123 ; MIPS32: xori [[T4]],[[T4]],0x1
5124 ; MIPS32: srl [[T4]],[[T4]],0x18
5125 ; MIPS32: sll [[T1]],[[T1]],0x8
5126 ; MIPS32: srl [[T1]],[[T1]],0x8
5127 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
5128 ; MIPS32: andi [[T3]],a1,0xff
5129 ; MIPS32: andi [[T3]],[[T3]],0x1
5130 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
5131 ; MIPS32: andi [[T2]],[[T2]],0x1
5132 ; MIPS32: sll [[T3]],[[T3]],0x1f
5133 ; MIPS32: sll [[T2]],[[T2]],0x1f
5134 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
5135 ; MIPS32: xori [[T2]],[[T2]],0x1
5136 ; MIPS32: andi [[T2]],[[T2]],0xff
5137 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
5138 ; MIPS32: sll [[T5]],[[T5]],0x8
5139 ; MIPS32: or [[T2]],[[T2]],[[T5]]
5140 ; MIPS32: srl [[T3]],a1,0x8
5141 ; MIPS32: andi [[T3]],[[T3]],0xff
5142 ; MIPS32: andi [[T3]],[[T3]],0x1
5143 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
5144 ; MIPS32: andi [[T5]],[[T5]],0xff
5145 ; MIPS32: andi [[T5]],[[T5]],0x1
5146 ; MIPS32: sll [[T3]],[[T3]],0x1f
5147 ; MIPS32: sll [[T5]],[[T5]],0x1f
5148 ; MIPS32: slt [[T5]],[[T5]],[[T3]]
5149 ; MIPS32: xori [[T5]],[[T5]],0x1
5150 ; MIPS32: andi [[T5]],[[T5]],0xff
5151 ; MIPS32: sll [[T5]],[[T5]],0x8
5152 ; MIPS32: lui [[T3]],0xffff
5153 ; MIPS32: ori [[T3]],[[T3]],0xff
5154 ; MIPS32: and [[T2]],[[T2]],[[T3]]
5155 ; MIPS32: or [[T5]],[[T5]],[[T2]]
5156 ; MIPS32: srl [[T3]],a1,0x10
5157 ; MIPS32: andi [[T3]],[[T3]],0xff
5158 ; MIPS32: andi [[T3]],[[T3]],0x1
5159 ; MIPS32: srl [[T2]],[[BV_E1]],0x10
5160 ; MIPS32: andi [[T2]],[[T2]],0xff
5161 ; MIPS32: andi [[T2]],[[T2]],0x1
5162 ; MIPS32: sll [[T3]],[[T3]],0x1f
5163 ; MIPS32: sll [[T2]],[[T2]],0x1f
5164 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
5165 ; MIPS32: xori [[T2]],[[T2]],0x1
5166 ; MIPS32: andi [[T2]],[[T2]],0xff
5167 ; MIPS32: sll [[T2]],[[T2]],0x10
5168 ; MIPS32: lui [[T3]],0xff00
5169 ; MIPS32: ori [[T3]],[[T3]],0xffff
5170 ; MIPS32: and [[T5]],[[T5]],[[T3]]
5171 ; MIPS32: or [[T2]],[[T2]],[[T5]]
5172 ; MIPS32: srl [[T6:.*]],a1,0x18
5173 ; MIPS32: andi [[T6]],[[T6]],0x1
5174 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
5175 ; MIPS32: andi [[T7]],[[T7]],0x1
5176 ; MIPS32: sll [[T6]],[[T6]],0x1f
5177 ; MIPS32: sll [[T7]],[[T7]],0x1f
5178 ; MIPS32: slt [[T7]],[[T7]],[[T6]]
5179 ; MIPS32: xori [[T7]],[[T7]],0x1
5180 ; MIPS32: srl [[T7]],[[T7]],0x18
5181 ; MIPS32: sll [[T2]],[[T2]],0x8
5182 ; MIPS32: srl [[T2]],[[T2]],0x8
5183 ; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
5184 ; MIPS32: andi [[T3]],a2,0xff
5185 ; MIPS32: andi [[T3]],[[T3]],0x1
5186 ; MIPS32: andi [[T6]],[[BV_E2]],0xff
5187 ; MIPS32: andi [[T6]],[[T6]],0x1
5188 ; MIPS32: sll [[T3]],[[T3]],0x1f
5189 ; MIPS32: sll [[T6]],[[T6]],0x1f
5190 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
5191 ; MIPS32: xori [[T6]],[[T6]],0x1
5192 ; MIPS32: andi [[T6]],[[T6]],0xff
5193 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
5194 ; MIPS32: sll [[T8]],[[T8]],0x8
5195 ; MIPS32: or [[T6]],[[T6]],[[T8]]
5196 ; MIPS32: srl [[T3]],a2,0x8
5197 ; MIPS32: andi [[T3]],[[T3]],0xff
5198 ; MIPS32: andi [[T3]],[[T3]],0x1
5199 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
5200 ; MIPS32: andi [[T2]],[[T2]],0xff
5201 ; MIPS32: andi [[T2]],[[T2]],0x1
5202 ; MIPS32: sll [[T3]],[[T3]],0x1f
5203 ; MIPS32: sll [[T2]],[[T2]],0x1f
5204 ; MIPS32: slt [[T2]],[[T2]],[[T3]]
5205 ; MIPS32: xori [[T2]],[[T2]],0x1
5206 ; MIPS32: andi [[T2]],[[T2]],0xff
5207 ; MIPS32: sll [[T2]],[[T2]],0x8
5208 ; MIPS32: lui [[T3]],0xffff
5209 ; MIPS32: ori [[T3]],[[T3]],0xff
5210 ; MIPS32: and [[T6]],[[T6]],[[T3]]
5211 ; MIPS32: or [[T2]],[[T2]],[[T6]]
5212 ; MIPS32: srl [[T3]],a2,0x10
5213 ; MIPS32: andi [[T3]],[[T3]],0xff
5214 ; MIPS32: andi [[T3]],[[T3]],0x1
5215 ; MIPS32: srl [[T6]],[[BV_E2]],0x10
5216 ; MIPS32: andi [[T6]],[[T6]],0xff
5217 ; MIPS32: andi [[T6]],[[T6]],0x1
5218 ; MIPS32: sll [[T3]],[[T3]],0x1f
5219 ; MIPS32: sll [[T6]],[[T6]],0x1f
5220 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
5221 ; MIPS32: xori [[T6]],[[T6]],0x1
5222 ; MIPS32: andi [[T6]],[[T6]],0xff
5223 ; MIPS32: sll [[T6]],[[T6]],0x10
5224 ; MIPS32: lui [[T3]],0xff00
5225 ; MIPS32: ori [[T3]],[[T3]],0xffff
5226 ; MIPS32: and [[T2]],[[T2]],[[T3]]
5227 ; MIPS32: or [[T6]],[[T6]],[[T2]]
5228 ; MIPS32: srl [[T9:.*]],a2,0x18
5229 ; MIPS32: andi [[T9]],[[T9]],0x1
5230 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
5231 ; MIPS32: andi [[T10]],[[T10]],0x1
5232 ; MIPS32: sll [[T9]],[[T9]],0x1f
5233 ; MIPS32: sll [[T10]],[[T10]],0x1f
5234 ; MIPS32: slt [[T10]],[[T10]],[[T9]]
5235 ; MIPS32: xori [[T10]],[[T10]],0x1
5236 ; MIPS32: srl [[T10]],[[T10]],0x18
5237 ; MIPS32: sll [[T6]],[[T6]],0x8
5238 ; MIPS32: srl [[T6]],[[T6]],0x8
5239 ; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
5240 ; MIPS32: andi [[T3]],a3,0xff
5241 ; MIPS32: andi [[T3]],[[T3]],0x1
5242 ; MIPS32: andi [[T6]],[[BV_E3]],0xff
5243 ; MIPS32: andi [[T6]],[[T6]],0x1
5244 ; MIPS32: sll [[T3]],[[T3]],0x1f
5245 ; MIPS32: sll [[T6]],[[T6]],0x1f
5246 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
5247 ; MIPS32: xori [[T6]],[[T6]],0x1
5248 ; MIPS32: andi [[T6]],[[T6]],0xff
5249 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
5250 ; MIPS32: sll [[T11]],[[T11]],0x8
5251 ; MIPS32: or [[T6]],[[T6]],[[T11]]
5252 ; MIPS32: srl [[T3]],a3,0x8
5253 ; MIPS32: andi [[T3]],[[T3]],0xff
5254 ; MIPS32: andi [[T3]],[[T3]],0x1
5255 ; MIPS32: srl [[T9]],[[BV_E3]],0x8
5256 ; MIPS32: andi [[T9]],[[T9]],0xff
5257 ; MIPS32: andi [[T9]],[[T9]],0x1
5258 ; MIPS32: sll [[T3]],[[T3]],0x1f
5259 ; MIPS32: sll [[T9]],[[T9]],0x1f
5260 ; MIPS32: slt [[T9]],[[T9]],[[T3]]
5261 ; MIPS32: xori [[T9]],[[T9]],0x1
5262 ; MIPS32: andi [[T9]],[[T9]],0xff
5263 ; MIPS32: sll [[T9]],[[T9]],0x8
5264 ; MIPS32: lui [[T3]],0xffff
5265 ; MIPS32: ori [[T3]],[[T3]],0xff
5266 ; MIPS32: and [[T6]],[[T6]],[[T3]]
5267 ; MIPS32: or [[T9]],[[T9]],[[T6]]
5268 ; MIPS32: srl [[T3]],a3,0x10
5269 ; MIPS32: andi [[T3]],[[T3]],0xff
5270 ; MIPS32: andi [[T3]],[[T3]],0x1
5271 ; MIPS32: srl [[T6]],[[BV_E3]],0x10
5272 ; MIPS32: andi [[T6]],[[T6]],0xff
5273 ; MIPS32: andi [[T6]],[[T6]],0x1
5274 ; MIPS32: sll [[T3]],[[T3]],0x1f
5275 ; MIPS32: sll [[T6]],[[T6]],0x1f
5276 ; MIPS32: slt [[T6]],[[T6]],[[T3]]
5277 ; MIPS32: xori [[T6]],[[T6]],0x1
5278 ; MIPS32: andi [[T6]],[[T6]],0xff
5279 ; MIPS32: sll [[T6]],[[T6]],0x10
5280 ; MIPS32: lui [[T3]],0xff00
5281 ; MIPS32: ori [[T3]],[[T3]],0xffff
5282 ; MIPS32: and [[T9]],[[T9]],[[T3]]
5283 ; MIPS32: or [[T6]],[[T6]],[[T9]]
5284 ; MIPS32: srl [[T12:.*]],a3,0x18
5285 ; MIPS32: andi [[T12]],[[T12]],0x1
5286 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
5287 ; MIPS32: andi [[T13]],[[T13]],0x1
5288 ; MIPS32: sll [[T12]],[[T12]],0x1f
5289 ; MIPS32: sll [[T13]],[[T13]],0x1f
5290 ; MIPS32: slt [[T13]],[[T13]],[[T12]]
5291 ; MIPS32: xori [[T13]],[[T13]],0x1
5292 ; MIPS32: srl [[T13]],[[T13]],0x18
5293 ; MIPS32: sll [[T6]],[[T6]],0x8
5294 ; MIPS32: srl [[T6]],[[T6]],0x8
5295 ; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
451 } 5296 }
452 5297
453 define internal <16 x i1> @test_icmp_v16i1_slt(<16 x i1> %a, <16 x i1> %b) { 5298 define internal <16 x i1> @test_icmp_v16i1_slt(<16 x i1> %a, <16 x i1> %b) {
454 entry: 5299 entry:
455 %res = icmp slt <16 x i1> %a, %b 5300 %res = icmp slt <16 x i1> %a, %b
456 ret <16 x i1> %res 5301 ret <16 x i1> %res
457 ; CHECK-LABEL: test_icmp_v16i1_slt 5302 ; CHECK-LABEL: test_icmp_v16i1_slt
458 ; CHECK: pcmpgtb 5303 ; CHECK: pcmpgtb
5304
5305 ; MIPS32-LABEL: test_icmp_v16i1_slt
5306 ; MIPS32: lw [[BV_E0:.*]],
5307 ; MIPS32: lw [[BV_E1:.*]],
5308 ; MIPS32: lw [[BV_E2:.*]],
5309 ; MIPS32: lw [[BV_E3:.*]],
5310 ; MIPS32: move [[TV_E0:.*]],zero
5311 ; MIPS32: move [[TV_E1:.*]],zero
5312 ; MIPS32: move [[TV_E2:.*]],zero
5313 ; MIPS32: move [[TV_E3:.*]],zero
5314 ; MIPS32: andi [[T0:.*]],a0,0xff
5315 ; MIPS32: andi [[T0]],[[T0]],0x1
5316 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
5317 ; MIPS32: andi [[T1]],[[T1]],0x1
5318 ; MIPS32: sll [[T0]],[[T0]],0x1f
5319 ; MIPS32: sll [[T1]],[[T1]],0x1f
5320 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
5321 ; MIPS32: andi [[T0]],[[T0]],0xff
5322 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
5323 ; MIPS32: sll [[T2]],[[T2]],0x8
5324 ; MIPS32: or [[T0]],[[T0]],[[T2]]
5325 ; MIPS32: srl [[T2]],a0,0x8
5326 ; MIPS32: andi [[T2]],[[T2]],0xff
5327 ; MIPS32: andi [[T2]],[[T2]],0x1
5328 ; MIPS32: srl [[T1]],[[BV_E0]],0x8
5329 ; MIPS32: andi [[T1]],[[T1]],0xff
5330 ; MIPS32: andi [[T1]],[[T1]],0x1
5331 ; MIPS32: sll [[T2]],[[T2]],0x1f
5332 ; MIPS32: sll [[T1]],[[T1]],0x1f
5333 ; MIPS32: slt [[T2]],[[T2]],[[T1]]
5334 ; MIPS32: andi [[T2]],[[T2]],0xff
5335 ; MIPS32: sll [[T2]],[[T2]],0x8
5336 ; MIPS32: lui [[T1]],0xffff
5337 ; MIPS32: ori [[T1]],[[T1]],0xff
5338 ; MIPS32: and [[T0]],[[T0]],[[T1]]
5339 ; MIPS32: or [[T2]],[[T2]],[[T0]]
5340 ; MIPS32: srl [[T0]],a0,0x10
5341 ; MIPS32: andi [[T0]],[[T0]],0xff
5342 ; MIPS32: andi [[T0]],[[T0]],0x1
5343 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
5344 ; MIPS32: andi [[T1]],[[T1]],0xff
5345 ; MIPS32: andi [[T1]],[[T1]],0x1
5346 ; MIPS32: sll [[T0]],[[T0]],0x1f
5347 ; MIPS32: sll [[T1]],[[T1]],0x1f
5348 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
5349 ; MIPS32: andi [[T0]],[[T0]],0xff
5350 ; MIPS32: sll [[T0]],[[T0]],0x10
5351 ; MIPS32: lui [[T1]],0xff00
5352 ; MIPS32: ori [[T1]],[[T1]],0xffff
5353 ; MIPS32: and [[T2]],[[T2]],[[T1]]
5354 ; MIPS32: or [[T0]],[[T0]],[[T2]]
5355 ; MIPS32: srl [[T3:.*]],a0,0x18
5356 ; MIPS32: andi [[T3]],[[T3]],0x1
5357 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
5358 ; MIPS32: andi [[T4]],[[T4]],0x1
5359 ; MIPS32: sll [[T3]],[[T3]],0x1f
5360 ; MIPS32: sll [[T4]],[[T4]],0x1f
5361 ; MIPS32: slt [[T3]],[[T3]],[[T4]]
5362 ; MIPS32: srl [[T3]],[[T3]],0x18
5363 ; MIPS32: sll [[T0]],[[T0]],0x8
5364 ; MIPS32: srl [[T0]],[[T0]],0x8
5365 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
5366 ; MIPS32: andi [[T4]],a1,0xff
5367 ; MIPS32: andi [[T4]],[[T4]],0x1
5368 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
5369 ; MIPS32: andi [[T2]],[[T2]],0x1
5370 ; MIPS32: sll [[T4]],[[T4]],0x1f
5371 ; MIPS32: sll [[T2]],[[T2]],0x1f
5372 ; MIPS32: slt [[T4]],[[T4]],[[T2]]
5373 ; MIPS32: andi [[T4]],[[T4]],0xff
5374 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
5375 ; MIPS32: sll [[T5]],[[T5]],0x8
5376 ; MIPS32: or [[T4]],[[T4]],[[T5]]
5377 ; MIPS32: srl [[T2]],a1,0x8
5378 ; MIPS32: andi [[T2]],[[T2]],0xff
5379 ; MIPS32: andi [[T2]],[[T2]],0x1
5380 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
5381 ; MIPS32: andi [[T5]],[[T5]],0xff
5382 ; MIPS32: andi [[T5]],[[T5]],0x1
5383 ; MIPS32: sll [[T2]],[[T2]],0x1f
5384 ; MIPS32: sll [[T5]],[[T5]],0x1f
5385 ; MIPS32: slt [[T2]],[[T2]],[[T5]]
5386 ; MIPS32: andi [[T2]],[[T2]],0xff
5387 ; MIPS32: sll [[T2]],[[T2]],0x8
5388 ; MIPS32: lui [[T5]],0xffff
5389 ; MIPS32: ori [[T5]],[[T5]],0xff
5390 ; MIPS32: and [[T4]],[[T4]],[[T5]]
5391 ; MIPS32: or [[T2]],[[T2]],[[T4]]
5392 ; MIPS32: srl [[T4]],a1,0x10
5393 ; MIPS32: andi [[T4]],[[T4]],0xff
5394 ; MIPS32: andi [[T4]],[[T4]],0x1
5395 ; MIPS32: srl [[T5]],[[BV_E1]],0x10
5396 ; MIPS32: andi [[T5]],[[T5]],0xff
5397 ; MIPS32: andi [[T5]],[[T5]],0x1
5398 ; MIPS32: sll [[T4]],[[T4]],0x1f
5399 ; MIPS32: sll [[T5]],[[T5]],0x1f
5400 ; MIPS32: slt [[T4]],[[T4]],[[T5]]
5401 ; MIPS32: andi [[T4]],[[T4]],0xff
5402 ; MIPS32: sll [[T4]],[[T4]],0x10
5403 ; MIPS32: lui [[T5]],0xff00
5404 ; MIPS32: ori [[T5]],[[T5]],0xffff
5405 ; MIPS32: and [[T2]],[[T2]],[[T5]]
5406 ; MIPS32: or [[T4]],[[T4]],[[T2]]
5407 ; MIPS32: srl [[T6:.*]],a1,0x18
5408 ; MIPS32: andi [[T6]],[[T6]],0x1
5409 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
5410 ; MIPS32: andi [[T7]],[[T7]],0x1
5411 ; MIPS32: sll [[T6]],[[T6]],0x1f
5412 ; MIPS32: sll [[T7]],[[T7]],0x1f
5413 ; MIPS32: slt [[T6]],[[T6]],[[T7]]
5414 ; MIPS32: srl [[T6]],[[T6]],0x18
5415 ; MIPS32: sll [[T4]],[[T4]],0x8
5416 ; MIPS32: srl [[T4]],[[T4]],0x8
5417 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
5418 ; MIPS32: andi [[T4]],a2,0xff
5419 ; MIPS32: andi [[T4]],[[T4]],0x1
5420 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
5421 ; MIPS32: andi [[T7]],[[T7]],0x1
5422 ; MIPS32: sll [[T4]],[[T4]],0x1f
5423 ; MIPS32: sll [[T7]],[[T7]],0x1f
5424 ; MIPS32: slt [[T4]],[[T4]],[[T7]]
5425 ; MIPS32: andi [[T4]],[[T4]],0xff
5426 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
5427 ; MIPS32: sll [[T8]],[[T8]],0x8
5428 ; MIPS32: or [[T4]],[[T4]],[[T8]]
5429 ; MIPS32: srl [[T7]],a2,0x8
5430 ; MIPS32: andi [[T7]],[[T7]],0xff
5431 ; MIPS32: andi [[T7]],[[T7]],0x1
5432 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
5433 ; MIPS32: andi [[T2]],[[T2]],0xff
5434 ; MIPS32: andi [[T2]],[[T2]],0x1
5435 ; MIPS32: sll [[T7]],[[T7]],0x1f
5436 ; MIPS32: sll [[T2]],[[T2]],0x1f
5437 ; MIPS32: slt [[T7]],[[T7]],[[T2]]
5438 ; MIPS32: andi [[T7]],[[T7]],0xff
5439 ; MIPS32: sll [[T7]],[[T7]],0x8
5440 ; MIPS32: lui [[T2]],0xffff
5441 ; MIPS32: ori [[T2]],[[T2]],0xff
5442 ; MIPS32: and [[T4]],[[T4]],[[T2]]
5443 ; MIPS32: or [[T7]],[[T7]],[[T4]]
5444 ; MIPS32: srl [[T4]],a2,0x10
5445 ; MIPS32: andi [[T4]],[[T4]],0xff
5446 ; MIPS32: andi [[T4]],[[T4]],0x1
5447 ; MIPS32: srl [[T2]],[[BV_E2]],0x10
5448 ; MIPS32: andi [[T2]],[[T2]],0xff
5449 ; MIPS32: andi [[T2]],[[T2]],0x1
5450 ; MIPS32: sll [[T4]],[[T4]],0x1f
5451 ; MIPS32: sll [[T2]],[[T2]],0x1f
5452 ; MIPS32: slt [[T4]],[[T4]],[[T2]]
5453 ; MIPS32: andi [[T4]],[[T4]],0xff
5454 ; MIPS32: sll [[T4]],[[T4]],0x10
5455 ; MIPS32: lui [[T2]],0xff00
5456 ; MIPS32: ori [[T2]],[[T2]],0xffff
5457 ; MIPS32: and [[T7]],[[T7]],[[T2]]
5458 ; MIPS32: or [[T4]],[[T4]],[[T7]]
5459 ; MIPS32: srl [[T9:.*]],a2,0x18
5460 ; MIPS32: andi [[T9]],[[T9]],0x1
5461 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
5462 ; MIPS32: andi [[T10]],[[T10]],0x1
5463 ; MIPS32: sll [[T9]],[[T9]],0x1f
5464 ; MIPS32: sll [[T10]],[[T10]],0x1f
5465 ; MIPS32: slt [[T9]],[[T9]],[[T10]]
5466 ; MIPS32: srl [[T9]],[[T9]],0x18
5467 ; MIPS32: sll [[T4]],[[T4]],0x8
5468 ; MIPS32: srl [[T4]],[[T4]],0x8
5469 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
5470 ; MIPS32: andi [[T4]],a3,0xff
5471 ; MIPS32: andi [[T4]],[[T4]],0x1
5472 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
5473 ; MIPS32: andi [[T7]],[[T7]],0x1
5474 ; MIPS32: sll [[T4]],[[T4]],0x1f
5475 ; MIPS32: sll [[T7]],[[T7]],0x1f
5476 ; MIPS32: slt [[T4]],[[T4]],[[T7]]
5477 ; MIPS32: andi [[T4]],[[T4]],0xff
5478 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
5479 ; MIPS32: sll [[T11]],[[T11]],0x8
5480 ; MIPS32: or [[T4]],[[T4]],[[T11]]
5481 ; MIPS32: srl [[T7]],a3,0x8
5482 ; MIPS32: andi [[T7]],[[T7]],0xff
5483 ; MIPS32: andi [[T7]],[[T7]],0x1
5484 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
5485 ; MIPS32: andi [[T10]],[[T10]],0xff
5486 ; MIPS32: andi [[T10]],[[T10]],0x1
5487 ; MIPS32: sll [[T7]],[[T7]],0x1f
5488 ; MIPS32: sll [[T10]],[[T10]],0x1f
5489 ; MIPS32: slt [[T7]],[[T7]],[[T10]]
5490 ; MIPS32: andi [[T7]],[[T7]],0xff
5491 ; MIPS32: sll [[T7]],[[T7]],0x8
5492 ; MIPS32: lui [[T10]],0xffff
5493 ; MIPS32: ori [[T10]],[[T10]],0xff
5494 ; MIPS32: and [[T4]],[[T4]],[[T10]]
5495 ; MIPS32: or [[T7]],[[T7]],[[T4]]
5496 ; MIPS32: srl [[T4]],a3,0x10
5497 ; MIPS32: andi [[T4]],[[T4]],0xff
5498 ; MIPS32: andi [[T4]],[[T4]],0x1
5499 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
5500 ; MIPS32: andi [[T10]],[[T10]],0xff
5501 ; MIPS32: andi [[T10]],[[T10]],0x1
5502 ; MIPS32: sll [[T4]],[[T4]],0x1f
5503 ; MIPS32: sll [[T10]],[[T10]],0x1f
5504 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
5505 ; MIPS32: andi [[T4]],[[T4]],0xff
5506 ; MIPS32: sll [[T4]],[[T4]],0x10
5507 ; MIPS32: lui [[T10]],0xff00
5508 ; MIPS32: ori [[T10]],[[T10]],0xffff
5509 ; MIPS32: and [[T7]],[[T7]],[[T10]]
5510 ; MIPS32: or [[T4]],[[T4]],[[T7]]
5511 ; MIPS32: srl [[T12:.*]],a3,0x18
5512 ; MIPS32: andi [[T12]],[[T12]],0x1
5513 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
5514 ; MIPS32: andi [[T13]],[[T13]],0x1
5515 ; MIPS32: sll [[T12]],[[T12]],0x1f
5516 ; MIPS32: sll [[T13]],[[T13]],0x1f
5517 ; MIPS32: slt [[T12]],[[T12]],[[T13]]
5518 ; MIPS32: srl [[T12]],[[T12]],0x18
5519 ; MIPS32: sll [[T4]],[[T4]],0x8
5520 ; MIPS32: srl [[T4]],[[T4]],0x8
5521 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
459 } 5522 }
460 5523
461 define internal <16 x i1> @test_icmp_v16i1_uge(<16 x i1> %a, <16 x i1> %b) { 5524 define internal <16 x i1> @test_icmp_v16i1_uge(<16 x i1> %a, <16 x i1> %b) {
462 entry: 5525 entry:
463 %res = icmp uge <16 x i1> %a, %b 5526 %res = icmp uge <16 x i1> %a, %b
464 ret <16 x i1> %res 5527 ret <16 x i1> %res
465 ; CHECK-LABEL: test_icmp_v16i1_uge 5528 ; CHECK-LABEL: test_icmp_v16i1_uge
466 ; CHECK: pxor 5529 ; CHECK: pxor
467 ; CHECK: pcmpgtb 5530 ; CHECK: pcmpgtb
468 ; CHECK: pxor 5531 ; CHECK: pxor
5532
5533 ; MIPS32-LABEL: test_icmp_v16i1_uge
5534 ; MIPS32: lw [[BV_E0:.*]],
5535 ; MIPS32: lw [[BV_E1:.*]],
5536 ; MIPS32: lw [[BV_E2:.*]],
5537 ; MIPS32: lw [[BV_E3:.*]],
5538 ; MIPS32: move [[TV_E0:.*]],zero
5539 ; MIPS32: move [[TV_E1:.*]],zero
5540 ; MIPS32: move [[TV_E2:.*]],zero
5541 ; MIPS32: move [[TV_E3:.*]],zero
5542 ; MIPS32: andi [[T0:.*]],a0,0xff
5543 ; MIPS32: andi [[T0]],[[T0]],0x1
5544 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
5545 ; MIPS32: andi [[T1]],[[T1]],0x1
5546 ; MIPS32: sll [[T0]],[[T0]],0x1f
5547 ; MIPS32: sll [[T1]],[[T1]],0x1f
5548 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
5549 ; MIPS32: xori [[T0]],[[T0]],0x1
5550 ; MIPS32: andi [[T0]],[[T0]],0xff
5551 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
5552 ; MIPS32: sll [[T2]],[[T2]],0x8
5553 ; MIPS32: or [[T0]],[[T0]],[[T2]]
5554 ; MIPS32: srl [[T2]],a0,0x8
5555 ; MIPS32: andi [[T2]],[[T2]],0xff
5556 ; MIPS32: andi [[T2]],[[T2]],0x1
5557 ; MIPS32: srl [[T1]],[[BV_E0]],0x8
5558 ; MIPS32: andi [[T1]],[[T1]],0xff
5559 ; MIPS32: andi [[T1]],[[T1]],0x1
5560 ; MIPS32: sll [[T2]],[[T2]],0x1f
5561 ; MIPS32: sll [[T1]],[[T1]],0x1f
5562 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
5563 ; MIPS32: xori [[T2]],[[T2]],0x1
5564 ; MIPS32: andi [[T2]],[[T2]],0xff
5565 ; MIPS32: sll [[T2]],[[T2]],0x8
5566 ; MIPS32: lui [[T1]],0xffff
5567 ; MIPS32: ori [[T1]],[[T1]],0xff
5568 ; MIPS32: and [[T0]],[[T0]],[[T1]]
5569 ; MIPS32: or [[T2]],[[T2]],[[T0]]
5570 ; MIPS32: srl [[T0]],a0,0x10
5571 ; MIPS32: andi [[T0]],[[T0]],0xff
5572 ; MIPS32: andi [[T0]],[[T0]],0x1
5573 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
5574 ; MIPS32: andi [[T1]],[[T1]],0xff
5575 ; MIPS32: andi [[T1]],[[T1]],0x1
5576 ; MIPS32: sll [[T0]],[[T0]],0x1f
5577 ; MIPS32: sll [[T1]],[[T1]],0x1f
5578 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
5579 ; MIPS32: xori [[T0]],[[T0]],0x1
5580 ; MIPS32: andi [[T0]],[[T0]],0xff
5581 ; MIPS32: sll [[T0]],[[T0]],0x10
5582 ; MIPS32: lui [[T1]],0xff00
5583 ; MIPS32: ori [[T1]],[[T1]],0xffff
5584 ; MIPS32: and [[T2]],[[T2]],[[T1]]
5585 ; MIPS32: or [[T0]],[[T0]],[[T2]]
5586 ; MIPS32: srl [[T3:.*]],a0,0x18
5587 ; MIPS32: andi [[T3]],[[T3]],0x1
5588 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
5589 ; MIPS32: andi [[T4]],[[T4]],0x1
5590 ; MIPS32: sll [[T3]],[[T3]],0x1f
5591 ; MIPS32: sll [[T4]],[[T4]],0x1f
5592 ; MIPS32: sltu [[T3]],[[T3]],[[T4]]
5593 ; MIPS32: xori [[T3]],[[T3]],0x1
5594 ; MIPS32: srl [[T3]],[[T3]],0x18
5595 ; MIPS32: sll [[T0]],[[T0]],0x8
5596 ; MIPS32: srl [[T0]],[[T0]],0x8
5597 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
5598 ; MIPS32: andi [[T4]],a1,0xff
5599 ; MIPS32: andi [[T4]],[[T4]],0x1
5600 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
5601 ; MIPS32: andi [[T2]],[[T2]],0x1
5602 ; MIPS32: sll [[T4]],[[T4]],0x1f
5603 ; MIPS32: sll [[T2]],[[T2]],0x1f
5604 ; MIPS32: sltu [[T4]],[[T4]],[[T2]]
5605 ; MIPS32: xori [[T4]],[[T4]],0x1
5606 ; MIPS32: andi [[T4]],[[T4]],0xff
5607 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
5608 ; MIPS32: sll [[T5]],[[T5]],0x8
5609 ; MIPS32: or [[T4]],[[T4]],[[T5]]
5610 ; MIPS32: srl [[T2]],a1,0x8
5611 ; MIPS32: andi [[T2]],[[T2]],0xff
5612 ; MIPS32: andi [[T2]],[[T2]],0x1
5613 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
5614 ; MIPS32: andi [[T5]],[[T5]],0xff
5615 ; MIPS32: andi [[T5]],[[T5]],0x1
5616 ; MIPS32: sll [[T2]],[[T2]],0x1f
5617 ; MIPS32: sll [[T5]],[[T5]],0x1f
5618 ; MIPS32: sltu [[T2]],[[T2]],[[T5]]
5619 ; MIPS32: xori [[T2]],[[T2]],0x1
5620 ; MIPS32: andi [[T2]],[[T2]],0xff
5621 ; MIPS32: sll [[T2]],[[T2]],0x8
5622 ; MIPS32: lui [[T5]],0xffff
5623 ; MIPS32: ori [[T5]],[[T5]],0xff
5624 ; MIPS32: and [[T4]],[[T4]],[[T5]]
5625 ; MIPS32: or [[T2]],[[T2]],[[T4]]
5626 ; MIPS32: srl [[T4]],a1,0x10
5627 ; MIPS32: andi [[T4]],[[T4]],0xff
5628 ; MIPS32: andi [[T4]],[[T4]],0x1
5629 ; MIPS32: srl [[T5]],[[BV_E1]],0x10
5630 ; MIPS32: andi [[T5]],[[T5]],0xff
5631 ; MIPS32: andi [[T5]],[[T5]],0x1
5632 ; MIPS32: sll [[T4]],[[T4]],0x1f
5633 ; MIPS32: sll [[T5]],[[T5]],0x1f
5634 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
5635 ; MIPS32: xori [[T4]],[[T4]],0x1
5636 ; MIPS32: andi [[T4]],[[T4]],0xff
5637 ; MIPS32: sll [[T4]],[[T4]],0x10
5638 ; MIPS32: lui [[T5]],0xff00
5639 ; MIPS32: ori [[T5]],[[T5]],0xffff
5640 ; MIPS32: and [[T2]],[[T2]],[[T5]]
5641 ; MIPS32: or [[T4]],[[T4]],[[T2]]
5642 ; MIPS32: srl [[T6:.*]],a1,0x18
5643 ; MIPS32: andi [[T6]],[[T6]],0x1
5644 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
5645 ; MIPS32: andi [[T7]],[[T7]],0x1
5646 ; MIPS32: sll [[T6]],[[T6]],0x1f
5647 ; MIPS32: sll [[T7]],[[T7]],0x1f
5648 ; MIPS32: sltu [[T6]],[[T6]],[[T7]]
5649 ; MIPS32: xori [[T6]],[[T6]],0x1
5650 ; MIPS32: srl [[T6]],[[T6]],0x18
5651 ; MIPS32: sll [[T4]],[[T4]],0x8
5652 ; MIPS32: srl [[T4]],[[T4]],0x8
5653 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
5654 ; MIPS32: andi [[T4]],a2,0xff
5655 ; MIPS32: andi [[T4]],[[T4]],0x1
5656 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
5657 ; MIPS32: andi [[T7]],[[T7]],0x1
5658 ; MIPS32: sll [[T4]],[[T4]],0x1f
5659 ; MIPS32: sll [[T7]],[[T7]],0x1f
5660 ; MIPS32: sltu [[T4]],[[T4]],[[T7]]
5661 ; MIPS32: xori [[T4]],[[T4]],0x1
5662 ; MIPS32: andi [[T4]],[[T4]],0xff
5663 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
5664 ; MIPS32: sll [[T8]],[[T8]],0x8
5665 ; MIPS32: or [[T4]],[[T4]],[[T8]]
5666 ; MIPS32: srl [[T7]],a2,0x8
5667 ; MIPS32: andi [[T7]],[[T7]],0xff
5668 ; MIPS32: andi [[T7]],[[T7]],0x1
5669 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
5670 ; MIPS32: andi [[T2]],[[T2]],0xff
5671 ; MIPS32: andi [[T2]],[[T2]],0x1
5672 ; MIPS32: sll [[T7]],[[T7]],0x1f
5673 ; MIPS32: sll [[T2]],[[T2]],0x1f
5674 ; MIPS32: sltu [[T7]],[[T7]],[[T2]]
5675 ; MIPS32: xori [[T7]],[[T7]],0x1
5676 ; MIPS32: andi [[T7]],[[T7]],0xff
5677 ; MIPS32: sll [[T7]],[[T7]],0x8
5678 ; MIPS32: lui [[T2]],0xffff
5679 ; MIPS32: ori [[T2]],[[T2]],0xff
5680 ; MIPS32: and [[T4]],[[T4]],[[T2]]
5681 ; MIPS32: or [[T7]],[[T7]],[[T4]]
5682 ; MIPS32: srl [[T4]],a2,0x10
5683 ; MIPS32: andi [[T4]],[[T4]],0xff
5684 ; MIPS32: andi [[T4]],[[T4]],0x1
5685 ; MIPS32: srl [[T2]],[[BV_E2]],0x10
5686 ; MIPS32: andi [[T2]],[[T2]],0xff
5687 ; MIPS32: andi [[T2]],[[T2]],0x1
5688 ; MIPS32: sll [[T4]],[[T4]],0x1f
5689 ; MIPS32: sll [[T2]],[[T2]],0x1f
5690 ; MIPS32: sltu [[T4]],[[T4]],[[T2]]
5691 ; MIPS32: xori [[T4]],[[T4]],0x1
5692 ; MIPS32: andi [[T4]],[[T4]],0xff
5693 ; MIPS32: sll [[T4]],[[T4]],0x10
5694 ; MIPS32: lui [[T2]],0xff00
5695 ; MIPS32: ori [[T2]],[[T2]],0xffff
5696 ; MIPS32: and [[T7]],[[T7]],[[T2]]
5697 ; MIPS32: or [[T4]],[[T4]],[[T7]]
5698 ; MIPS32: srl [[T9:.*]],a2,0x18
5699 ; MIPS32: andi [[T9]],[[T9]],0x1
5700 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
5701 ; MIPS32: andi [[T10]],[[T10]],0x1
5702 ; MIPS32: sll [[T9]],[[T9]],0x1f
5703 ; MIPS32: sll [[T10]],[[T10]],0x1f
5704 ; MIPS32: sltu [[T9]],[[T9]],[[T10]]
5705 ; MIPS32: xori [[T9]],[[T9]],0x1
5706 ; MIPS32: srl [[T9]],[[T9]],0x18
5707 ; MIPS32: sll [[T4]],[[T4]],0x8
5708 ; MIPS32: srl [[T4]],[[T4]],0x8
5709 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
5710 ; MIPS32: andi [[T4]],a3,0xff
5711 ; MIPS32: andi [[T4]],[[T4]],0x1
5712 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
5713 ; MIPS32: andi [[T7]],[[T7]],0x1
5714 ; MIPS32: sll [[T4]],[[T4]],0x1f
5715 ; MIPS32: sll [[T7]],[[T7]],0x1f
5716 ; MIPS32: sltu [[T4]],[[T4]],[[T7]]
5717 ; MIPS32: xori [[T4]],[[T4]],0x1
5718 ; MIPS32: andi [[T4]],[[T4]],0xff
5719 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
5720 ; MIPS32: sll [[T11]],[[T11]],0x8
5721 ; MIPS32: or [[T4]],[[T4]],[[T11]]
5722 ; MIPS32: srl [[T7]],a3,0x8
5723 ; MIPS32: andi [[T7]],[[T7]],0xff
5724 ; MIPS32: andi [[T7]],[[T7]],0x1
5725 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
5726 ; MIPS32: andi [[T10]],[[T10]],0xff
5727 ; MIPS32: andi [[T10]],[[T10]],0x1
5728 ; MIPS32: sll [[T7]],[[T7]],0x1f
5729 ; MIPS32: sll [[T10]],[[T10]],0x1f
5730 ; MIPS32: sltu [[T7]],[[T7]],[[T10]]
5731 ; MIPS32: xori [[T7]],[[T7]],0x1
5732 ; MIPS32: andi [[T7]],[[T7]],0xff
5733 ; MIPS32: sll [[T7]],[[T7]],0x8
5734 ; MIPS32: lui [[T10]],0xffff
5735 ; MIPS32: ori [[T10]],[[T10]],0xff
5736 ; MIPS32: and [[T4]],[[T4]],[[T10]]
5737 ; MIPS32: or [[T7]],[[T7]],[[T4]]
5738 ; MIPS32: srl [[T4]],a3,0x10
5739 ; MIPS32: andi [[T4]],[[T4]],0xff
5740 ; MIPS32: andi [[T4]],[[T4]],0x1
5741 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
5742 ; MIPS32: andi [[T10]],[[T10]],0xff
5743 ; MIPS32: andi [[T10]],[[T10]],0x1
5744 ; MIPS32: sll [[T4]],[[T4]],0x1f
5745 ; MIPS32: sll [[T10]],[[T10]],0x1f
5746 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
5747 ; MIPS32: xori [[T4]],[[T4]],0x1
5748 ; MIPS32: andi [[T4]],[[T4]],0xff
5749 ; MIPS32: sll [[T4]],[[T4]],0x10
5750 ; MIPS32: lui [[T10]],0xff00
5751 ; MIPS32: ori [[T10]],[[T10]],0xffff
5752 ; MIPS32: and [[T7]],[[T7]],[[T10]]
5753 ; MIPS32: or [[T4]],[[T4]],[[T7]]
5754 ; MIPS32: srl [[T12:.*]],a3,0x18
5755 ; MIPS32: andi [[T12]],[[T12]],0x1
5756 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
5757 ; MIPS32: andi [[T13]],[[T13]],0x1
5758 ; MIPS32: sll [[T12]],[[T12]],0x1f
5759 ; MIPS32: sll [[T13]],[[T13]],0x1f
5760 ; MIPS32: sltu [[T12]],[[T12]],[[T13]]
5761 ; MIPS32: xori [[T12]],[[T12]],0x1
5762 ; MIPS32: srl [[T12]],[[T12]],0x18
5763 ; MIPS32: sll [[T4]],[[T4]],0x8
5764 ; MIPS32: srl [[T4]],[[T4]],0x8
5765 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
469 } 5766 }
470 5767
471 define internal <16 x i1> @test_icmp_v16i1_ugt(<16 x i1> %a, <16 x i1> %b) { 5768 define internal <16 x i1> @test_icmp_v16i1_ugt(<16 x i1> %a, <16 x i1> %b) {
472 entry: 5769 entry:
473 %res = icmp ugt <16 x i1> %a, %b 5770 %res = icmp ugt <16 x i1> %a, %b
474 ret <16 x i1> %res 5771 ret <16 x i1> %res
475 ; CHECK-LABEL: test_icmp_v16i1_ugt 5772 ; CHECK-LABEL: test_icmp_v16i1_ugt
476 ; CHECK: pxor 5773 ; CHECK: pxor
477 ; CHECK: pcmpgtb 5774 ; CHECK: pcmpgtb
5775
5776 ; MIPS32-LABEL: test_icmp_v16i1_ugt
5777 ; MIPS32: lw [[BV_E0:.*]],
5778 ; MIPS32: lw [[BV_E1:.*]],
5779 ; MIPS32: lw [[BV_E2:.*]],
5780 ; MIPS32: lw [[BV_E3:.*]],
5781 ; MIPS32: move [[TV_E0:.*]],zero
5782 ; MIPS32: move [[TV_E1:.*]],zero
5783 ; MIPS32: move [[TV_E2:.*]],zero
5784 ; MIPS32: move [[TV_E3:.*]],zero
5785 ; MIPS32: andi [[T0:.*]],a0,0xff
5786 ; MIPS32: andi [[T0]],[[T0]],0x1
5787 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
5788 ; MIPS32: andi [[T1]],[[T1]],0x1
5789 ; MIPS32: sll [[T0]],[[T0]],0x1f
5790 ; MIPS32: sll [[T1]],[[T1]],0x1f
5791 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
5792 ; MIPS32: andi [[T1]],[[T1]],0xff
5793 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
5794 ; MIPS32: sll [[T2]],[[T2]],0x8
5795 ; MIPS32: or [[T1]],[[T1]],[[T2]]
5796 ; MIPS32: srl [[T2]],a0,0x8
5797 ; MIPS32: andi [[T2]],[[T2]],0xff
5798 ; MIPS32: andi [[T2]],[[T2]],0x1
5799 ; MIPS32: srl [[T0]],[[BV_E0]],0x8
5800 ; MIPS32: andi [[T0]],[[T0]],0xff
5801 ; MIPS32: andi [[T0]],[[T0]],0x1
5802 ; MIPS32: sll [[T2]],[[T2]],0x1f
5803 ; MIPS32: sll [[T0]],[[T0]],0x1f
5804 ; MIPS32: sltu [[T0]],[[T0]],[[T2]]
5805 ; MIPS32: andi [[T0]],[[T0]],0xff
5806 ; MIPS32: sll [[T0]],[[T0]],0x8
5807 ; MIPS32: lui [[T2]],0xffff
5808 ; MIPS32: ori [[T2]],[[T2]],0xff
5809 ; MIPS32: and [[T1]],[[T1]],[[T2]]
5810 ; MIPS32: or [[T0]],[[T0]],[[T1]]
5811 ; MIPS32: srl [[T2]],a0,0x10
5812 ; MIPS32: andi [[T2]],[[T2]],0xff
5813 ; MIPS32: andi [[T2]],[[T2]],0x1
5814 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
5815 ; MIPS32: andi [[T1]],[[T1]],0xff
5816 ; MIPS32: andi [[T1]],[[T1]],0x1
5817 ; MIPS32: sll [[T2]],[[T2]],0x1f
5818 ; MIPS32: sll [[T1]],[[T1]],0x1f
5819 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
5820 ; MIPS32: andi [[T1]],[[T1]],0xff
5821 ; MIPS32: sll [[T1]],[[T1]],0x10
5822 ; MIPS32: lui [[T2]],0xff00
5823 ; MIPS32: ori [[T2]],[[T2]],0xffff
5824 ; MIPS32: and [[T0]],[[T0]],[[T2]]
5825 ; MIPS32: or [[T1]],[[T1]],[[T0]]
5826 ; MIPS32: srl [[T3:.*]],a0,0x18
5827 ; MIPS32: andi [[T3]],[[T3]],0x1
5828 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
5829 ; MIPS32: andi [[T4]],[[T4]],0x1
5830 ; MIPS32: sll [[T3]],[[T3]],0x1f
5831 ; MIPS32: sll [[T4]],[[T4]],0x1f
5832 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
5833 ; MIPS32: srl [[T4]],[[T4]],0x18
5834 ; MIPS32: sll [[T1]],[[T1]],0x8
5835 ; MIPS32: srl [[T1]],[[T1]],0x8
5836 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
5837 ; MIPS32: andi [[T3]],a1,0xff
5838 ; MIPS32: andi [[T3]],[[T3]],0x1
5839 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
5840 ; MIPS32: andi [[T2]],[[T2]],0x1
5841 ; MIPS32: sll [[T3]],[[T3]],0x1f
5842 ; MIPS32: sll [[T2]],[[T2]],0x1f
5843 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
5844 ; MIPS32: andi [[T2]],[[T2]],0xff
5845 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
5846 ; MIPS32: sll [[T5]],[[T5]],0x8
5847 ; MIPS32: or [[T2]],[[T2]],[[T5]]
5848 ; MIPS32: srl [[T3]],a1,0x8
5849 ; MIPS32: andi [[T3]],[[T3]],0xff
5850 ; MIPS32: andi [[T3]],[[T3]],0x1
5851 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
5852 ; MIPS32: andi [[T5]],[[T5]],0xff
5853 ; MIPS32: andi [[T5]],[[T5]],0x1
5854 ; MIPS32: sll [[T3]],[[T3]],0x1f
5855 ; MIPS32: sll [[T5]],[[T5]],0x1f
5856 ; MIPS32: sltu [[T5]],[[T5]],[[T3]]
5857 ; MIPS32: andi [[T5]],[[T5]],0xff
5858 ; MIPS32: sll [[T5]],[[T5]],0x8
5859 ; MIPS32: lui [[T3]],0xffff
5860 ; MIPS32: ori [[T3]],[[T3]],0xff
5861 ; MIPS32: and [[T2]],[[T2]],[[T3]]
5862 ; MIPS32: or [[T5]],[[T5]],[[T2]]
5863 ; MIPS32: srl [[T3]],a1,0x10
5864 ; MIPS32: andi [[T3]],[[T3]],0xff
5865 ; MIPS32: andi [[T3]],[[T3]],0x1
5866 ; MIPS32: srl [[T2]],[[BV_E1]],0x10
5867 ; MIPS32: andi [[T2]],[[T2]],0xff
5868 ; MIPS32: andi [[T2]],[[T2]],0x1
5869 ; MIPS32: sll [[T3]],[[T3]],0x1f
5870 ; MIPS32: sll [[T2]],[[T2]],0x1f
5871 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
5872 ; MIPS32: andi [[T2]],[[T2]],0xff
5873 ; MIPS32: sll [[T2]],[[T2]],0x10
5874 ; MIPS32: lui [[T3]],0xff00
5875 ; MIPS32: ori [[T3]],[[T3]],0xffff
5876 ; MIPS32: and [[T5]],[[T5]],[[T3]]
5877 ; MIPS32: or [[T2]],[[T2]],[[T5]]
5878 ; MIPS32: srl [[T6:.*]],a1,0x18
5879 ; MIPS32: andi [[T6]],[[T6]],0x1
5880 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
5881 ; MIPS32: andi [[T7]],[[T7]],0x1
5882 ; MIPS32: sll [[T6]],[[T6]],0x1f
5883 ; MIPS32: sll [[T7]],[[T7]],0x1f
5884 ; MIPS32: sltu [[T7]],[[T7]],[[T6]]
5885 ; MIPS32: srl [[T7]],[[T7]],0x18
5886 ; MIPS32: sll [[T2]],[[T2]],0x8
5887 ; MIPS32: srl [[T2]],[[T2]],0x8
5888 ; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
5889 ; MIPS32: andi [[T3]],a2,0xff
5890 ; MIPS32: andi [[T3]],[[T3]],0x1
5891 ; MIPS32: andi [[T6]],[[BV_E2]],0xff
5892 ; MIPS32: andi [[T6]],[[T6]],0x1
5893 ; MIPS32: sll [[T3]],[[T3]],0x1f
5894 ; MIPS32: sll [[T6]],[[T6]],0x1f
5895 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
5896 ; MIPS32: andi [[T6]],[[T6]],0xff
5897 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
5898 ; MIPS32: sll [[T8]],[[T8]],0x8
5899 ; MIPS32: or [[T6]],[[T6]],[[T8]]
5900 ; MIPS32: srl [[T3]],a2,0x8
5901 ; MIPS32: andi [[T3]],[[T3]],0xff
5902 ; MIPS32: andi [[T3]],[[T3]],0x1
5903 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
5904 ; MIPS32: andi [[T2]],[[T2]],0xff
5905 ; MIPS32: andi [[T2]],[[T2]],0x1
5906 ; MIPS32: sll [[T3]],[[T3]],0x1f
5907 ; MIPS32: sll [[T2]],[[T2]],0x1f
5908 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
5909 ; MIPS32: andi [[T2]],[[T2]],0xff
5910 ; MIPS32: sll [[T2]],[[T2]],0x8
5911 ; MIPS32: lui [[T3]],0xffff
5912 ; MIPS32: ori [[T3]],[[T3]],0xff
5913 ; MIPS32: and [[T6]],[[T6]],[[T3]]
5914 ; MIPS32: or [[T2]],[[T2]],[[T6]]
5915 ; MIPS32: srl [[T3]],a2,0x10
5916 ; MIPS32: andi [[T3]],[[T3]],0xff
5917 ; MIPS32: andi [[T3]],[[T3]],0x1
5918 ; MIPS32: srl [[T6]],[[BV_E2]],0x10
5919 ; MIPS32: andi [[T6]],[[T6]],0xff
5920 ; MIPS32: andi [[T6]],[[T6]],0x1
5921 ; MIPS32: sll [[T3]],[[T3]],0x1f
5922 ; MIPS32: sll [[T6]],[[T6]],0x1f
5923 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
5924 ; MIPS32: andi [[T6]],[[T6]],0xff
5925 ; MIPS32: sll [[T6]],[[T6]],0x10
5926 ; MIPS32: lui [[T3]],0xff00
5927 ; MIPS32: ori [[T3]],[[T3]],0xffff
5928 ; MIPS32: and [[T2]],[[T2]],[[T3]]
5929 ; MIPS32: or [[T6]],[[T6]],[[T2]]
5930 ; MIPS32: srl [[T9:.*]],a2,0x18
5931 ; MIPS32: andi [[T9]],[[T9]],0x1
5932 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
5933 ; MIPS32: andi [[T10]],[[T10]],0x1
5934 ; MIPS32: sll [[T9]],[[T9]],0x1f
5935 ; MIPS32: sll [[T10]],[[T10]],0x1f
5936 ; MIPS32: sltu [[T10]],[[T10]],[[T9]]
5937 ; MIPS32: srl [[T10]],[[T10]],0x18
5938 ; MIPS32: sll [[T6]],[[T6]],0x8
5939 ; MIPS32: srl [[T6]],[[T6]],0x8
5940 ; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
5941 ; MIPS32: andi [[T3]],a3,0xff
5942 ; MIPS32: andi [[T3]],[[T3]],0x1
5943 ; MIPS32: andi [[T6]],[[BV_E3]],0xff
5944 ; MIPS32: andi [[T6]],[[T6]],0x1
5945 ; MIPS32: sll [[T3]],[[T3]],0x1f
5946 ; MIPS32: sll [[T6]],[[T6]],0x1f
5947 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
5948 ; MIPS32: andi [[T6]],[[T6]],0xff
5949 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
5950 ; MIPS32: sll [[T11]],[[T11]],0x8
5951 ; MIPS32: or [[T6]],[[T6]],[[T11]]
5952 ; MIPS32: srl [[T3]],a3,0x8
5953 ; MIPS32: andi [[T3]],[[T3]],0xff
5954 ; MIPS32: andi [[T3]],[[T3]],0x1
5955 ; MIPS32: srl [[T9]],[[BV_E3]],0x8
5956 ; MIPS32: andi [[T9]],[[T9]],0xff
5957 ; MIPS32: andi [[T9]],[[T9]],0x1
5958 ; MIPS32: sll [[T3]],[[T3]],0x1f
5959 ; MIPS32: sll [[T9]],[[T9]],0x1f
5960 ; MIPS32: sltu [[T9]],[[T9]],[[T3]]
5961 ; MIPS32: andi [[T9]],[[T9]],0xff
5962 ; MIPS32: sll [[T9]],[[T9]],0x8
5963 ; MIPS32: lui [[T3]],0xffff
5964 ; MIPS32: ori [[T3]],[[T3]],0xff
5965 ; MIPS32: and [[T6]],[[T6]],[[T3]]
5966 ; MIPS32: or [[T9]],[[T9]],[[T6]]
5967 ; MIPS32: srl [[T3]],a3,0x10
5968 ; MIPS32: andi [[T3]],[[T3]],0xff
5969 ; MIPS32: andi [[T3]],[[T3]],0x1
5970 ; MIPS32: srl [[T6]],[[BV_E3]],0x10
5971 ; MIPS32: andi [[T6]],[[T6]],0xff
5972 ; MIPS32: andi [[T6]],[[T6]],0x1
5973 ; MIPS32: sll [[T3]],[[T3]],0x1f
5974 ; MIPS32: sll [[T6]],[[T6]],0x1f
5975 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
5976 ; MIPS32: andi [[T6]],[[T6]],0xff
5977 ; MIPS32: sll [[T6]],[[T6]],0x10
5978 ; MIPS32: lui [[T3]],0xff00
5979 ; MIPS32: ori [[T3]],[[T3]],0xffff
5980 ; MIPS32: and [[T9]],[[T9]],[[T3]]
5981 ; MIPS32: or [[T6]],[[T6]],[[T9]]
5982 ; MIPS32: srl [[T12:.*]],a3,0x18
5983 ; MIPS32: andi [[T12]],[[T12]],0x1
5984 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
5985 ; MIPS32: andi [[T13]],[[T13]],0x1
5986 ; MIPS32: sll [[T12]],[[T12]],0x1f
5987 ; MIPS32: sll [[T13]],[[T13]],0x1f
5988 ; MIPS32: sltu [[T13]],[[T13]],[[T12]]
5989 ; MIPS32: srl [[T13]],[[T13]],0x18
5990 ; MIPS32: sll [[T6]],[[T6]],0x8
5991 ; MIPS32: srl [[T6]],[[T6]],0x8
5992 ; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
478 } 5993 }
479 5994
480 define internal <16 x i1> @test_icmp_v16i1_ule(<16 x i1> %a, <16 x i1> %b) { 5995 define internal <16 x i1> @test_icmp_v16i1_ule(<16 x i1> %a, <16 x i1> %b) {
481 entry: 5996 entry:
482 %res = icmp ule <16 x i1> %a, %b 5997 %res = icmp ule <16 x i1> %a, %b
483 ret <16 x i1> %res 5998 ret <16 x i1> %res
484 ; CHECK-LABEL: test_icmp_v16i1_ule 5999 ; CHECK-LABEL: test_icmp_v16i1_ule
485 ; CHECK: pxor 6000 ; CHECK: pxor
486 ; CHECK: pcmpgtb 6001 ; CHECK: pcmpgtb
487 ; CHECK: pxor 6002 ; CHECK: pxor
6003
6004 ; MIPS32-LABEL: test_icmp_v16i1_ule
6005 ; MIPS32: lw [[BV_E0:.*]],
6006 ; MIPS32: lw [[BV_E1:.*]],
6007 ; MIPS32: lw [[BV_E2:.*]],
6008 ; MIPS32: lw [[BV_E3:.*]],
6009 ; MIPS32: move [[TV_E0:.*]],zero
6010 ; MIPS32: move [[TV_E1:.*]],zero
6011 ; MIPS32: move [[TV_E2:.*]],zero
6012 ; MIPS32: move [[TV_E3:.*]],zero
6013 ; MIPS32: andi [[T0:.*]],a0,0xff
6014 ; MIPS32: andi [[T0]],[[T0]],0x1
6015 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
6016 ; MIPS32: andi [[T1]],[[T1]],0x1
6017 ; MIPS32: sll [[T0]],[[T0]],0x1f
6018 ; MIPS32: sll [[T1]],[[T1]],0x1f
6019 ; MIPS32: sltu [[T1]],[[T1]],[[T0]]
6020 ; MIPS32: xori [[T1]],[[T1]],0x1
6021 ; MIPS32: andi [[T1]],[[T1]],0xff
6022 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
6023 ; MIPS32: sll [[T2]],[[T2]],0x8
6024 ; MIPS32: or [[T1]],[[T1]],[[T2]]
6025 ; MIPS32: srl [[T2]],a0,0x8
6026 ; MIPS32: andi [[T2]],[[T2]],0xff
6027 ; MIPS32: andi [[T2]],[[T2]],0x1
6028 ; MIPS32: srl [[T0]],[[BV_E0]],0x8
6029 ; MIPS32: andi [[T0]],[[T0]],0xff
6030 ; MIPS32: andi [[T0]],[[T0]],0x1
6031 ; MIPS32: sll [[T2]],[[T2]],0x1f
6032 ; MIPS32: sll [[T0]],[[T0]],0x1f
6033 ; MIPS32: sltu [[T0]],[[T0]],[[T2]]
6034 ; MIPS32: xori [[T0]],[[T0]],0x1
6035 ; MIPS32: andi [[T0]],[[T0]],0xff
6036 ; MIPS32: sll [[T0]],[[T0]],0x8
6037 ; MIPS32: lui [[T2]],0xffff
6038 ; MIPS32: ori [[T2]],[[T2]],0xff
6039 ; MIPS32: and [[T1]],[[T1]],[[T2]]
6040 ; MIPS32: or [[T0]],[[T0]],[[T1]]
6041 ; MIPS32: srl [[T2]],a0,0x10
6042 ; MIPS32: andi [[T2]],[[T2]],0xff
6043 ; MIPS32: andi [[T2]],[[T2]],0x1
6044 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
6045 ; MIPS32: andi [[T1]],[[T1]],0xff
6046 ; MIPS32: andi [[T1]],[[T1]],0x1
6047 ; MIPS32: sll [[T2]],[[T2]],0x1f
6048 ; MIPS32: sll [[T1]],[[T1]],0x1f
6049 ; MIPS32: sltu [[T1]],[[T1]],[[T2]]
6050 ; MIPS32: xori [[T1]],[[T1]],0x1
6051 ; MIPS32: andi [[T1]],[[T1]],0xff
6052 ; MIPS32: sll [[T1]],[[T1]],0x10
6053 ; MIPS32: lui [[T2]],0xff00
6054 ; MIPS32: ori [[T2]],[[T2]],0xffff
6055 ; MIPS32: and [[T0]],[[T0]],[[T2]]
6056 ; MIPS32: or [[T1]],[[T1]],[[T0]]
6057 ; MIPS32: srl [[T3:.*]],a0,0x18
6058 ; MIPS32: andi [[T3]],[[T3]],0x1
6059 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
6060 ; MIPS32: andi [[T4]],[[T4]],0x1
6061 ; MIPS32: sll [[T3]],[[T3]],0x1f
6062 ; MIPS32: sll [[T4]],[[T4]],0x1f
6063 ; MIPS32: sltu [[T4]],[[T4]],[[T3]]
6064 ; MIPS32: xori [[T4]],[[T4]],0x1
6065 ; MIPS32: srl [[T4]],[[T4]],0x18
6066 ; MIPS32: sll [[T1]],[[T1]],0x8
6067 ; MIPS32: srl [[T1]],[[T1]],0x8
6068 ; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
6069 ; MIPS32: andi [[T3]],a1,0xff
6070 ; MIPS32: andi [[T3]],[[T3]],0x1
6071 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
6072 ; MIPS32: andi [[T2]],[[T2]],0x1
6073 ; MIPS32: sll [[T3]],[[T3]],0x1f
6074 ; MIPS32: sll [[T2]],[[T2]],0x1f
6075 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
6076 ; MIPS32: xori [[T2]],[[T2]],0x1
6077 ; MIPS32: andi [[T2]],[[T2]],0xff
6078 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
6079 ; MIPS32: sll [[T5]],[[T5]],0x8
6080 ; MIPS32: or [[T2]],[[T2]],[[T5]]
6081 ; MIPS32: srl [[T3]],a1,0x8
6082 ; MIPS32: andi [[T3]],[[T3]],0xff
6083 ; MIPS32: andi [[T3]],[[T3]],0x1
6084 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
6085 ; MIPS32: andi [[T5]],[[T5]],0xff
6086 ; MIPS32: andi [[T5]],[[T5]],0x1
6087 ; MIPS32: sll [[T3]],[[T3]],0x1f
6088 ; MIPS32: sll [[T5]],[[T5]],0x1f
6089 ; MIPS32: sltu [[T5]],[[T5]],[[T3]]
6090 ; MIPS32: xori [[T5]],[[T5]],0x1
6091 ; MIPS32: andi [[T5]],[[T5]],0xff
6092 ; MIPS32: sll [[T5]],[[T5]],0x8
6093 ; MIPS32: lui [[T3]],0xffff
6094 ; MIPS32: ori [[T3]],[[T3]],0xff
6095 ; MIPS32: and [[T2]],[[T2]],[[T3]]
6096 ; MIPS32: or [[T5]],[[T5]],[[T2]]
6097 ; MIPS32: srl [[T3]],a1,0x10
6098 ; MIPS32: andi [[T3]],[[T3]],0xff
6099 ; MIPS32: andi [[T3]],[[T3]],0x1
6100 ; MIPS32: srl [[T2]],[[BV_E1]],0x10
6101 ; MIPS32: andi [[T2]],[[T2]],0xff
6102 ; MIPS32: andi [[T2]],[[T2]],0x1
6103 ; MIPS32: sll [[T3]],[[T3]],0x1f
6104 ; MIPS32: sll [[T2]],[[T2]],0x1f
6105 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
6106 ; MIPS32: xori [[T2]],[[T2]],0x1
6107 ; MIPS32: andi [[T2]],[[T2]],0xff
6108 ; MIPS32: sll [[T2]],[[T2]],0x10
6109 ; MIPS32: lui [[T3]],0xff00
6110 ; MIPS32: ori [[T3]],[[T3]],0xffff
6111 ; MIPS32: and [[T5]],[[T5]],[[T3]]
6112 ; MIPS32: or [[T2]],[[T2]],[[T5]]
6113 ; MIPS32: srl [[T6:.*]],a1,0x18
6114 ; MIPS32: andi [[T6]],[[T6]],0x1
6115 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
6116 ; MIPS32: andi [[T7]],[[T7]],0x1
6117 ; MIPS32: sll [[T6]],[[T6]],0x1f
6118 ; MIPS32: sll [[T7]],[[T7]],0x1f
6119 ; MIPS32: sltu [[T7]],[[T7]],[[T6]]
6120 ; MIPS32: xori [[T7]],[[T7]],0x1
6121 ; MIPS32: srl [[T7]],[[T7]],0x18
6122 ; MIPS32: sll [[T2]],[[T2]],0x8
6123 ; MIPS32: srl [[T2]],[[T2]],0x8
6124 ; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
6125 ; MIPS32: andi [[T3]],a2,0xff
6126 ; MIPS32: andi [[T3]],[[T3]],0x1
6127 ; MIPS32: andi [[T6]],[[BV_E2]],0xff
6128 ; MIPS32: andi [[T6]],[[T6]],0x1
6129 ; MIPS32: sll [[T3]],[[T3]],0x1f
6130 ; MIPS32: sll [[T6]],[[T6]],0x1f
6131 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
6132 ; MIPS32: xori [[T6]],[[T6]],0x1
6133 ; MIPS32: andi [[T6]],[[T6]],0xff
6134 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
6135 ; MIPS32: sll [[T8]],[[T8]],0x8
6136 ; MIPS32: or [[T6]],[[T6]],[[T8]]
6137 ; MIPS32: srl [[T3]],a2,0x8
6138 ; MIPS32: andi [[T3]],[[T3]],0xff
6139 ; MIPS32: andi [[T3]],[[T3]],0x1
6140 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
6141 ; MIPS32: andi [[T2]],[[T2]],0xff
6142 ; MIPS32: andi [[T2]],[[T2]],0x1
6143 ; MIPS32: sll [[T3]],[[T3]],0x1f
6144 ; MIPS32: sll [[T2]],[[T2]],0x1f
6145 ; MIPS32: sltu [[T2]],[[T2]],[[T3]]
6146 ; MIPS32: xori [[T2]],[[T2]],0x1
6147 ; MIPS32: andi [[T2]],[[T2]],0xff
6148 ; MIPS32: sll [[T2]],[[T2]],0x8
6149 ; MIPS32: lui [[T3]],0xffff
6150 ; MIPS32: ori [[T3]],[[T3]],0xff
6151 ; MIPS32: and [[T6]],[[T6]],[[T3]]
6152 ; MIPS32: or [[T2]],[[T2]],[[T6]]
6153 ; MIPS32: srl [[T3]],a2,0x10
6154 ; MIPS32: andi [[T3]],[[T3]],0xff
6155 ; MIPS32: andi [[T3]],[[T3]],0x1
6156 ; MIPS32: srl [[T6]],[[BV_E2]],0x10
6157 ; MIPS32: andi [[T6]],[[T6]],0xff
6158 ; MIPS32: andi [[T6]],[[T6]],0x1
6159 ; MIPS32: sll [[T3]],[[T3]],0x1f
6160 ; MIPS32: sll [[T6]],[[T6]],0x1f
6161 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
6162 ; MIPS32: xori [[T6]],[[T6]],0x1
6163 ; MIPS32: andi [[T6]],[[T6]],0xff
6164 ; MIPS32: sll [[T6]],[[T6]],0x10
6165 ; MIPS32: lui [[T3]],0xff00
6166 ; MIPS32: ori [[T3]],[[T3]],0xffff
6167 ; MIPS32: and [[T2]],[[T2]],[[T3]]
6168 ; MIPS32: or [[T6]],[[T6]],[[T2]]
6169 ; MIPS32: srl [[T9:.*]],a2,0x18
6170 ; MIPS32: andi [[T9]],[[T9]],0x1
6171 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
6172 ; MIPS32: andi [[T10]],[[T10]],0x1
6173 ; MIPS32: sll [[T9]],[[T9]],0x1f
6174 ; MIPS32: sll [[T10]],[[T10]],0x1f
6175 ; MIPS32: sltu [[T10]],[[T10]],[[T9]]
6176 ; MIPS32: xori [[T10]],[[T10]],0x1
6177 ; MIPS32: srl [[T10]],[[T10]],0x18
6178 ; MIPS32: sll [[T6]],[[T6]],0x8
6179 ; MIPS32: srl [[T6]],[[T6]],0x8
6180 ; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
6181 ; MIPS32: andi [[T3]],a3,0xff
6182 ; MIPS32: andi [[T3]],[[T3]],0x1
6183 ; MIPS32: andi [[T6]],[[BV_E3]],0xff
6184 ; MIPS32: andi [[T6]],[[T6]],0x1
6185 ; MIPS32: sll [[T3]],[[T3]],0x1f
6186 ; MIPS32: sll [[T6]],[[T6]],0x1f
6187 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
6188 ; MIPS32: xori [[T6]],[[T6]],0x1
6189 ; MIPS32: andi [[T6]],[[T6]],0xff
6190 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
6191 ; MIPS32: sll [[T11]],[[T11]],0x8
6192 ; MIPS32: or [[T6]],[[T6]],[[T11]]
6193 ; MIPS32: srl [[T3]],a3,0x8
6194 ; MIPS32: andi [[T3]],[[T3]],0xff
6195 ; MIPS32: andi [[T3]],[[T3]],0x1
6196 ; MIPS32: srl [[T9]],[[BV_E3]],0x8
6197 ; MIPS32: andi [[T9]],[[T9]],0xff
6198 ; MIPS32: andi [[T9]],[[T9]],0x1
6199 ; MIPS32: sll [[T3]],[[T3]],0x1f
6200 ; MIPS32: sll [[T9]],[[T9]],0x1f
6201 ; MIPS32: sltu [[T9]],[[T9]],[[T3]]
6202 ; MIPS32: xori [[T9]],[[T9]],0x1
6203 ; MIPS32: andi [[T9]],[[T9]],0xff
6204 ; MIPS32: sll [[T9]],[[T9]],0x8
6205 ; MIPS32: lui [[T3]],0xffff
6206 ; MIPS32: ori [[T3]],[[T3]],0xff
6207 ; MIPS32: and [[T6]],[[T6]],[[T3]]
6208 ; MIPS32: or [[T9]],[[T9]],[[T6]]
6209 ; MIPS32: srl [[T3]],a3,0x10
6210 ; MIPS32: andi [[T3]],[[T3]],0xff
6211 ; MIPS32: andi [[T3]],[[T3]],0x1
6212 ; MIPS32: srl [[T6]],[[BV_E3]],0x10
6213 ; MIPS32: andi [[T6]],[[T6]],0xff
6214 ; MIPS32: andi [[T6]],[[T6]],0x1
6215 ; MIPS32: sll [[T3]],[[T3]],0x1f
6216 ; MIPS32: sll [[T6]],[[T6]],0x1f
6217 ; MIPS32: sltu [[T6]],[[T6]],[[T3]]
6218 ; MIPS32: xori [[T6]],[[T6]],0x1
6219 ; MIPS32: andi [[T6]],[[T6]],0xff
6220 ; MIPS32: sll [[T6]],[[T6]],0x10
6221 ; MIPS32: lui [[T3]],0xff00
6222 ; MIPS32: ori [[T3]],[[T3]],0xffff
6223 ; MIPS32: and [[T9]],[[T9]],[[T3]]
6224 ; MIPS32: or [[T6]],[[T6]],[[T9]]
6225 ; MIPS32: srl [[T12:.*]],a3,0x18
6226 ; MIPS32: andi [[T12]],[[T12]],0x1
6227 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
6228 ; MIPS32: andi [[T13]],[[T13]],0x1
6229 ; MIPS32: sll [[T12]],[[T12]],0x1f
6230 ; MIPS32: sll [[T13]],[[T13]],0x1f
6231 ; MIPS32: sltu [[T13]],[[T13]],[[T12]]
6232 ; MIPS32: xori [[T13]],[[T13]],0x1
6233 ; MIPS32: srl [[T13]],[[T13]],0x18
6234 ; MIPS32: sll [[T6]],[[T6]],0x8
6235 ; MIPS32: srl [[T6]],[[T6]],0x8
6236 ; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
488 } 6237 }
489 6238
490 define internal <16 x i1> @test_icmp_v16i1_ult(<16 x i1> %a, <16 x i1> %b) { 6239 define internal <16 x i1> @test_icmp_v16i1_ult(<16 x i1> %a, <16 x i1> %b) {
491 entry: 6240 entry:
492 %res = icmp ult <16 x i1> %a, %b 6241 %res = icmp ult <16 x i1> %a, %b
493 ret <16 x i1> %res 6242 ret <16 x i1> %res
494 ; CHECK-LABEL: test_icmp_v16i1_ult 6243 ; CHECK-LABEL: test_icmp_v16i1_ult
495 ; CHECK: pxor 6244 ; CHECK: pxor
496 ; CHECK: pcmpgtb 6245 ; CHECK: pcmpgtb
6246
6247 ; MIPS32-LABEL: test_icmp_v16i1_ult
6248 ; MIPS32: lw [[BV_E0:.*]],
6249 ; MIPS32: lw [[BV_E1:.*]],
6250 ; MIPS32: lw [[BV_E2:.*]],
6251 ; MIPS32: lw [[BV_E3:.*]],
6252 ; MIPS32: move [[TV_E0:.*]],zero
6253 ; MIPS32: move [[TV_E1:.*]],zero
6254 ; MIPS32: move [[TV_E2:.*]],zero
6255 ; MIPS32: move [[TV_E3:.*]],zero
6256 ; MIPS32: andi [[T0:.*]],a0,0xff
6257 ; MIPS32: andi [[T0]],[[T0]],0x1
6258 ; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
6259 ; MIPS32: andi [[T1]],[[T1]],0x1
6260 ; MIPS32: sll [[T0]],[[T0]],0x1f
6261 ; MIPS32: sll [[T1]],[[T1]],0x1f
6262 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
6263 ; MIPS32: andi [[T0]],[[T0]],0xff
6264 ; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
6265 ; MIPS32: sll [[T2]],[[T2]],0x8
6266 ; MIPS32: or [[T0]],[[T0]],[[T2]]
6267 ; MIPS32: srl [[T2]],a0,0x8
6268 ; MIPS32: andi [[T2]],[[T2]],0xff
6269 ; MIPS32: andi [[T2]],[[T2]],0x1
6270 ; MIPS32: srl [[T1]],[[BV_E0]],0x8
6271 ; MIPS32: andi [[T1]],[[T1]],0xff
6272 ; MIPS32: andi [[T1]],[[T1]],0x1
6273 ; MIPS32: sll [[T2]],[[T2]],0x1f
6274 ; MIPS32: sll [[T1]],[[T1]],0x1f
6275 ; MIPS32: sltu [[T2]],[[T2]],[[T1]]
6276 ; MIPS32: andi [[T2]],[[T2]],0xff
6277 ; MIPS32: sll [[T2]],[[T2]],0x8
6278 ; MIPS32: lui [[T1]],0xffff
6279 ; MIPS32: ori [[T1]],[[T1]],0xff
6280 ; MIPS32: and [[T0]],[[T0]],[[T1]]
6281 ; MIPS32: or [[T2]],[[T2]],[[T0]]
6282 ; MIPS32: srl [[T0]],a0,0x10
6283 ; MIPS32: andi [[T0]],[[T0]],0xff
6284 ; MIPS32: andi [[T0]],[[T0]],0x1
6285 ; MIPS32: srl [[T1]],[[BV_E0]],0x10
6286 ; MIPS32: andi [[T1]],[[T1]],0xff
6287 ; MIPS32: andi [[T1]],[[T1]],0x1
6288 ; MIPS32: sll [[T0]],[[T0]],0x1f
6289 ; MIPS32: sll [[T1]],[[T1]],0x1f
6290 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
6291 ; MIPS32: andi [[T0]],[[T0]],0xff
6292 ; MIPS32: sll [[T0]],[[T0]],0x10
6293 ; MIPS32: lui [[T1]],0xff00
6294 ; MIPS32: ori [[T1]],[[T1]],0xffff
6295 ; MIPS32: and [[T2]],[[T2]],[[T1]]
6296 ; MIPS32: or [[T0]],[[T0]],[[T2]]
6297 ; MIPS32: srl [[T3:.*]],a0,0x18
6298 ; MIPS32: andi [[T3]],[[T3]],0x1
6299 ; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
6300 ; MIPS32: andi [[T4]],[[T4]],0x1
6301 ; MIPS32: sll [[T3]],[[T3]],0x1f
6302 ; MIPS32: sll [[T4]],[[T4]],0x1f
6303 ; MIPS32: sltu [[T3]],[[T3]],[[T4]]
6304 ; MIPS32: srl [[T3]],[[T3]],0x18
6305 ; MIPS32: sll [[T0]],[[T0]],0x8
6306 ; MIPS32: srl [[T0]],[[T0]],0x8
6307 ; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
6308 ; MIPS32: andi [[T4]],a1,0xff
6309 ; MIPS32: andi [[T4]],[[T4]],0x1
6310 ; MIPS32: andi [[T2]],[[BV_E1]],0xff
6311 ; MIPS32: andi [[T2]],[[T2]],0x1
6312 ; MIPS32: sll [[T4]],[[T4]],0x1f
6313 ; MIPS32: sll [[T2]],[[T2]],0x1f
6314 ; MIPS32: sltu [[T4]],[[T4]],[[T2]]
6315 ; MIPS32: andi [[T4]],[[T4]],0xff
6316 ; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
6317 ; MIPS32: sll [[T5]],[[T5]],0x8
6318 ; MIPS32: or [[T4]],[[T4]],[[T5]]
6319 ; MIPS32: srl [[T2]],a1,0x8
6320 ; MIPS32: andi [[T2]],[[T2]],0xff
6321 ; MIPS32: andi [[T2]],[[T2]],0x1
6322 ; MIPS32: srl [[T5]],[[BV_E1]],0x8
6323 ; MIPS32: andi [[T5]],[[T5]],0xff
6324 ; MIPS32: andi [[T5]],[[T5]],0x1
6325 ; MIPS32: sll [[T2]],[[T2]],0x1f
6326 ; MIPS32: sll [[T5]],[[T5]],0x1f
6327 ; MIPS32: sltu [[T2]],[[T2]],[[T5]]
6328 ; MIPS32: andi [[T2]],[[T2]],0xff
6329 ; MIPS32: sll [[T2]],[[T2]],0x8
6330 ; MIPS32: lui [[T5]],0xffff
6331 ; MIPS32: ori [[T5]],[[T5]],0xff
6332 ; MIPS32: and [[T4]],[[T4]],[[T5]]
6333 ; MIPS32: or [[T2]],[[T2]],[[T4]]
6334 ; MIPS32: srl [[T4]],a1,0x10
6335 ; MIPS32: andi [[T4]],[[T4]],0xff
6336 ; MIPS32: andi [[T4]],[[T4]],0x1
6337 ; MIPS32: srl [[T5]],[[BV_E1]],0x10
6338 ; MIPS32: andi [[T5]],[[T5]],0xff
6339 ; MIPS32: andi [[T5]],[[T5]],0x1
6340 ; MIPS32: sll [[T4]],[[T4]],0x1f
6341 ; MIPS32: sll [[T5]],[[T5]],0x1f
6342 ; MIPS32: sltu [[T4]],[[T4]],[[T5]]
6343 ; MIPS32: andi [[T4]],[[T4]],0xff
6344 ; MIPS32: sll [[T4]],[[T4]],0x10
6345 ; MIPS32: lui [[T5]],0xff00
6346 ; MIPS32: ori [[T5]],[[T5]],0xffff
6347 ; MIPS32: and [[T2]],[[T2]],[[T5]]
6348 ; MIPS32: or [[T4]],[[T4]],[[T2]]
6349 ; MIPS32: srl [[T6:.*]],a1,0x18
6350 ; MIPS32: andi [[T6]],[[T6]],0x1
6351 ; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
6352 ; MIPS32: andi [[T7]],[[T7]],0x1
6353 ; MIPS32: sll [[T6]],[[T6]],0x1f
6354 ; MIPS32: sll [[T7]],[[T7]],0x1f
6355 ; MIPS32: sltu [[T6]],[[T6]],[[T7]]
6356 ; MIPS32: srl [[T6]],[[T6]],0x18
6357 ; MIPS32: sll [[T4]],[[T4]],0x8
6358 ; MIPS32: srl [[T4]],[[T4]],0x8
6359 ; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
6360 ; MIPS32: andi [[T4]],a2,0xff
6361 ; MIPS32: andi [[T4]],[[T4]],0x1
6362 ; MIPS32: andi [[T7]],[[BV_E2]],0xff
6363 ; MIPS32: andi [[T7]],[[T7]],0x1
6364 ; MIPS32: sll [[T4]],[[T4]],0x1f
6365 ; MIPS32: sll [[T7]],[[T7]],0x1f
6366 ; MIPS32: sltu [[T4]],[[T4]],[[T7]]
6367 ; MIPS32: andi [[T4]],[[T4]],0xff
6368 ; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
6369 ; MIPS32: sll [[T8]],[[T8]],0x8
6370 ; MIPS32: or [[T4]],[[T4]],[[T8]]
6371 ; MIPS32: srl [[T7]],a2,0x8
6372 ; MIPS32: andi [[T7]],[[T7]],0xff
6373 ; MIPS32: andi [[T7]],[[T7]],0x1
6374 ; MIPS32: srl [[T2]],[[BV_E2]],0x8
6375 ; MIPS32: andi [[T2]],[[T2]],0xff
6376 ; MIPS32: andi [[T2]],[[T2]],0x1
6377 ; MIPS32: sll [[T7]],[[T7]],0x1f
6378 ; MIPS32: sll [[T2]],[[T2]],0x1f
6379 ; MIPS32: sltu [[T7]],[[T7]],[[T2]]
6380 ; MIPS32: andi [[T7]],[[T7]],0xff
6381 ; MIPS32: sll [[T7]],[[T7]],0x8
6382 ; MIPS32: lui [[T2]],0xffff
6383 ; MIPS32: ori [[T2]],[[T2]],0xff
6384 ; MIPS32: and [[T4]],[[T4]],[[T2]]
6385 ; MIPS32: or [[T7]],[[T7]],[[T4]]
6386 ; MIPS32: srl [[T4]],a2,0x10
6387 ; MIPS32: andi [[T4]],[[T4]],0xff
6388 ; MIPS32: andi [[T4]],[[T4]],0x1
6389 ; MIPS32: srl [[T2]],[[BV_E2]],0x10
6390 ; MIPS32: andi [[T2]],[[T2]],0xff
6391 ; MIPS32: andi [[T2]],[[T2]],0x1
6392 ; MIPS32: sll [[T4]],[[T4]],0x1f
6393 ; MIPS32: sll [[T2]],[[T2]],0x1f
6394 ; MIPS32: sltu [[T4]],[[T4]],[[T2]]
6395 ; MIPS32: andi [[T4]],[[T4]],0xff
6396 ; MIPS32: sll [[T4]],[[T4]],0x10
6397 ; MIPS32: lui [[T2]],0xff00
6398 ; MIPS32: ori [[T2]],[[T2]],0xffff
6399 ; MIPS32: and [[T7]],[[T7]],[[T2]]
6400 ; MIPS32: or [[T4]],[[T4]],[[T7]]
6401 ; MIPS32: srl [[T9:.*]],a2,0x18
6402 ; MIPS32: andi [[T9]],[[T9]],0x1
6403 ; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
6404 ; MIPS32: andi [[T10]],[[T10]],0x1
6405 ; MIPS32: sll [[T9]],[[T9]],0x1f
6406 ; MIPS32: sll [[T10]],[[T10]],0x1f
6407 ; MIPS32: sltu [[T9]],[[T9]],[[T10]]
6408 ; MIPS32: srl [[T9]],[[T9]],0x18
6409 ; MIPS32: sll [[T4]],[[T4]],0x8
6410 ; MIPS32: srl [[T4]],[[T4]],0x8
6411 ; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
6412 ; MIPS32: andi [[T4]],a3,0xff
6413 ; MIPS32: andi [[T4]],[[T4]],0x1
6414 ; MIPS32: andi [[T7]],[[BV_E3]],0xff
6415 ; MIPS32: andi [[T7]],[[T7]],0x1
6416 ; MIPS32: sll [[T4]],[[T4]],0x1f
6417 ; MIPS32: sll [[T7]],[[T7]],0x1f
6418 ; MIPS32: sltu [[T4]],[[T4]],[[T7]]
6419 ; MIPS32: andi [[T4]],[[T4]],0xff
6420 ; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
6421 ; MIPS32: sll [[T11]],[[T11]],0x8
6422 ; MIPS32: or [[T4]],[[T4]],[[T11]]
6423 ; MIPS32: srl [[T7]],a3,0x8
6424 ; MIPS32: andi [[T7]],[[T7]],0xff
6425 ; MIPS32: andi [[T7]],[[T7]],0x1
6426 ; MIPS32: srl [[T10]],[[BV_E3]],0x8
6427 ; MIPS32: andi [[T10]],[[T10]],0xff
6428 ; MIPS32: andi [[T10]],[[T10]],0x1
6429 ; MIPS32: sll [[T7]],[[T7]],0x1f
6430 ; MIPS32: sll [[T10]],[[T10]],0x1f
6431 ; MIPS32: sltu [[T7]],[[T7]],[[T10]]
6432 ; MIPS32: andi [[T7]],[[T7]],0xff
6433 ; MIPS32: sll [[T7]],[[T7]],0x8
6434 ; MIPS32: lui [[T10]],0xffff
6435 ; MIPS32: ori [[T10]],[[T10]],0xff
6436 ; MIPS32: and [[T4]],[[T4]],[[T10]]
6437 ; MIPS32: or [[T7]],[[T7]],[[T4]]
6438 ; MIPS32: srl [[T4]],a3,0x10
6439 ; MIPS32: andi [[T4]],[[T4]],0xff
6440 ; MIPS32: andi [[T4]],[[T4]],0x1
6441 ; MIPS32: srl [[T10]],[[BV_E3]],0x10
6442 ; MIPS32: andi [[T10]],[[T10]],0xff
6443 ; MIPS32: andi [[T10]],[[T10]],0x1
6444 ; MIPS32: sll [[T4]],[[T4]],0x1f
6445 ; MIPS32: sll [[T10]],[[T10]],0x1f
6446 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
6447 ; MIPS32: andi [[T4]],[[T4]],0xff
6448 ; MIPS32: sll [[T4]],[[T4]],0x10
6449 ; MIPS32: lui [[T10]],0xff00
6450 ; MIPS32: ori [[T10]],[[T10]],0xffff
6451 ; MIPS32: and [[T7]],[[T7]],[[T10]]
6452 ; MIPS32: or [[T4]],[[T4]],[[T7]]
6453 ; MIPS32: srl [[T12:.*]],a3,0x18
6454 ; MIPS32: andi [[T12]],[[T12]],0x1
6455 ; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
6456 ; MIPS32: andi [[T13]],[[T13]],0x1
6457 ; MIPS32: sll [[T12]],[[T12]],0x1f
6458 ; MIPS32: sll [[T13]],[[T13]],0x1f
6459 ; MIPS32: sltu [[T12]],[[T12]],[[T13]]
6460 ; MIPS32: srl [[T12]],[[T12]],0x18
6461 ; MIPS32: sll [[T4]],[[T4]],0x8
6462 ; MIPS32: srl [[T4]],[[T4]],0x8
6463 ; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
497 } 6464 }
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