[SubZero] Implement Fcmp, ICmp, Cast and Select for vector type

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 201 matching lines @@
   }
 }
 
 uint32_t TargetMIPS32::getStackAlignment() const {
   return MIPS32_STACK_ALIGNMENT_BYTES;
 }
 
 void TargetMIPS32::genTargetHelperCallFor(Inst *Instr) {
   constexpr bool NoTailCall = false;
   constexpr bool IsTargetHelperCall = true;
 

[Jim Stichnoth, 2016/10/14 13:43:37]

Would be nice to factor out Dest queries to the top here, something like:

Variable *Dest = Instr->getDest();
const Type DestTy = Dest ? Dest->getType() : IceType_void;

[jaydeep.patil, 2016/10/15 03:47:57]

Done.

   switch (Instr->getKind()) {
   default:
     return;
+  case Inst::Select: {
+    Variable *Dest = Instr->getDest();
+    if (isVectorType(Dest->getType())) {
+      Operand *SrcT = llvm::cast<InstSelect>(Instr)->getTrueOperand();
+      Operand *SrcF = llvm::cast<InstSelect>(Instr)->getFalseOperand();
+      Operand *Cond = llvm::cast<InstSelect>(Instr)->getCondition();
+      Variable *T = Func->makeVariable(Dest->getType());
+      auto *Undef = ConstantUndef::create(Ctx, Dest->getType());
+      Context.insert<InstAssign>(T, Undef);
+      auto *VarVecOn32 = llvm::dyn_cast<VariableVecOn32>(T);

[Jim Stichnoth, 2016/10/14 13:43:37]

Use llvm::cast<> since the next statement assumes the result is non-nullptr.

[jaydeep.patil, 2016/10/15 03:47:57]

Done.

+      VarVecOn32->initVecElement(Func);
+      for (SizeT I = 0; I < typeNumElements(Dest->getType()); ++I) {
+        auto *Index = Ctx->getConstantInt32(I);
+        auto *OpC = Func->makeVariable(typeElementType(Cond->getType()));
+        Context.insert<InstExtractElement>(OpC, Cond, Index);
+        auto *OpT = Func->makeVariable(typeElementType(T->getType()));

[Jim Stichnoth, 2016/10/14 13:43:37]

I would use DestTy instead of T->getType() just to make it a bit more clear.

[jaydeep.patil, 2016/10/15 03:47:56]

Done.

+        Context.insert<InstExtractElement>(OpT, SrcT, Index);
+        auto *OpF = Func->makeVariable(typeElementType(T->getType()));
+        Context.insert<InstExtractElement>(OpF, SrcF, Index);
+        auto *Dst = Func->makeVariable(typeElementType(Dest->getType()));
+        Variable *DestT = Func->makeVariable(Dest->getType());
+        Context.insert<InstSelect>(Dst, OpC, OpT, OpF);
+        Context.insert<InstInsertElement>(DestT, T, Dst, Index);
+        T = DestT;
+      }
+      Context.insert<InstAssign>(Dest, T);
+      Instr->setDeleted();
+    }
+    return;
+  }
+  case Inst::Fcmp: {
+    Variable *Dest = Instr->getDest();
+    if (isVectorType(Dest->getType())) {
+      InstFcmp::FCond Cond = llvm::cast<InstFcmp>(Instr)->getCondition();
+      Operand *Src0 = Instr->getSrc(0);
+      Operand *Src1 = Instr->getSrc(1);
+      Variable *T = Func->makeVariable(IceType_v4f32);
+      auto *Undef = ConstantUndef::create(Ctx, IceType_v4f32);
+      Context.insert<InstAssign>(T, Undef);
+      auto *VarVecOn32 = llvm::dyn_cast<VariableVecOn32>(T);
+      VarVecOn32->initVecElement(Func);
+      for (SizeT I = 0; I < typeNumElements(IceType_v4f32); ++I) {
+        auto *Index = Ctx->getConstantInt32(I);
+        auto *Op0 = Func->makeVariable(IceType_f32);
+        Context.insert<InstExtractElement>(Op0, Src0, Index);
+        auto *Op1 = Func->makeVariable(IceType_f32);
+        Context.insert<InstExtractElement>(Op1, Src1, Index);
+        auto *Dst = Func->makeVariable(IceType_f32);
+        Variable *DestT = Func->makeVariable(IceType_v4f32);
+        Context.insert<InstFcmp>(Cond, Dst, Op0, Op1);
+        Context.insert<InstInsertElement>(DestT, T, Dst, Index);
+        T = DestT;
+      }
+      Context.insert<InstAssign>(Dest, T);
+      Instr->setDeleted();
+    }
+    return;
+  }
+  case Inst::Icmp: {
+    Variable *Dest = Instr->getDest();
+    const Type DetType = Dest->getType();
+    if (isVectorType(DetType)) {
+      InstIcmp::ICond Cond = llvm::cast<InstIcmp>(Instr)->getCondition();
+      Operand *Src0 = Instr->getSrc(0);
+      Operand *Src1 = Instr->getSrc(1);
+      const Type SrcType = Src0->getType();
+      Variable *T = Func->makeVariable(DetType);
+      auto *Undef = ConstantUndef::create(Ctx, DetType);
+      Context.insert<InstAssign>(T, Undef);
+      auto *VarVecOn32 = llvm::dyn_cast<VariableVecOn32>(T);
+      VarVecOn32->initVecElement(Func);
+      for (SizeT I = 0; I < typeNumElements(SrcType); ++I) {
+        auto *Index = Ctx->getConstantInt32(I);
+        auto *Op0 = Func->makeVariable(typeElementType(SrcType));
+        Context.insert<InstExtractElement>(Op0, Src0, Index);
+        auto *Op1 = Func->makeVariable(typeElementType(SrcType));
+        Context.insert<InstExtractElement>(Op1, Src1, Index);
+        auto *Dst = Func->makeVariable(typeElementType(DetType));
+        Variable *DestT = Func->makeVariable(DetType);
+        Context.insert<InstIcmp>(Cond, Dst, Op0, Op1);
+        Context.insert<InstInsertElement>(DestT, T, Dst, Index);
+        T = DestT;
+      }
+      Context.insert<InstAssign>(Dest, T);
+      Instr->setDeleted();
+    }
+    return;
+  }
   case Inst::Arithmetic: {
     Variable *Dest = Instr->getDest();
     const Type DestTy = Dest->getType();
     const InstArithmetic::OpKind Op =
         llvm::cast<InstArithmetic>(Instr)->getOp();
     if (isVectorType(DestTy)) {
       scalarizeArithmetic(Op, Dest, Instr->getSrc(0), Instr->getSrc(1));
       Instr->setDeleted();
       return;
     }
@@ skipping 51 matching lines @@
     }
     llvm::report_fatal_error("Control flow should never have reached here.");
   }
   case Inst::Cast: {
     Variable *Dest = Instr->getDest();
     Operand *Src0 = Instr->getSrc(0);
     const Type DestTy = Dest->getType();
     const Type SrcTy = Src0->getType();
     auto *CastInstr = llvm::cast<InstCast>(Instr);
     const InstCast::OpKind CastKind = CastInstr->getCastKind();
+
+    if (isVectorType(Dest->getType())) {
+      Variable *T = Func->makeVariable(DestTy);
+      auto *VarVecOn32 = llvm::dyn_cast<VariableVecOn32>(T);
+      VarVecOn32->initVecElement(Func);
+      auto *Undef = ConstantUndef::create(Ctx, DestTy);
+      Context.insert<InstAssign>(T, Undef);
+      for (SizeT I = 0; I < typeNumElements(DestTy); ++I) {
+        auto *Index = Ctx->getConstantInt32(I);
+        auto *Op = Func->makeVariable(typeElementType(SrcTy));
+        Context.insert<InstExtractElement>(Op, Src0, Index);
+        auto *Dst = Func->makeVariable(typeElementType(DestTy));
+        Variable *DestT = Func->makeVariable(DestTy);
+        Context.insert<InstCast>(CastKind, Dst, Op);
+        Context.insert<InstInsertElement>(DestT, T, Dst, Index);
+        T = DestT;
+      }
+      Context.insert<InstAssign>(Dest, T);
+      Instr->setDeleted();
+      return;
+    }
+
     switch (CastKind) {
     default:
       return;
     case InstCast::Fptosi:
     case InstCast::Fptoui: {
       if ((DestTy != IceType_i32) && (DestTy != IceType_i64)) {
         return;
       }
       const bool DestIs32 = DestTy == IceType_i32;
       const bool DestIsSigned = CastKind == InstCast::Fptosi;
@@ skipping 131 matching lines @@
       Operand *Src0 = IntrinsicCall->getArg(0);
       GlobalString FabsFloat = Ctx->getGlobalString("llvm.fabs.f32");
       Operand *CallTarget = Ctx->getConstantExternSym(FabsFloat);
       GlobalString FabsVec = Ctx->getGlobalString("llvm.fabs.v4f32");
       bool BadIntrinsic = false;
       const Intrinsics::FullIntrinsicInfo *FullInfo =
           Ctx->getIntrinsicsInfo().find(FabsVec, BadIntrinsic);
       Intrinsics::IntrinsicInfo Info = FullInfo->Info;
 
       Variable *T = Func->makeVariable(IceType_v4f32);
+      auto *Undef = ConstantUndef::create(Ctx, IceType_v4f32);
+      Context.insert<InstAssign>(T, Undef);
       auto *VarVecOn32 = llvm::dyn_cast<VariableVecOn32>(T);
       VarVecOn32->initVecElement(Func);
-      Context.insert<InstFakeDef>(T);
 
-      for (SizeT i = 0; i < VarVecOn32->ElementsPerContainer; ++i) {
+      for (SizeT i = 0; i < typeNumElements(IceType_v4f32); ++i) {
         auto *Index = Ctx->getConstantInt32(i);
         auto *Op = Func->makeVariable(IceType_f32);
         Context.insert<InstExtractElement>(Op, Src0, Index);
         auto *Res = Func->makeVariable(IceType_f32);
         Variable *DestT = Func->makeVariable(IceType_v4f32);
         auto *Call =
             Context.insert<InstIntrinsicCall>(1, Res, CallTarget, Info);
         Call->addArg(Op);
         Context.insert<InstInsertElement>(DestT, T, Res, Index);
         T = DestT;
@@ skipping 609 matching lines @@
   TargetMIPS32::CallingConv CC;
 
   // For each register argument, replace Arg in the argument list with the home
   // register. Then generate an instruction in the prolog to copy the home
   // register to the assigned location of Arg.
   Context.init(Func->getEntryNode());
   Context.setInsertPoint(Context.getCur());
 
   // v4f32 is returned through stack. $4 is setup by the caller and passed as
   // first argument implicitly. Callee then copies the return vector at $4.
+  Variable *ImplicitRetVec = nullptr;
   if (isVectorFloatingType(Func->getReturnType())) {
-    Variable *ImplicitRetVec = Func->makeVariable(IceType_i32);
+    ImplicitRetVec = Func->makeVariable(IceType_i32);
     ImplicitRetVec->setName(Func, "ImplicitRet_v4f32");
     ImplicitRetVec->setIsArg();
     Args.insert(Args.begin(), ImplicitRetVec);
     setImplicitRet(ImplicitRetVec);
-    Context.insert<InstFakeDef>(ImplicitRetVec);
-    for (CfgNode *Node : Func->getNodes()) {
-      for (Inst &Instr : Node->getInsts()) {
-        if (llvm::isa<InstRet>(&Instr)) {
-          Context.setInsertPoint(Instr);
-          Context.insert<InstFakeUse>(ImplicitRetVec);
-          break;
-        }
-      }
-    }
-    Context.setInsertPoint(Context.getCur());
   }
 
   for (SizeT i = 0, E = Args.size(); i < E; ++i) {
     Variable *Arg = Args[i];
     Type Ty = Arg->getType();
     RegNumT RegNum;
     if (!CC.argInReg(Ty, i, &RegNum)) {
       continue;
     }
     Variable *RegisterArg = Func->makeVariable(Ty);
@@ skipping 33 matching lines @@
         RegisterArg64->initHiLo(Func);
         RegisterArg64->getLo()->setRegNum(
             RegNumT::fixme(RegMIPS32::get64PairFirstRegNum(RegNum)));
         RegisterArg64->getHi()->setRegNum(
             RegNumT::fixme(RegMIPS32::get64PairSecondRegNum(RegNum)));
       } break;
       }
     }
     Context.insert<InstAssign>(Arg, RegisterArg);
   }
+
+  // Insert fake use of ImplicitRet_v4f32 to keep it live
+  if (ImplicitRetVec) {
+    for (CfgNode *Node : Func->getNodes()) {
+      for (Inst &Instr : Node->getInsts()) {
+        if (llvm::isa<InstRet>(&Instr)) {
+          Context.setInsertPoint(Instr);
+          Context.insert<InstFakeUse>(ImplicitRetVec);
+          break;
+        }
+      }
+    }
+  }
 }
 
 Type TargetMIPS32::stackSlotType() { return IceType_i32; }
 
 // Helper function for addProlog().
 //
 // This assumes Arg is an argument passed on the stack. This sets the frame
 // offset for Arg and updates InArgsSizeBytes according to Arg's width. For an
 // I64 arg that has been split into Lo and Hi components, it calls itself
 // recursively on the components, taking care to handle Lo first because of the
@@ skipping 1044 matching lines @@
   // legalization into new variables, otherwise Om1 register allocation may fail
   // when it sees variables that are defined but not used.
   Type DestTy = Dest->getType();
   Operand *Src0 = legalizeUndef(Instr->getSrc(0));
   Operand *Src1 = legalizeUndef(Instr->getSrc(1));
   if (DestTy == IceType_i64) {
     lowerInt64Arithmetic(Instr, Instr->getDest(), Src0, Src1);
     return;
   }
   if (isVectorType(Dest->getType())) {
-    UnimplementedLoweringError(this, Instr);
+    llvm::report_fatal_error("Arithmetic: Destination type is vector");
     return;
   }
 
   Variable *T = makeReg(Dest->getType());
   Variable *Src0R = legalizeToReg(Src0);
   Variable *Src1R = legalizeToReg(Src1);
   constexpr uint32_t DivideByZeroTrapCode = 7;
 
   switch (Instr->getOp()) {
   case InstArithmetic::_num:
@@ skipping 127 matching lines @@
 }
 
 void TargetMIPS32::lowerAssign(const InstAssign *Instr) {
   Variable *Dest = Instr->getDest();
 
   if (Dest->isRematerializable()) {
     Context.insert<InstFakeDef>(Dest);
     return;
   }
 
+  // Source type may not be same as destination
+  if (isVectorType(Dest->getType())) {
+    Operand *Src0 = legalizeUndef(Instr->getSrc(0));
+    auto *DstVec = llvm::dyn_cast<VariableVecOn32>(Dest);
+    for (SizeT i = 0; i < DstVec->ContainersPerVector; ++i) {
+      auto *DCont = DstVec->getContainers()[i];
+      auto *SCont =
+          legalize(getOperandAtIndex(Src0, IceType_i32, i), Legal_Reg);
+      auto *TReg = makeReg(IceType_i32);
+      _mov(TReg, SCont);
+      _mov(DCont, TReg);
+    }
+    return;
+  }
   Operand *Src0 = Instr->getSrc(0);
   assert(Dest->getType() == Src0->getType());
   if (Dest->getType() == IceType_i64) {
     Src0 = legalizeUndef(Src0);
     Operand *Src0Lo = legalize(loOperand(Src0), Legal_Reg);
     Operand *Src0Hi = legalize(hiOperand(Src0), Legal_Reg);
     auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
     auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     auto *T_Lo = I32Reg(), *T_Hi = I32Reg();
     _mov(T_Lo, Src0Lo);
     _mov(DestLo, T_Lo);
     _mov(T_Hi, Src0Hi);
     _mov(DestHi, T_Hi);
     return;
   }
-  if (isVectorType(Dest->getType())) {
-    auto *DstVec = llvm::dyn_cast<VariableVecOn32>(Dest);
-    for (SizeT i = 0; i < DstVec->ElementsPerContainer; ++i) {
-      auto *DCont = DstVec->getContainers()[i];
-      auto *SCont =
-          legalize(getOperandAtIndex(Src0, IceType_i32, i), Legal_Reg);
-      auto *TReg = makeReg(IceType_i32);
-      _mov(TReg, SCont);
-      _mov(DCont, TReg);
-    }
-    return;
-  }
   Operand *SrcR;
   if (Dest->hasReg()) {
     // If Dest already has a physical register, then legalize the Src operand
     // into a Variable with the same register assignment.  This especially
     // helps allow the use of Flex operands.
     SrcR = legalize(Src0, Legal_Reg, Dest->getRegNum());
   } else {
     // Dest could be a stack operand. Since we could potentially need
     // to do a Store (and store can only have Register operands),
     // legalize this to a register.
@@ skipping 388 matching lines @@
       break;
     case IceType_v4i1:
     case IceType_v8i1:
     case IceType_v16i1:
     case IceType_v16i8:
     case IceType_v8i16:
     case IceType_v4i32: {
       ReturnReg = makeReg(Dest->getType(), RegMIPS32::Reg_V0);
       auto *RetVec = llvm::dyn_cast<VariableVecOn32>(ReturnReg);
       RetVec->initVecElement(Func);
-      for (SizeT i = 0; i < RetVec->ElementsPerContainer; ++i) {
+      for (SizeT i = 0; i < RetVec->ContainersPerVector; ++i) {
         auto *Var = RetVec->getContainers()[i];
         Var->setRegNum(RegNumT::fixme(RegMIPS32::Reg_V0 + i));
       }
       break;
     }
     case IceType_v4f32:
       ReturnReg = makeReg(IceType_i32, RegMIPS32::Reg_V0);
       break;
     }
   }
@@ skipping 70 matching lines @@
     }
   }
 
   if (Dest == nullptr)
     return;
 
   // Assign the result of the call to Dest.
   if (ReturnReg) {
     if (RetVecFloat) {
       auto *DestVecOn32 = llvm::cast<VariableVecOn32>(Dest);
-      for (SizeT i = 0; i < DestVecOn32->ElementsPerContainer; ++i) {
+      for (SizeT i = 0; i < DestVecOn32->ContainersPerVector; ++i) {
         auto *Var = DestVecOn32->getContainers()[i];
         OperandMIPS32Mem *Mem = OperandMIPS32Mem::create(
             Func, IceType_i32, RetVecFloat,
             llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(i * 4)));
         _lw(Var, Mem);
       }
     } else if (auto *RetVec = llvm::dyn_cast<VariableVecOn32>(ReturnReg)) {
       auto *DestVecOn32 = llvm::cast<VariableVecOn32>(Dest);
-      for (SizeT i = 0; i < DestVecOn32->ElementsPerContainer; ++i) {
+      for (SizeT i = 0; i < DestVecOn32->ContainersPerVector; ++i) {
         _mov(DestVecOn32->getContainers()[i], RetVec->getContainers()[i]);
       }
     } else if (ReturnRegHi) {
       assert(Dest->getType() == IceType_i64);
       auto *Dest64On32 = llvm::cast<Variable64On32>(Dest);
       Variable *DestLo = Dest64On32->getLo();
       Variable *DestHi = Dest64On32->getHi();
       _mov(DestLo, ReturnReg);
       _mov(DestHi, ReturnRegHi);
     } else {
@@ skipping 15 matching lines @@
   const uint32_t ShiftAmount =
       (Src0Ty == IceType_i1
            ? INT32_BITS - 1
            : INT32_BITS - (CHAR_BITS * typeWidthInBytes(Src0Ty)));
   const uint32_t Mask =
       (Src0Ty == IceType_i1
            ? 1
            : (1 << (CHAR_BITS * typeWidthInBytes(Src0Ty))) - 1);
 
   if (isVectorType(DestTy)) {
-    UnimplementedLoweringError(this, Instr);
+    llvm::report_fatal_error("Cast: Destination type is vector");
     return;
   }
   switch (CastKind) {
   default:
     Func->setError("Cast type not supported");
     return;
   case InstCast::Sext: {
     if (DestTy == IceType_i64) {
       auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
       auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
@@ skipping 142 matching lines @@
     UnimplementedLoweringError(this, Instr);
     break;
   }
   case InstCast::Bitcast: {
     Operand *Src0 = Instr->getSrc(0);
     if (DestTy == Src0->getType()) {
       auto *Assign = InstAssign::create(Func, Dest, Src0);
       lowerAssign(Assign);
       return;
     }
+    if (isVectorType(DestTy) || isVectorType(Src0->getType())) {
+      llvm::report_fatal_error(
+          "Bitcast: vector type should have been prelowered.");
+      return;
+    }
     switch (DestTy) {
     case IceType_NUM:
     case IceType_void:
       llvm::report_fatal_error("Unexpected bitcast.");
     case IceType_i1:
       UnimplementedLoweringError(this, Instr);
       break;
     case IceType_i8:
-      assert(Src0->getType() == IceType_v8i1);
-      llvm::report_fatal_error(
-          "i8 to v8i1 conversion should have been prelowered.");
+      UnimplementedLoweringError(this, Instr);
       break;
     case IceType_i16:
-      assert(Src0->getType() == IceType_v16i1);
-      llvm::report_fatal_error(
-          "i16 to v16i1 conversion should have been prelowered.");
-      break;
-    case IceType_v8i1:
-      assert(Src0->getType() == IceType_i8);
-      llvm::report_fatal_error(
-          "v8i1 to i8 conversion should have been prelowered.");
-      break;
-    case IceType_v16i1:
-      assert(Src0->getType() == IceType_i16);
-      llvm::report_fatal_error(
-          "v16i1 to i16 conversion should have been prelowered.");
+      UnimplementedLoweringError(this, Instr);
       break;
     default:
       UnimplementedLoweringError(this, Instr);
     }
     break;
   }
   }
 }
 
 void TargetMIPS32::lowerExtractElement(const InstExtractElement *Instr) {
   Variable *Dest = Instr->getDest();
   const Type DestTy = Dest->getType();
   Operand *Src1 = Instr->getSrc(1);
   if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src1)) {
     const uint32_t Index = Imm->getValue();
     Variable *TDest = makeReg(DestTy);
     Variable *TReg = makeReg(DestTy);
     auto *Src0 = legalizeUndef(Instr->getSrc(0));
     auto *Src0R = llvm::dyn_cast<VariableVecOn32>(Src0);
     // Number of elements in each container
     uint32_t ElemPerCont =
-        typeNumElements(Src0->getType()) / Src0R->ElementsPerContainer;
+        typeNumElements(Src0->getType()) / Src0R->ContainersPerVector;
     auto *SrcE = Src0R->getContainers()[Index / ElemPerCont];
     // Position of the element in the container
     uint32_t PosInCont = Index % ElemPerCont;
     if (ElemPerCont == 1) {
       _mov(TDest, SrcE);
     } else if (ElemPerCont == 2) {
       switch (PosInCont) {
       case 0:
         _andi(TDest, SrcE, 0xffff);
         break;
@@ skipping 19 matching lines @@
         break;
       case 3:
         _srl(TDest, SrcE, 24);
         break;
       default:
         llvm::report_fatal_error("ExtractElement: Invalid PosInCont");
         break;
       }
     }
     if (typeElementType(Src0R->getType()) == IceType_i1) {
-      _andi(TReg, TDest, 0x1);
-      _mov(Dest, TReg);
+      Variable *TReg1 = makeReg(DestTy);
+      _andi(TReg1, TDest, 0x1);
+      _mov(Dest, TReg1);
     } else {
       _mov(Dest, TDest);
     }
     return;
   }
   llvm::report_fatal_error("ExtractElement requires a constant index");
 }
 
 void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
   Variable *Dest = Instr->getDest();
   if (isVectorType(Dest->getType())) {
-    UnimplementedLoweringError(this, Instr);
+    llvm::report_fatal_error("Fcmp: Destination type is vector");
     return;
   }
 
   auto *Src0 = Instr->getSrc(0);
   auto *Src1 = Instr->getSrc(1);
   auto *Zero = getZero();
 
   InstFcmp::FCond Cond = Instr->getCondition();
-  auto *DestR = makeReg(Dest->getType());
+  auto *DestR = makeReg(IceType_i32);
   auto *Src0R = legalizeToReg(Src0);
   auto *Src1R = legalizeToReg(Src1);
   const Type Src0Ty = Src0->getType();
 
   Operand *FCC0 = OperandMIPS32FCC::create(getFunc(), OperandMIPS32FCC::FCC0);
 
   switch (Cond) {
   default: {
     UnimplementedLoweringError(this, Instr);
     return;
@@ skipping 317 matching lines @@
 
 void TargetMIPS32::lowerIcmp(const InstIcmp *Instr) {
   auto *Src0 = Instr->getSrc(0);
   auto *Src1 = Instr->getSrc(1);
   if (Src0->getType() == IceType_i64) {
     lower64Icmp(Instr);
     return;
   }
   Variable *Dest = Instr->getDest();
   if (isVectorType(Dest->getType())) {
-    UnimplementedLoweringError(this, Instr);
+    llvm::report_fatal_error("Icmp: Destination type is vector");
     return;
   }
   InstIcmp::ICond Cond = Instr->getCondition();
   auto *Src0R = legalizeToReg(Src0);
   auto *Src1R = legalizeToReg(Src1);
   const Type Src0Ty = Src0R->getType();
   const uint32_t ShAmt = INT32_BITS - getScalarIntBitWidth(Src0->getType());
   Variable *Src0RT = I32Reg();
   Variable *Src1RT = I32Reg();
 
@@ skipping 85 matching lines @@
   }
 }
 
 void TargetMIPS32::lowerInsertElement(const InstInsertElement *Instr) {
   Variable *Dest = Instr->getDest();
   const Type DestTy = Dest->getType();
   Operand *Src2 = Instr->getSrc(2);
   if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src2)) {
     const uint32_t Index = Imm->getValue();
     // Vector to insert in
-    auto *Src0 = Instr->getSrc(0);
+    auto *Src0 = legalizeUndef(Instr->getSrc(0));
     auto *Src0R = llvm::dyn_cast<VariableVecOn32>(Src0);
     // Number of elements in each container
     uint32_t ElemPerCont =
-        typeNumElements(Src0->getType()) / Src0R->ElementsPerContainer;
+        typeNumElements(Src0->getType()) / Src0R->ContainersPerVector;
     // Source Element
     auto *SrcE = Src0R->getContainers()[Index / ElemPerCont];
-    Context.insert<InstFakeDef>(SrcE);
     // Dest is a vector
     auto *VDest = llvm::dyn_cast<VariableVecOn32>(Dest);
     VDest->initVecElement(Func);
     // Temp vector variable
     auto *TDest = makeReg(DestTy);
     auto *TVDest = llvm::dyn_cast<VariableVecOn32>(TDest);
     TVDest->initVecElement(Func);
     // Destination element
     auto *DstE = TVDest->getContainers()[Index / ElemPerCont];
     // Element to insert
     auto *Src1R = legalizeToReg(Instr->getSrc(1));
     auto *TReg1 = makeReg(Src1R->getType());
     auto *TReg2 = makeReg(Src1R->getType());
     auto *TReg3 = makeReg(Src1R->getType());
     auto *TReg4 = makeReg(Src1R->getType());
     auto *TReg5 = makeReg(Src1R->getType());
     // Position of the element in the container
     uint32_t PosInCont = Index % ElemPerCont;
     // Load source vector in a temporary vector
-    for (SizeT i = 0; i < TVDest->ElementsPerContainer; ++i) {
+    for (SizeT i = 0; i < TVDest->ContainersPerVector; ++i) {
       auto *DCont = TVDest->getContainers()[i];
       // Do not define DstE as we are going to redefine it
       if (DCont == DstE)
         continue;
       auto *SCont = Src0R->getContainers()[i];
       auto *TReg = makeReg(IceType_i32);
       _mov(TReg, SCont);
       _mov(DCont, TReg);
     }
     // Insert the element
@@ skipping 522 matching lines @@
 
   Func->resetCurrentNode();
   if (Func->isVerbose(IceV_AddrOpt)) {
     OstreamLocker _(Func->getContext());
     Ostream &Str = Func->getContext()->getStrDump();
     Str << "\nAddress mode formation:\t";
     LdSt->dumpDecorated(Func);
   }
 
   if (isVectorType(Ty)) {
-    UnimplementedError(getFlags());
     return nullptr;
   }
 
   auto *BaseVar = llvm::dyn_cast<Variable>(Base);
   if (BaseVar == nullptr)
     return nullptr;
 
   const VariablesMetadata *VMetadata = Func->getVMetadata();
   const Inst *Reason = nullptr;
 
@@ skipping 122 matching lines @@
       Context.insert<InstFakeUse>(V1);
       Context.insert<InstFakeUse>(A0);
       Context.insert<InstFakeUse>(A1);
       break;
     }
     case IceType_v4f32: {
       auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(Src0);
       Reg = getImplicitRet();
       auto *RegT = legalizeToReg(Reg);
       // Return the vector through buffer in implicit argument a0
-      for (SizeT i = 0; i < SrcVec->ElementsPerContainer; ++i) {
+      for (SizeT i = 0; i < SrcVec->ContainersPerVector; ++i) {
         OperandMIPS32Mem *Mem = OperandMIPS32Mem::create(
             Func, IceType_f32, RegT,
             llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(i * 4)));
         Variable *Var = legalizeToReg(SrcVec->getContainers()[i]);
         _sw(Var, Mem);
       }
       Variable *V0 = makeReg(IceType_i32, RegMIPS32::Reg_V0);
       _mov(V0, Reg); // move v0,a0
       Context.insert<InstFakeUse>(Reg);
       Context.insert<InstFakeUse>(V0);
       break;
     }
     default:
       llvm::report_fatal_error("Ret: Invalid type.");
       break;
     }
   }
   _ret(getPhysicalRegister(RegMIPS32::Reg_RA), Reg);
 }
 
 void TargetMIPS32::lowerSelect(const InstSelect *Instr) {
   Variable *Dest = Instr->getDest();
   const Type DestTy = Dest->getType();
 
   if (isVectorType(DestTy)) {
-    UnimplementedLoweringError(this, Instr);
+    llvm::report_fatal_error("Select: Destination type is vector");
     return;
   }
 
   Variable *DestR = nullptr;
   Variable *DestHiR = nullptr;
   Variable *SrcTR = nullptr;
   Variable *SrcTHiR = nullptr;
   Variable *SrcFR = nullptr;
   Variable *SrcFHiR = nullptr;
 
@@ skipping 51 matching lines @@
   Type Ty = NewAddr->getType();
 
   if (Ty == IceType_i64) {
     Value = legalizeUndef(Value);
     Variable *ValueHi = legalizeToReg(hiOperand(Value));
     Variable *ValueLo = legalizeToReg(loOperand(Value));
     _sw(ValueHi, llvm::cast<OperandMIPS32Mem>(hiOperand(NewAddr)));
     _sw(ValueLo, llvm::cast<OperandMIPS32Mem>(loOperand(NewAddr)));
   } else if (isVectorType(Value->getType())) {
     auto *DataVec = llvm::dyn_cast<VariableVecOn32>(Value);
-    for (SizeT i = 0; i < DataVec->ElementsPerContainer; ++i) {
+    for (SizeT i = 0; i < DataVec->ContainersPerVector; ++i) {
       auto *DCont = legalizeToReg(DataVec->getContainers()[i]);
       auto *MCont = llvm::cast<OperandMIPS32Mem>(
           getOperandAtIndex(NewAddr, IceType_i32, i));
       _sw(DCont, MCont);
     }
   } else {
     Variable *ValueR = legalizeToReg(Value);
     _sw(ValueR, NewAddr);
   }
 }
@@ skipping 453 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice