[SubZero] Legalize load, store for MIPS post lower

tests_lit/llvm2ice_tests/mips-legalization.ll

+; This file checks support for legalization in MIPS.
+
+; RUN: %if --need=target_MIPS32 --need=allow_dump \

[Jim Stichnoth, 2016/10/13 17:15:29]

Better to remove both instances of --need=allow_dump and add a line near the
top:

; REQUIRES: allow_dump

The --need=allow_dump is if you have a mix of filetype=asm and filetype=obj
tests, e.g. for different targets, but that should never be the case in this
test file.

[jaydeep.patil, 2016/10/14 04:40:43]

Done.

+; RUN:   --command %p2i --filetype=asm --assemble --disassemble \
+; RUN:   --target mips32 -i %s --args -O2 --skip-unimplemented \

[Jim Stichnoth, 2016/10/13 17:15:30]

If possible, remove --skip-unimplemented and -allow-externally-defined-symbol.

[jaydeep.patil, 2016/10/14 04:40:43]

Done.
We are also planning to remove --skip-unimplemented from all lit-tests for MIPS.

+; RUN:   -allow-externally-defined-symbols \
+; RUN:   | %if --need=target_MIPS32 --need=allow_dump \
+; RUN:     --command FileCheck --check-prefix MIPS32 %s
+
+define internal i32 @legalization(i32 %a, i32 %b, i32 %c, i32 %d,
+                                  i32 %e, i32 %f) {
+entry:
+  %a.addr.i8 = alloca i8, i32 4, align 4
+  %b.addr.i8 = alloca i8, i32 4, align 4
+  %c.addr.i8 = alloca i8, i32 4, align 4
+  %d.addr.i8 = alloca i8, i32 4, align 4
+  %e.addr.i8 = alloca i8, i32 4, align 4
+  %f.addr.i8 = alloca i8, i32 4, align 4
+  %r1.i8 = alloca i8, i32 4, align 4
+  %r2.i8 = alloca i8, i32 4, align 4
+  %r3.i8 = alloca i8, i32 4, align 4
+  %a.addr = bitcast i8* %a.addr.i8 to i32*
+  %b.addr = bitcast i8* %b.addr.i8 to i32*
+  %c.addr = bitcast i8* %c.addr.i8 to i32*
+  %d.addr = bitcast i8* %d.addr.i8 to i32*
+  %e.addr = bitcast i8* %e.addr.i8 to i32*
+  %f.addr = bitcast i8* %f.addr.i8 to i32*
+  %r1 = bitcast i8* %r1.i8 to i32*
+  %r2 = bitcast i8* %r2.i8 to i32*
+  %r3 = bitcast i8* %r3.i8 to i32*
+  store i32 %a, i32* %a.addr, align 1
+  store i32 %b, i32* %b.addr, align 1
+  store i32 %c, i32* %c.addr, align 1
+  store i32 %d, i32* %d.addr, align 1
+  store i32 %e, i32* %e.addr, align 1
+  store i32 %f, i32* %f.addr, align 1
+  %0 = load i32, i32* %a.addr, align 1
+  %1 = load i32, i32* %f.addr, align 1
+  %add1 = add nsw i32 %0, %1

[Jim Stichnoth, 2016/10/13 17:15:29]

"nsw" is not part of the PNaCl bitcode ABI, so that kind of stands out here. 
(The %p2i script probably strips it, and/or the Subzero bitcode parser ignores
it, but still.)

There is an undocumented pydir/build-pnacl-ir.py script that may be helpful
here, if you're starting from a .c file.

[jaydeep.patil, 2016/10/14 04:40:43]

Done.
Used pydir/build-pnacl-ir.py script to generate the .ll file.

+  store i32 %add1, i32* %r1, align 1
+  %2 = load i32, i32* %b.addr, align 1
+  %3 = load i32, i32* %e.addr, align 1
+  %add2 = add nsw i32 %2, %3
+  store i32 %add2, i32* %r2, align 1
+  %4 = load i32, i32* %r1, align 1
+  %5 = load i32, i32* %r2, align 1
+  %add3 = add nsw i32 %4, %5
+  store i32 %add3, i32* %r3, align 1
+  %6 = load i32, i32* %r3, align 1
+  ret i32 %6
+}
+; MIPS32-LABEL: legalization
+; MIPS32: addiu sp,sp,-48

[Jim Stichnoth, 2016/10/13 17:15:29]

I would be a bit cautious about assuming specific stack frame sizes or stack
offsets.  It can cause extra hardship if someone modifies/improves stack layout,
register allocation, alloca address rematerialization, etc.

But, it might be less of a pain to fix that when it happens, compared to making
the test fully general today, so it's your call...

[jaydeep.patil, 2016/10/14 04:40:43]

Acknowledged.
The pre-colored registers (a0-a3 and v0) are for arguments and return value.
Change in register allocation would not change these registers for MIPS32.
Temporaries are checked using macros. However, we need to get back to this case
whenever we change/optimize the stack layout.

+; MIPS32: lw [[ARG_E:.*]],64(sp)
+; MIPS32: lw [[ARG_F:.*]],68(sp)
+; MIPS32: sw a0,0(sp)
+; MIPS32: sw a1,4(sp)
+; MIPS32: sw a2,8(sp)
+; MIPS32: sw a3,12(sp)
+; MIPS32: sw [[ARG_E]],16(sp)
+; MIPS32: sw [[ARG_F]],20(sp)
+; MIPS32: lw [[TMP_A:.*]],0(sp)
+; MIPS32: lw [[TMP_F:.*]],20(sp)
+; MIPS32: addu [[ADD1:.*]],[[TMP_A]],[[TMP_F]]
+; MIPS32: sw [[ADD1]],24(sp)
+; MIPS32: lw [[TMP_B:.*]],4(sp)
+; MIPS32: lw [[TMP_E:.*]],16(sp)
+; MIPS32: addu [[ADD2:.*]],[[TMP_B]],[[TMP_E]]
+; MIPS32: sw [[ADD2]],28(sp)
+; MIPS32: lw [[TMP_ADD1:.*]],24(sp)
+; MIPS32: lw [[TMP_ADD2:.*]],28(sp)
+; MIPS32: addu [[ADD3:.*]],[[TMP_ADD1]],[[TMP_ADD2]]
+; MIPS32: sw [[ADD3]],32(sp)
+; MIPS32: lw v0,32(sp)
+; MIPS32: addiu sp,sp,48
+; MIPS32: jr ra