[Turbofan] Add concept of FP register aliasing on ARM 32.

src/register-configuration.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_COMPILER_REGISTER_CONFIGURATION_H_
 #define V8_COMPILER_REGISTER_CONFIGURATION_H_
 
 #include "src/base/macros.h"
 #include "src/globals.h"
 #include "src/machine-type.h"
@@ skipping 18 matching lines @@
 
   // Default RegisterConfigurations for the target architecture.
   // TODO(X87): This distinction in RegisterConfigurations is temporary
   // until x87 TF supports all of the registers that Crankshaft does.
   static const RegisterConfiguration* Crankshaft();
   static const RegisterConfiguration* Turbofan();
 
   RegisterConfiguration(int num_general_registers, int num_double_registers,
                         int num_allocatable_general_registers,
                         int num_allocatable_double_registers,
-                        int num_allocatable_aliased_double_registers,
                         const int* allocatable_general_codes,
                         const int* allocatable_double_codes,
                         AliasingKind fp_aliasing_kind,
                         char const* const* general_names,
                         char const* const* float_names,
                         char const* const* double_names,
                         char const* const* simd128_names);
 
   int num_general_registers() const { return num_general_registers_; }
   int num_float_registers() const { return num_float_registers_; }
   int num_double_registers() const { return num_double_registers_; }
   int num_simd128_registers() const { return num_simd128_registers_; }
   int num_allocatable_general_registers() const {
     return num_allocatable_general_registers_;
   }
   int num_allocatable_float_registers() const {
     return num_allocatable_float_registers_;
   }
   int num_allocatable_double_registers() const {
     return num_allocatable_double_registers_;
   }
-  // TODO(bbudge): This is a temporary work-around required because our
-  // register allocator does not yet support the aliasing of single/double
-  // registers on ARM.
-  int num_allocatable_aliased_double_registers() const {
-    return num_allocatable_aliased_double_registers_;
-  }
   int num_allocatable_simd128_registers() const {
     return num_allocatable_simd128_registers_;
   }
   AliasingKind fp_aliasing_kind() const { return fp_aliasing_kind_; }
   int32_t allocatable_general_codes_mask() const {
     return allocatable_general_codes_mask_;
   }
   int32_t allocatable_double_codes_mask() const {
     return allocatable_double_codes_mask_;
   }
@@ skipping 59 matching lines @@
                   MachineRepresentation other_rep, int other_index) const;
 
  private:
   const int num_general_registers_;
   int num_float_registers_;
   const int num_double_registers_;
   int num_simd128_registers_;
   int num_allocatable_general_registers_;
   int num_allocatable_float_registers_;
   int num_allocatable_double_registers_;
-  int num_allocatable_aliased_double_registers_;
   int num_allocatable_simd128_registers_;
   int32_t allocatable_general_codes_mask_;
   int32_t allocatable_float_codes_mask_;
   int32_t allocatable_double_codes_mask_;
   int32_t allocatable_simd128_codes_mask_;
   const int* allocatable_general_codes_;
   int allocatable_float_codes_[kMaxFPRegisters];
   const int* allocatable_double_codes_;
   int allocatable_simd128_codes_[kMaxFPRegisters];
   AliasingKind fp_aliasing_kind_;
   char const* const* general_register_names_;
   char const* const* float_register_names_;
   char const* const* double_register_names_;
   char const* const* simd128_register_names_;
 };
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_COMPILER_REGISTER_CONFIGURATION_H_