[Turbofan] Add concept of FP register aliasing on ARM 32.

src/compiler/instruction.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/common-operator.h"
 #include "src/compiler/graph.h"
 #include "src/compiler/instruction.h"
 #include "src/compiler/schedule.h"
 #include "src/compiler/state-values-utils.h"
 
@@ skipping 46 matching lines @@
     case kOverflow:
     case kNotOverflow:
     case kUnorderedEqual:
     case kUnorderedNotEqual:
       return condition;
   }
   UNREACHABLE();
   return condition;
 }
 
-bool InstructionOperand::InterferesWith(const InstructionOperand& that) const {
-  return EqualsCanonicalized(that);
+bool InstructionOperand::InterferesWith(const InstructionOperand& other) const {
+  if (kSimpleFPAliasing || !this->IsFPLocationOperand() ||
+      !other.IsFPLocationOperand())
+    return EqualsCanonicalized(other);
+  // Aliasing is complex and both operands are fp locations.
+  const LocationOperand& loc = *LocationOperand::cast(this);
+  const LocationOperand& other_loc = LocationOperand::cast(other);
+  LocationOperand::LocationKind kind = loc.location_kind();
+  LocationOperand::LocationKind other_kind = other_loc.location_kind();
+  if (kind != other_kind) return false;
+  MachineRepresentation rep = loc.representation();
+  MachineRepresentation other_rep = other_loc.representation();
+  if (rep == other_rep) return EqualsCanonicalized(other);
+  if (kind == LocationOperand::REGISTER) {
+    // FP register-register interference.
+    return GetRegConfig()->AreAliases(rep, loc.register_code(), other_rep,
+                                      other_loc.register_code());
+  } else {
+    // FP slot-slot interference. Slots of different FP reps can alias because
+    // the gap resolver may break a move into 2 or 4 equivalent smaller moves.
+    DCHECK_EQ(LocationOperand::STACK_SLOT, kind);
+    int index_hi = loc.index();
+    const int kBaseRep = static_cast<int>(MachineRepresentation::kFloat32);
+    int index_lo = index_hi - (1 << (static_cast<int>(rep) - kBaseRep)) + 1;
+    int other_index_hi = other_loc.index();
+    int other_index_lo =
+        other_index_hi - (1 << (static_cast<int>(other_rep) - kBaseRep)) + 1;
+    return !(other_index_hi < index_lo || index_hi < other_index_lo);
+  }
+  return false;
 }
 
 void InstructionOperand::Print(const RegisterConfiguration* config) const {
   OFStream os(stdout);
   PrintableInstructionOperand wrapper;
   wrapper.register_configuration_ = config;
   wrapper.op_ = *this;
   os << wrapper << std::endl;
 }
 
@@ skipping 146 matching lines @@
 }
 
 
 bool ParallelMove::IsRedundant() const {
   for (MoveOperands* move : *this) {
     if (!move->IsRedundant()) return false;
   }
   return true;
 }
 
-
-MoveOperands* ParallelMove::PrepareInsertAfter(MoveOperands* move) const {
+void ParallelMove::PrepareInsertAfter(
+    MoveOperands* move, ZoneVector<MoveOperands*>* to_eliminate) const {
+  bool no_aliasing =
+      kSimpleFPAliasing || !move->destination().IsFPLocationOperand();
   MoveOperands* replacement = nullptr;
-  MoveOperands* to_eliminate = nullptr;
+  MoveOperands* eliminated = nullptr;
   for (MoveOperands* curr : *this) {
     if (curr->IsEliminated()) continue;
     if (curr->destination().EqualsCanonicalized(move->source())) {
       DCHECK(!replacement);
       replacement = curr;
-      if (to_eliminate != nullptr) break;
-    } else if (curr->destination().EqualsCanonicalized(move->destination())) {
-      DCHECK(!to_eliminate);
-      to_eliminate = curr;
-      if (replacement != nullptr) break;
+      if (no_aliasing && eliminated != nullptr) break;
+    } else if (curr->destination().InterferesWith(move->destination())) {
+      eliminated = curr;
+      to_eliminate->push_back(curr);

[georgia.kouveli, 2016/10/12 17:38:41]

If the representation of "move" is narrower than the representation of "curr",
shouldn't this split "curr" like in the gap resolver instead of removing it?

I'm thinking of the case where the existing parallel move contains the move:
D1 -> D0
and you want to add:
S4 -> S0
where eliminating D1->D0 and just keeping S4->S0 doesn't have the same semantics
as performing S4->S0 after D1->D0.

The "if" case (destination interfering with source) seems more complicated, you
could have:
D1 -> D0
and add:
S0 -> S4
or you could have:
S4 -> S0
and add:
D0 -> D1
in both cases the source of the added move overlaps with the destination of an
existing one, but the existing parallel move won't be changed, if I am reading
this correctly.

Is there some guarantee that these cases don't happen? If yes, I think a comment
would be useful!

[bbudge, 2016/10/12 23:07:17]

I don't think splitting is needed here in either case.

If move's destination interferes with curr's destination, that means there is no
longer a double in that register as far as the register allocator is concerned.
So it doesn't matter what's in the remaining fragment (or fragments in the case
of SIMD registers.)

If move's source interferes with curr's destination (but has a different
representation), we don't want to chain those moves together. This combination
should never occur though. It implies that curr's destination is both double and
float, which is impossible.

I hope this makes sense and I'm not missing anything in my analysis. I did add
some comments to make this a little clearer.

+      if (no_aliasing && replacement != nullptr) break;
     }
   }
-  DCHECK_IMPLIES(replacement == to_eliminate, replacement == nullptr);
   if (replacement != nullptr) move->set_source(replacement->source());
-  return to_eliminate;
 }
 
-
 ExplicitOperand::ExplicitOperand(LocationKind kind, MachineRepresentation rep,
                                  int index)
     : LocationOperand(EXPLICIT, kind, rep, index) {
   DCHECK_IMPLIES(kind == REGISTER && !IsFloatingPoint(rep),
                  GetRegConfig()->IsAllocatableGeneralCode(index));
   DCHECK_IMPLIES(kind == REGISTER && rep == MachineRepresentation::kFloat32,
                  GetRegConfig()->IsAllocatableFloatCode(index));
   DCHECK_IMPLIES(kind == REGISTER && (rep == MachineRepresentation::kFloat64),
                  GetRegConfig()->IsAllocatableDoubleCode(index));
 }
@@ skipping 769 matching lines @@
   for (int i = 0; i < code.InstructionBlockCount(); i++) {
     printable_block.block_ = code.InstructionBlockAt(RpoNumber::FromInt(i));
     os << printable_block;
   }
   return os;
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8