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Side by Side Diff: runtime/vm/instructions_mips.cc

Issue 2404973002: Switchable call scheduling. (Closed)
Patch Set: . Created 4 years, 2 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_MIPS. 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_MIPS.
6 #if defined(TARGET_ARCH_MIPS) 6 #if defined(TARGET_ARCH_MIPS)
7 7
8 #include "vm/constants_mips.h" 8 #include "vm/constants_mips.h"
9 #include "vm/cpu.h" 9 #include "vm/cpu.h"
10 #include "vm/instructions.h" 10 #include "vm/instructions.h"
(...skipping 209 matching lines...) Expand 10 before | Expand all | Expand 10 after
220 SwitchableCallPattern::SwitchableCallPattern(uword pc, const Code& code) 220 SwitchableCallPattern::SwitchableCallPattern(uword pc, const Code& code)
221 : object_pool_(ObjectPool::Handle(code.GetObjectPool())), 221 : object_pool_(ObjectPool::Handle(code.GetObjectPool())),
222 data_pool_index_(-1), 222 data_pool_index_(-1),
223 target_pool_index_(-1) { 223 target_pool_index_(-1) {
224 ASSERT(code.ContainsInstructionAt(pc)); 224 ASSERT(code.ContainsInstructionAt(pc));
225 // Last instruction: jalr t9. 225 // Last instruction: jalr t9.
226 ASSERT(*(reinterpret_cast<uword*>(pc) - 1) == 0); // Delay slot. 226 ASSERT(*(reinterpret_cast<uword*>(pc) - 1) == 0); // Delay slot.
227 ASSERT(*(reinterpret_cast<uword*>(pc) - 2) == 0x0320f809); 227 ASSERT(*(reinterpret_cast<uword*>(pc) - 2) == 0x0320f809);
228 228
229 Register reg; 229 Register reg;
230 uword stub_load_end = 230 uword data_load_end =
231 InstructionPattern::DecodeLoadWordFromPool(pc - 3 * Instr::kInstrSize, 231 InstructionPattern::DecodeLoadWordFromPool(pc - 2 * Instr::kInstrSize,
232 &reg, 232 &reg,
233 &target_pool_index_); 233 &data_pool_index_);
234 ASSERT(reg == S5);
235 InstructionPattern::DecodeLoadWordFromPool(data_load_end - Instr::kInstrSize,
236 &reg,
237 &target_pool_index_);
234 ASSERT(reg == CODE_REG); 238 ASSERT(reg == CODE_REG);
235 InstructionPattern::DecodeLoadWordFromPool(stub_load_end,
236 &reg,
237 &data_pool_index_);
238 ASSERT(reg == S5);
239 } 239 }
240 240
241 241
242 RawObject* SwitchableCallPattern::data() const { 242 RawObject* SwitchableCallPattern::data() const {
243 return object_pool_.ObjectAt(data_pool_index_); 243 return object_pool_.ObjectAt(data_pool_index_);
244 } 244 }
245 245
246 246
247 RawCode* SwitchableCallPattern::target() const { 247 RawCode* SwitchableCallPattern::target() const {
248 return reinterpret_cast<RawCode*>( 248 return reinterpret_cast<RawCode*>(
(...skipping 21 matching lines...) Expand all
270 bool ReturnPattern::IsValid() const { 270 bool ReturnPattern::IsValid() const {
271 Instr* jr = Instr::At(pc_); 271 Instr* jr = Instr::At(pc_);
272 return (jr->OpcodeField() == SPECIAL) && 272 return (jr->OpcodeField() == SPECIAL) &&
273 (jr->FunctionField() == JR) && 273 (jr->FunctionField() == JR) &&
274 (jr->RsField() == RA); 274 (jr->RsField() == RA);
275 } 275 }
276 276
277 } // namespace dart 277 } // namespace dart
278 278
279 #endif // defined TARGET_ARCH_MIPS 279 #endif // defined TARGET_ARCH_MIPS
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