Adds simulator debugger and Stop to arm64.

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 308 matching lines @@
   friend class Assembler;
 };
 
 
 class Assembler : public ValueObject {
  public:
   explicit Assembler(bool use_far_branches = false);
   ~Assembler() { }
 
   void PopRegister(Register r) {
-    UNIMPLEMENTED();
+    Pop(r);
   }
 
   void Drop(intptr_t stack_elements) {
-    UNIMPLEMENTED();
+    add(SP, SP, Operand(stack_elements * kWordSize));
   }
 
   void Bind(Label* label);
 
   // Misc. functionality
   intptr_t CodeSize() const { return buffer_.Size(); }
   intptr_t prologue_offset() const { return prologue_offset_; }
 
   // Count the fixups that produce a pointer offset, without processing
   // the fixups.  On ARM64 there are no pointers in code.
@@ skipping 201 matching lines @@
   void br(Register rn) {
     EmitUnconditionalBranchRegOp(BR, rn);
   }
   void blr(Register rn) {
     EmitUnconditionalBranchRegOp(BLR, rn);
   }
   void ret(Register rn = R30) {
     EmitUnconditionalBranchRegOp(RET, rn);
   }
 
+  // Exceptions.
+  void hlt(uint16_t imm) {
+    EmitExceptionGenOp(HLT, imm);
+  }
+
   // Aliases.
   void mov(Register rd, Register rn) {
     if ((rd == SP) || (rn == SP)) {
       add(rd, rn, Operand(0));
     } else {
       orr(rd, ZR, Operand(rn));
     }
   }
   void mvn(Register rd, Register rm) {
     orr(rd, ZR, Operand(rm));
   }
   void neg(Register rd, Register rm) {
     sub(rd, ZR, Operand(rm));
   }
   void negs(Register rd, Register rm) {
     subs(rd, ZR, Operand(rm));
   }
   void mul(Register rd, Register rn, Register rm) {
     madd(rd, rn, rm, ZR);
   }
   void Push(Register reg) {
     str(reg, Address(SP, -1 * kWordSize, Address::PreIndex));
   }
   void Pop(Register reg) {
     ldr(reg, Address(SP, 1 * kWordSize, Address::PostIndex));
   }
+  void tst(Register rn, Operand o) {
+    ands(ZR, rn, o);
+  }
+  void tsti(Register rn, uint64_t imm) {
+    andis(ZR, rn, imm);
+  }
 
   // Object pool, loading from pool, etc.
   void LoadPoolPointer(Register pp) {
     const intptr_t object_pool_pc_dist =
       Instructions::HeaderSize() - Instructions::object_pool_offset() +
       CodeSize();
     // PP <- Read(PC - object_pool_pc_dist).
     ldr(pp, Address::PC(-object_pool_pc_dist));
   }
 
@@ skipping 214 matching lines @@
       label->LinkTo(position);
     }
   }
 
   void EmitUnconditionalBranchRegOp(UnconditionalBranchRegOp op, Register rn) {
     const int32_t encoding =
         op | (static_cast<int32_t>(rn) << kRnShift);
     Emit(encoding);
   }
 
+  void EmitExceptionGenOp(ExceptionGenOp op, uint16_t imm) {
+    const int32_t encoding =
+        op | (static_cast<int32_t>(imm) << kImm16Shift);
+    Emit(encoding);
+  }
+
   void EmitMoveWideOp(MoveWideOp op, Register rd, uint16_t imm, int hw_idx,
                       OperandSize sz) {
     ASSERT((hw_idx >= 0) && (hw_idx <= 3));
     ASSERT((sz == kDoubleWord) || (sz == kWord));
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(rd) << kRdShift) |
         (static_cast<int32_t>(hw_idx) << kHWShift) |
         (static_cast<int32_t>(imm) << kImm16Shift);
@@ skipping 67 matching lines @@
     Emit(encoding);
   }
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_