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Unified Diff: test/unittests/compiler/instruction-sequence-unittest.h

Issue 2400513002: [Turbofan] Allow FP operands and vregs in InstructionSequenceTest. (Closed)
Patch Set: Remove extra tests, will add back later. Created 4 years, 2 months ago
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Index: test/unittests/compiler/instruction-sequence-unittest.h
diff --git a/test/unittests/compiler/instruction-sequence-unittest.h b/test/unittests/compiler/instruction-sequence-unittest.h
index 956f5d55b939095722dc849400bf2ff2f7697594..1aa552a1cc3d3a069ef2a0c2fd752a936e21cff1 100644
--- a/test/unittests/compiler/instruction-sequence-unittest.h
+++ b/test/unittests/compiler/instruction-sequence-unittest.h
@@ -19,14 +19,18 @@ class InstructionSequenceTest : public TestWithIsolateAndZone {
public:
static const int kDefaultNRegs = 8;
static const int kNoValue = kMinInt;
+ static const MachineRepresentation kNoRep = MachineRepresentation::kNone;
+ static const MachineRepresentation kFloat64 = MachineRepresentation::kFloat64;
typedef RpoNumber Rpo;
struct VReg {
VReg() : value_(kNoValue) {}
VReg(PhiInstruction* phi) : value_(phi->virtual_register()) {} // NOLINT
- explicit VReg(int value) : value_(value) {}
+ explicit VReg(int value, MachineRepresentation rep = kNoRep)
+ : value_(value), rep_(rep) {}
int value_;
+ MachineRepresentation rep_ = kNoRep;
};
typedef std::pair<VReg, VReg> VRegPair;
@@ -47,43 +51,64 @@ class InstructionSequenceTest : public TestWithIsolateAndZone {
};
struct TestOperand {
- TestOperand() : type_(kInvalid), vreg_(), value_(kNoValue) {}
- TestOperand(TestOperandType type, int imm)
- : type_(type), vreg_(), value_(imm) {}
+ TestOperand() : type_(kInvalid), vreg_(), value_(kNoValue), rep_(kNoRep) {}
+ explicit TestOperand(TestOperandType type)
+ : type_(type), vreg_(), value_(kNoValue), rep_(kNoRep) {}
+ // For tests that do register allocation.
TestOperand(TestOperandType type, VReg vreg, int value = kNoValue)
- : type_(type), vreg_(vreg), value_(value) {}
+ : type_(type), vreg_(vreg), value_(value), rep_(vreg.rep_) {}
+ // For immediates, constants, and tests that don't do register allocation.
+ TestOperand(TestOperandType type, int value,
+ MachineRepresentation rep = kNoRep)
+ : type_(type), vreg_(), value_(value), rep_(rep) {}
TestOperandType type_;
VReg vreg_;
int value_;
+ MachineRepresentation rep_;
};
- static TestOperand Same() { return TestOperand(kSameAsFirst, VReg()); }
+ static TestOperand Same() { return TestOperand(kSameAsFirst); }
static TestOperand ExplicitReg(int index) {
TestOperandType type = kExplicit;
- return TestOperand(type, VReg(), index);
+ return TestOperand(type, index);
+ }
+
+ static TestOperand ExplicitFPReg(int index,
+ MachineRepresentation rep = kFloat64) {
+ TestOperandType type = kExplicit;
+ return TestOperand(type, index, rep);
}
static TestOperand Reg(VReg vreg, int index = kNoValue) {
- TestOperandType type = kRegister;
- if (index != kNoValue) type = kFixedRegister;
+ TestOperandType type = (index == kNoValue) ? kRegister : kFixedRegister;
return TestOperand(type, vreg, index);
}
- static TestOperand Reg(int index = kNoValue) { return Reg(VReg(), index); }
+ static TestOperand Reg(int index = kNoValue,
+ MachineRepresentation rep = kNoRep) {
+ return Reg(VReg(kNoValue, rep), index);
+ }
+
+ static TestOperand FPReg(int index = kNoValue,
+ MachineRepresentation rep = kFloat64) {
+ return Reg(index, rep);
+ }
static TestOperand Slot(VReg vreg, int index = kNoValue) {
- TestOperandType type = kSlot;
- if (index != kNoValue) type = kFixedSlot;
+ TestOperandType type = (index == kNoValue) ? kSlot : kFixedSlot;
return TestOperand(type, vreg, index);
}
- static TestOperand Slot(int index = kNoValue) { return Slot(VReg(), index); }
+ static TestOperand Slot(int index = kNoValue,
+ MachineRepresentation rep = kNoRep) {
+ return Slot(VReg(kNoValue, rep), index);
+ }
static TestOperand Const(int index) {
CHECK_NE(kNoValue, index);
- return TestOperand(kConstant, VReg(), index);
+ return TestOperand(kConstant, index);
}
static TestOperand Use(VReg vreg) { return TestOperand(kNone, vreg); }
@@ -129,6 +154,8 @@ class InstructionSequenceTest : public TestWithIsolateAndZone {
InstructionSequenceTest();
void SetNumRegs(int num_general_registers, int num_double_registers);
+ int GetNumRegs(MachineRepresentation rep);
+ int GetAllocatableCode(int index, MachineRepresentation rep = kNoRep);
RegisterConfiguration* config();
InstructionSequence* sequence();
@@ -140,6 +167,14 @@ class InstructionSequenceTest : public TestWithIsolateAndZone {
TestOperand Imm(int32_t imm = 0);
VReg Define(TestOperand output_op);
VReg Parameter(TestOperand output_op = Reg()) { return Define(output_op); }
+ VReg FPParameter(MachineRepresentation rep = kFloat64) {
+ return Parameter(FPReg(kNoValue, rep));
+ }
+
+ MachineRepresentation GetCanonicalRep(TestOperand op) {
+ return IsFloatingPoint(op.rep_) ? op.rep_
+ : sequence()->DefaultRepresentation();
+ }
Instruction* Return(TestOperand input_op_0);
Instruction* Return(VReg vreg) { return Return(Reg(vreg, 0)); }
@@ -177,16 +212,21 @@ class InstructionSequenceTest : public TestWithIsolateAndZone {
TestOperand input_op_3 = TestOperand());
InstructionBlock* current_block() const { return current_block_; }
- int num_general_registers() const { return num_general_registers_; }
- int num_double_registers() const { return num_double_registers_; }
// Called after all instructions have been inserted.
void WireBlocks();
private:
- VReg NewReg() { return VReg(sequence()->NextVirtualRegister()); }
+ virtual bool DoesRegisterAllocation() const { return true; }
+
+ VReg NewReg(TestOperand op = TestOperand()) {
+ int vreg = sequence()->NextVirtualRegister();
+ if (IsFloatingPoint(op.rep_))
+ sequence()->MarkAsRepresentation(op.rep_, vreg);
+ return VReg(vreg, op.rep_);
+ }
- static TestOperand Invalid() { return TestOperand(kInvalid, VReg()); }
+ static TestOperand Invalid() { return TestOperand(kInvalid); }
Instruction* EmitBranch(TestOperand input_op);
Instruction* EmitFallThrough();
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