[Turbofan] Allow FP operands and vregs in InstructionSequenceTest.

test/unittests/compiler/move-optimizer-unittest.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/move-optimizer.h"
 #include "src/compiler/pipeline.h"
 #include "test/unittests/compiler/instruction-sequence-unittest.h"
 
 namespace v8 {
 namespace internal {
@@ skipping 43 matching lines @@
     move_optimizer.Run();
     if (FLAG_trace_turbo) {
       OFStream os(stdout);
       PrintableInstructionSequence printable = {config(), sequence()};
       os << "----- Instruction sequence after move optimization -----\n"
          << printable;
     }
   }
 
  private:
+  bool DoesRegisterAllocation() const override { return false; }
+
   InstructionOperand ConvertMoveArg(TestOperand op) {
     CHECK_EQ(kNoValue, op.vreg_.value_);
     CHECK_NE(kNoValue, op.value_);
     switch (op.type_) {
       case kConstant:
         return ConstantOperand(op.value_);
       case kFixedSlot:
         return AllocatedOperand(LocationOperand::STACK_SLOT,
                                 MachineRepresentation::kWord32, op.value_);
-      case kFixedRegister:
-        CHECK(0 <= op.value_ && op.value_ < num_general_registers());
-        return AllocatedOperand(LocationOperand::REGISTER,
-                                MachineRepresentation::kWord32, op.value_);
-      case kExplicit:
-        CHECK(0 <= op.value_ && op.value_ < num_general_registers());
-        return ExplicitOperand(LocationOperand::REGISTER,
-                               MachineRepresentation::kWord32, op.value_);
+      case kFixedRegister: {
+        MachineRepresentation rep = GetCanonicalRep(op);
+        CHECK(0 <= op.value_ && op.value_ < GetNumRegs(rep));
+        return AllocatedOperand(LocationOperand::REGISTER, rep, op.value_);
+      }
+      case kExplicit: {
+        MachineRepresentation rep = GetCanonicalRep(op);
+        CHECK(0 <= op.value_ && op.value_ < GetNumRegs(rep));
+        return ExplicitOperand(LocationOperand::REGISTER, rep, op.value_);
+      }
       default:
         break;
     }
     CHECK(false);
     return InstructionOperand();
   }
 };
 
 
 TEST_F(MoveOptimizerTest, RemovesRedundant) {
   StartBlock();
   auto first_instr = EmitNop();
+  auto last_instr = EmitNop();
+
   AddMove(first_instr, Reg(0), Reg(1));
-  auto last_instr = EmitNop();
   AddMove(last_instr, Reg(1), Reg(0));
+
+  AddMove(first_instr, FPReg(0), FPReg(1));
+  AddMove(last_instr, FPReg(1), FPReg(0));
+
   EndBlock(Last());
 
   Optimize();
 
   CHECK_EQ(0, NonRedundantSize(first_instr->parallel_moves()[0]));
   auto move = last_instr->parallel_moves()[0];
-  CHECK_EQ(1, NonRedundantSize(move));
+  CHECK_EQ(2, NonRedundantSize(move));
   CHECK(Contains(move, Reg(0), Reg(1)));
+  CHECK(Contains(move, FPReg(0), FPReg(1)));
 }
 
 
 TEST_F(MoveOptimizerTest, RemovesRedundantExplicit) {
-  int first_reg_index =
-      RegisterConfiguration::Turbofan()->GetAllocatableGeneralCode(0);
-  int second_reg_index =
-      RegisterConfiguration::Turbofan()->GetAllocatableGeneralCode(1);
+  int first_reg_index = GetAllocatableCode(0);
+  int second_reg_index = GetAllocatableCode(1);
 
   StartBlock();
   auto first_instr = EmitNop();
+  auto last_instr = EmitNop();
+
   AddMove(first_instr, Reg(first_reg_index), ExplicitReg(second_reg_index));
-  auto last_instr = EmitNop();
   AddMove(last_instr, Reg(second_reg_index), Reg(first_reg_index));
+
   EndBlock(Last());
 
   Optimize();
 
   CHECK_EQ(0, NonRedundantSize(first_instr->parallel_moves()[0]));
   auto move = last_instr->parallel_moves()[0];
   CHECK_EQ(1, NonRedundantSize(move));
   CHECK(Contains(move, Reg(first_reg_index), ExplicitReg(second_reg_index)));
 }
 
@@ skipping 50 matching lines @@
 TEST_F(MoveOptimizerTest, SimpleMergeCycle) {
   StartBlock();
   EndBlock(Branch(Imm(), 1, 2));
 
   StartBlock();
   EndBlock(Jump(2));
   auto gap_0 = LastInstruction();
   AddMove(gap_0, Reg(0), Reg(1));
   AddMove(LastInstruction(), Reg(1), Reg(0));
 
+  AddMove(gap_0, FPReg(0), FPReg(1));
+  AddMove(LastInstruction(), FPReg(1), FPReg(0));
+
   StartBlock();
   EndBlock(Jump(1));
   auto gap_1 = LastInstruction();
   AddMove(gap_1, Reg(0), Reg(1));
   AddMove(gap_1, Reg(1), Reg(0));
+  AddMove(gap_1, FPReg(0), FPReg(1));
+  AddMove(gap_1, FPReg(1), FPReg(0));
 
   StartBlock();
   EndBlock(Last());
 
   auto last = LastInstruction();
 
   Optimize();
 
   CHECK(gap_0->AreMovesRedundant());
   CHECK(gap_1->AreMovesRedundant());
   auto move = last->parallel_moves()[0];
-  CHECK_EQ(2, NonRedundantSize(move));
+  CHECK_EQ(4, NonRedundantSize(move));
   CHECK(Contains(move, Reg(0), Reg(1)));
   CHECK(Contains(move, Reg(1), Reg(0)));
+  CHECK(Contains(move, FPReg(0), FPReg(1)));
+  CHECK(Contains(move, FPReg(1), FPReg(0)));
 }
 
 
 TEST_F(MoveOptimizerTest, GapsCanMoveOverInstruction) {
   StartBlock();
   int const_index = 1;
   DefineConstant(const_index);
   Instruction* ctant_def = LastInstruction();
   AddMove(ctant_def, Reg(1), Reg(0));
 
@@ skipping 101 matching lines @@
   ParallelMove* b2_move = last_move_b2->parallel_moves()[0];
   CHECK_EQ(1, NonRedundantSize(b2_move));
   CHECK(Contains(b1_move, Reg(0), Reg(1)));
 }
 
 TEST_F(MoveOptimizerTest, ClobberedDestinationsAreEliminated) {
   StartBlock();
   EmitNop();
   Instruction* first_instr = LastInstruction();
   AddMove(first_instr, Reg(0), Reg(1));
-  EmitOI(Reg(1), 0, nullptr);
+  AddMove(first_instr, FPReg(0), FPReg(1));
+  EmitOOI(Reg(1), FPReg(1), 0, nullptr);
   Instruction* last_instr = LastInstruction();
   EndBlock();
   Optimize();
 
   ParallelMove* first_move = first_instr->parallel_moves()[0];
   CHECK_EQ(0, NonRedundantSize(first_move));
 
   ParallelMove* last_move = last_instr->parallel_moves()[0];
   CHECK_EQ(0, NonRedundantSize(last_move));
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8