Adds object pool, LoadImmediate, and LoadObject to ARM64.

runtime/vm/simulator_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include <math.h>  // for isnan.
 #include <setjmp.h>
 #include <stdlib.h>
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM64)
@@ skipping 854 matching lines @@
     }
   }
 
   // Do writeback.
   if (wb) {
     set_register(rn, wb_address, R31IsSP);
   }
 }
 
 
+void Simulator::DecodeLoadRegLiteral(Instr* instr) {
+  if ((instr->Bit(31) != 0) || (instr->Bit(29) != 0) ||
+      (instr->Bits(24, 3) != 0)) {
+    UnimplementedInstruction(instr);
+  }
+
+  const Register rt = instr->RtField();
+  const int64_t off = instr->SImm19Field() << 2;
+  const int64_t pc = reinterpret_cast<int64_t>(instr);
+  const int64_t address = pc + off;
+  const int64_t val = ReadX(address, instr);
+  if (instr->Bit(30)) {
+    // Format(instr, "ldrx 'rt, 'pcldr");
+    set_register(rt, val, R31IsZR);
+  } else {
+    // Format(instr, "ldrw 'rt, 'pcldr");
+    set_wregister(rt, static_cast<int32_t>(val), R31IsZR);
+  }
+}
+
+
 void Simulator::DecodeLoadStore(Instr* instr) {
   if (instr->IsLoadStoreRegOp()) {
     DecodeLoadStoreReg(instr);
+  } else if (instr->IsLoadRegLiteralOp()) {
+    DecodeLoadRegLiteral(instr);
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
 
 int64_t Simulator::ShiftOperand(uint8_t reg_size,
                                 int64_t value,
                                 Shift shift_type,
                                 uint8_t amount) {
@@ skipping 512 matching lines @@
   int64_t return_value;
   return_value = get_register(R0);
   return return_value;
 }
 
 }  // namespace dart
 
 #endif  // !defined(HOST_ARCH_ARM64)
 
 #endif  // defined TARGET_ARCH_ARM64