Adds object pool, LoadImmediate, and LoadObject to ARM64.

runtime/vm/disassembler_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM64.
 #if defined(TARGET_ARCH_ARM64)
 #include "platform/assert.h"
 
@@ skipping 67 matching lines @@
   buffer_[buffer_pos_] = '\0';
 }
 
 
 // These register names are defined in a way to match the native disassembler
 // formatting, except for register aliases ctx (r9) and pp (r10).
 // See for example the command "objdump -d <binary file>".
 static const char* reg_names[kNumberOfCpuRegisters] = {
   "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
   "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
-  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
-  "r24", "ip0", "ip1", "pp",  "ctx", "fp",  "lr",  "r31",
+  "ip0", "ip1", "r18", "r19", "r20", "r21", "r22", "r23",
+  "r24", "r25", "r26", "pp",  "ctx", "fp",  "lr",  "r31",
 };
 
 
 // Print the register name according to the active name converter.
 void ARM64Decoder::PrintRegister(int reg, R31Type r31t) {
   ASSERT(0 <= reg);
   ASSERT(reg < kNumberOfCpuRegisters);
   if (reg == 31) {
     const char* rstr = (r31t == R31IsZR) ? "zr" : "sp";
     Print(rstr);
@@ skipping 271 matching lines @@
                                  "0x%"Px64,
                                  imm);
       return ret;
     }
     case 'm': {
       ASSERT(STRING_STARTS_WITH(format, "memop"));
       PrintMemOperand(instr);
       return 5;
     }
     case 'p': {
-      ASSERT(STRING_STARTS_WITH(format, "pcrel"));
-      const int64_t immhi = instr->SImm19Field();
-      const int64_t immlo = instr->Bits(29, 2);
-      const int64_t off = (immhi << 2) | immlo;
-      const int64_t pc = reinterpret_cast<int64_t>(instr);
-      const int64_t dest = pc + off;
-      buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                 remaining_size_in_buffer(),
-                                 "0x%"Px64,
-                                 dest);
+      if (format[2] == 'a') {
+        ASSERT(STRING_STARTS_WITH(format, "pcadr"));
+        const int64_t immhi = instr->SImm19Field();
+        const int64_t immlo = instr->Bits(29, 2);
+        const int64_t off = (immhi << 2) | immlo;
+        const int64_t pc = reinterpret_cast<int64_t>(instr);
+        const int64_t dest = pc + off;
+        buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
+                                   remaining_size_in_buffer(),
+                                   "0x%"Px64,
+                                   dest);
+      } else {
+        ASSERT(STRING_STARTS_WITH(format, "pcldr"));
+        const int64_t off = instr->SImm19Field() << 2;
+        const int64_t pc = reinterpret_cast<int64_t>(instr);
+        const int64_t dest = pc + off;
+        buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
+                                   remaining_size_in_buffer(),
+                                   "0x%"Px64,
+                                   dest);
+      }
       return 5;
     }
     case 'r': {
       return FormatRegister(instr, format);
     }
     case 's': {  // 's: S flag.
       if (format[1] == 'h') {
         ASSERT(STRING_STARTS_WITH(format, "shift_op"));
         PrintShiftExtendRm(instr);
         return 8;
@@ skipping 90 matching lines @@
     return;
   }
   if (instr->Bit(22) == 1) {
     Format(instr, "ldr'sz 'rt, 'memop");
   } else {
     Format(instr, "str'sz 'rt, 'memop");
   }
 }
 
 
+void ARM64Decoder::DecodeLoadRegLiteral(Instr* instr) {
+  if ((instr->Bit(31) != 0) || (instr->Bit(29) != 0) ||
+      (instr->Bits(24, 3) != 0)) {
+    Unknown(instr);
+  }
+  if (instr->Bit(30)) {
+    Format(instr, "ldrx 'rt, 'pcldr");
+  } else {
+    Format(instr, "ldrw 'rt, 'pcldr");
+  }
+}
+
+
 void ARM64Decoder::DecodeAddSubImm(Instr* instr) {
   switch (instr->Bit(30)) {
     case 0: {
       if ((instr->RdField() == R31) && (instr->SFField())) {
         Format(instr, "cmni'sf 'rn, 'imm12s");
       } else {
         if (((instr->RdField() == R31) || (instr->RnField() == R31)) &&
             (instr->Imm12Field() == 0) && (instr->Bit(29) == 0)) {
           Format(instr, "mov'sf 'rd, 'rn");
         } else {
@@ skipping 40 matching lines @@
     default:
       Unknown(instr);
       break;
   }
 }
 
 
 void ARM64Decoder::DecodePCRel(Instr* instr) {
   const int op = instr->Bit(31);
   if (op == 0) {
-    Format(instr, "adr 'rd, 'pcrel");
+    Format(instr, "adr 'rd, 'pcadr");
   } else {
     Unknown(instr);
   }
 }
 
 
 void ARM64Decoder::DecodeDPImmediate(Instr* instr) {
   if (instr->IsMoveWideOp()) {
     DecodeMoveWide(instr);
   } else if (instr->IsAddSubImmOp()) {
@@ skipping 113 matching lines @@
     DecodeUnconditionalBranch(instr);
   } else {
     Unknown(instr);
   }
 }
 
 
 void ARM64Decoder::DecodeLoadStore(Instr* instr) {
   if (instr->IsLoadStoreRegOp()) {
     DecodeLoadStoreReg(instr);
+  } else if (instr->IsLoadRegLiteralOp()) {
+    DecodeLoadRegLiteral(instr);
   } else {
     Unknown(instr);
   }
 }
 
 
 void ARM64Decoder::DecodeAddSubShiftExt(Instr* instr) {
   switch (instr->Bit(30)) {
     case 0: {
       if ((instr->RdField() == R31) && (instr->SFField())) {
@@ skipping 187 matching lines @@
                                   human_buffer,
                                   sizeof(human_buffer),
                                   pc);
     pc += instruction_length;
   }
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM