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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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86 { 0x2A, BYTE_REG_OPER_OP_ORDER, "sub" }, | 86 { 0x2A, BYTE_REG_OPER_OP_ORDER, "sub" }, |
87 { 0x2B, REG_OPER_OP_ORDER, "sub" }, | 87 { 0x2B, REG_OPER_OP_ORDER, "sub" }, |
88 { 0x30, BYTE_OPER_REG_OP_ORDER, "xor" }, | 88 { 0x30, BYTE_OPER_REG_OP_ORDER, "xor" }, |
89 { 0x31, OPER_REG_OP_ORDER, "xor" }, | 89 { 0x31, OPER_REG_OP_ORDER, "xor" }, |
90 { 0x32, BYTE_REG_OPER_OP_ORDER, "xor" }, | 90 { 0x32, BYTE_REG_OPER_OP_ORDER, "xor" }, |
91 { 0x33, REG_OPER_OP_ORDER, "xor" }, | 91 { 0x33, REG_OPER_OP_ORDER, "xor" }, |
92 { 0x38, BYTE_OPER_REG_OP_ORDER, "cmp" }, | 92 { 0x38, BYTE_OPER_REG_OP_ORDER, "cmp" }, |
93 { 0x39, OPER_REG_OP_ORDER, "cmp" }, | 93 { 0x39, OPER_REG_OP_ORDER, "cmp" }, |
94 { 0x3A, BYTE_REG_OPER_OP_ORDER, "cmp" }, | 94 { 0x3A, BYTE_REG_OPER_OP_ORDER, "cmp" }, |
95 { 0x3B, REG_OPER_OP_ORDER, "cmp" }, | 95 { 0x3B, REG_OPER_OP_ORDER, "cmp" }, |
96 { 0x63, REG_OPER_OP_ORDER, "movsxlq" }, | 96 { 0x63, REG_OPER_OP_ORDER, "movsxl" }, |
97 { 0x84, BYTE_REG_OPER_OP_ORDER, "test" }, | 97 { 0x84, BYTE_REG_OPER_OP_ORDER, "test" }, |
98 { 0x85, REG_OPER_OP_ORDER, "test" }, | 98 { 0x85, REG_OPER_OP_ORDER, "test" }, |
99 { 0x86, BYTE_REG_OPER_OP_ORDER, "xchg" }, | 99 { 0x86, BYTE_REG_OPER_OP_ORDER, "xchg" }, |
100 { 0x87, REG_OPER_OP_ORDER, "xchg" }, | 100 { 0x87, REG_OPER_OP_ORDER, "xchg" }, |
101 { 0x88, BYTE_OPER_REG_OP_ORDER, "mov" }, | 101 { 0x88, BYTE_OPER_REG_OP_ORDER, "mov" }, |
102 { 0x89, OPER_REG_OP_ORDER, "mov" }, | 102 { 0x89, OPER_REG_OP_ORDER, "mov" }, |
103 { 0x8A, BYTE_REG_OPER_OP_ORDER, "mov" }, | 103 { 0x8A, BYTE_REG_OPER_OP_ORDER, "mov" }, |
104 { 0x8B, REG_OPER_OP_ORDER, "mov" }, | 104 { 0x8B, REG_OPER_OP_ORDER, "mov" }, |
105 { 0x8D, REG_OPER_OP_ORDER, "lea" }, | 105 { 0x8D, REG_OPER_OP_ORDER, "lea" }, |
106 { -1, UNSET_OP_ORDER, "" } | 106 { -1, UNSET_OP_ORDER, "" } |
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1885 for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) { | 1885 for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) { |
1886 fprintf(f, " "); | 1886 fprintf(f, " "); |
1887 } | 1887 } |
1888 fprintf(f, " %s\n", buffer.start()); | 1888 fprintf(f, " %s\n", buffer.start()); |
1889 } | 1889 } |
1890 } | 1890 } |
1891 | 1891 |
1892 } // namespace disasm | 1892 } // namespace disasm |
1893 | 1893 |
1894 #endif // V8_TARGET_ARCH_X64 | 1894 #endif // V8_TARGET_ARCH_X64 |
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