[wasm] Implement I32x4ReplaceLane, I32x4Add, I32x4Sub.

src/compiler/x64/code-generator-x64.cc

Index: src/compiler/x64/code-generator-x64.cc
diff --git a/src/compiler/x64/code-generator-x64.cc b/src/compiler/x64/code-generator-x64.cc
index 56cd3ea0258e7068c359d20b2141a4539ff04451..346159c4bc45d8e4ce1ecae69782c1849b70a60a 100644
--- a/src/compiler/x64/code-generator-x64.cc
+++ b/src/compiler/x64/code-generator-x64.cc
@@ -2084,6 +2084,32 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ Pextrd(i.OutputRegister(), i.InputSimd128Register(0), i.InputInt8(1));
       break;
     }
+    case kX64Int32x4ReplaceLane: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);
+      XMMRegister dst = i.OutputSimd128Register();
+      if (instr->InputAt(2)->IsRegister()) {
+        __ Pinsrd(i.InputSimd128Register(0), i.InputRegister(2),
+                  i.InputInt8(1));
+      } else {
+        __ Pinsrd(i.InputSimd128Register(0), i.InputOperand(2), i.InputInt8(1));
+      }
+      __ Movups(dst, i.InputSimd128Register(0));
+      break;
+    }
+    case kX64Int32x4Add: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);
+      XMMRegister dst = i.OutputSimd128Register();
+      __ addps(i.InputSimd128Register(0), i.InputSimd128Register(1));
+      __ Movups(dst, i.InputSimd128Register(0));
+      break;
+    }
+    case kX64Int32x4Sub: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);
+      XMMRegister dst = i.OutputSimd128Register();
+      __ subps(i.InputSimd128Register(0), i.InputSimd128Register(1));
+      __ Movups(dst, i.InputSimd128Register(0));
+      break;
+    }
     case kCheckedLoadInt8:
       ASSEMBLE_CHECKED_LOAD_INTEGER(movsxbl);
       break;