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Side by Side Diff: tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll

Issue 2384983002: Subzero: Remove --skip-unimplemented from ARM lit tests. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 2 months ago
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1 ; This tests each of the supported NaCl atomic instructions for every 1 ; This tests each of the supported NaCl atomic instructions for every
2 ; size allowed. 2 ; size allowed.
3 3
4 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ 4 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
5 ; RUN: -allow-externally-defined-symbols | FileCheck %s 5 ; RUN: -allow-externally-defined-symbols | FileCheck %s
6 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ 6 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
7 ; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=O2 %s 7 ; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=O2 %s
8 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \ 8 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
9 ; RUN: -allow-externally-defined-symbols | FileCheck %s 9 ; RUN: -allow-externally-defined-symbols | FileCheck %s
10 10
11 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \ 11 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \
12 ; RUN: --target arm32 -i %s --args -O2 --skip-unimplemented \ 12 ; RUN: --target arm32 -i %s --args -O2 \
13 ; RUN: -allow-externally-defined-symbols \ 13 ; RUN: -allow-externally-defined-symbols \
14 ; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \ 14 ; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \
15 ; RUN: --check-prefix=ARM32 15 ; RUN: --check-prefix=ARM32
16 16
17 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \ 17 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \
18 ; RUN: --target arm32 -i %s --args -O2 --skip-unimplemented \ 18 ; RUN: --target arm32 -i %s --args -O2 \
19 ; RUN: -allow-externally-defined-symbols \ 19 ; RUN: -allow-externally-defined-symbols \
20 ; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \ 20 ; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \
21 ; RUN: --check-prefix=ARM32O2 21 ; RUN: --check-prefix=ARM32O2
22 22
23 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \ 23 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \
24 ; RUN: --target arm32 -i %s --args -Om1 --skip-unimplemented \ 24 ; RUN: --target arm32 -i %s --args -Om1 \
25 ; RUN: -allow-externally-defined-symbols \ 25 ; RUN: -allow-externally-defined-symbols \
26 ; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \ 26 ; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \
27 ; RUN: --check-prefix=ARM32 27 ; RUN: --check-prefix=ARM32
28 28
29 declare i8 @llvm.nacl.atomic.load.i8(i8*, i32) 29 declare i8 @llvm.nacl.atomic.load.i8(i8*, i32)
30 declare i16 @llvm.nacl.atomic.load.i16(i16*, i32) 30 declare i16 @llvm.nacl.atomic.load.i16(i16*, i32)
31 declare i32 @llvm.nacl.atomic.load.i32(i32*, i32) 31 declare i32 @llvm.nacl.atomic.load.i32(i32*, i32)
32 declare i64 @llvm.nacl.atomic.load.i64(i64*, i32) 32 declare i64 @llvm.nacl.atomic.load.i64(i64*, i32)
33 declare void @llvm.nacl.atomic.store.i8(i8, i8*, i32) 33 declare void @llvm.nacl.atomic.store.i8(i8, i8*, i32)
34 declare void @llvm.nacl.atomic.store.i16(i16, i16*, i32) 34 declare void @llvm.nacl.atomic.store.i16(i16, i16*, i32)
(...skipping 1426 matching lines...) Expand 10 before | Expand all | Expand 10 after
1461 br i1 %cmp, label %done, label %body 1461 br i1 %cmp, label %done, label %body
1462 done: 1462 done:
1463 ret void 1463 ret void
1464 } 1464 }
1465 ; O2-LABEL: test_cmpxchg8b_regalloc 1465 ; O2-LABEL: test_cmpxchg8b_regalloc
1466 ;;; eax and some other register will be used in the cmpxchg instruction. 1466 ;;; eax and some other register will be used in the cmpxchg instruction.
1467 ; O2: lock cmpxchg8b QWORD PTR 1467 ; O2: lock cmpxchg8b QWORD PTR
1468 ;;; Make sure eax/ecx/edx/ebx aren't used again, e.g. as the induction variable. 1468 ;;; Make sure eax/ecx/edx/ebx aren't used again, e.g. as the induction variable.
1469 ; O2-NOT: ,{{eax|ecx|edx|ebx}} 1469 ; O2-NOT: ,{{eax|ecx|edx|ebx}}
1470 ; O2: pop ebx 1470 ; O2: pop ebx
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