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1 ; This tries to create variables with very large stack offsets. | 1 ; This tries to create variables with very large stack offsets. |
2 ; This requires a lot of variables/register pressure. To simplify this | 2 ; This requires a lot of variables/register pressure. To simplify this |
3 ; we assume poor register allocation from Om1, and a flag that forces | 3 ; we assume poor register allocation from Om1, and a flag that forces |
4 ; the frame to add K amount of unused stack for testing. | 4 ; the frame to add K amount of unused stack for testing. |
5 ; We only need to test ARM and other architectures which have limited space | 5 ; We only need to test ARM and other architectures which have limited space |
6 ; for specifying an offset within an instruction. | 6 ; for specifying an offset within an instruction. |
7 | 7 |
8 ; RUN: %if --need=target_ARM32 --need=allow_dump \ | 8 ; RUN: %if --need=target_ARM32 \ |
9 ; RUN: --command %p2i --filetype=asm --assemble --disassemble --target arm32 \ | 9 ; RUN: --command %p2i --filetype=obj --disassemble --target arm32 \ |
10 ; RUN: -i %s --args -Om1 --skip-unimplemented --test-stack-extra 4096 \ | 10 ; RUN: -i %s --args -Om1 --test-stack-extra 4096 \ |
11 ; RUN: -allow-externally-defined-symbols \ | 11 ; RUN: -allow-externally-defined-symbols \ |
12 ; RUN: | %if --need=target_ARM32 --need=allow_dump \ | 12 ; RUN: | %if --need=target_ARM32 \ |
13 ; RUN: --command FileCheck --check-prefix ARM32 %s | 13 ; RUN: --command FileCheck --check-prefix ARM32 %s |
14 | 14 |
15 declare i64 @dummy(i32 %t1, i32 %t2, i32 %t3, i64 %t4, i64 %t5) | 15 declare i64 @dummy(i32 %t1, i32 %t2, i32 %t3, i64 %t4, i64 %t5) |
16 | 16 |
17 ; Test a function that requires lots of stack (due to test flag), and uses | 17 ; Test a function that requires lots of stack (due to test flag), and uses |
18 ; SP as the base register (originally). | 18 ; SP as the base register (originally). |
19 define internal i64 @lotsOfStack(i32 %a, i32 %b, i32 %c, i32 %d) { | 19 define internal i64 @lotsOfStack(i32 %a, i32 %b, i32 %c, i32 %d) { |
20 entry: | 20 entry: |
21 %t1 = xor i32 %a, %b | 21 %t1 = xor i32 %a, %b |
22 %t2 = or i32 %c, %d | 22 %t2 = or i32 %c, %d |
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117 ; ARM32: b {{[a-f0-9]+}} | 117 ; ARM32: b {{[a-f0-9]+}} |
118 ; Now skip ahead to where the call in br_1 begins, to check how %t2 is used. | 118 ; Now skip ahead to where the call in br_1 begins, to check how %t2 is used. |
119 ; ARM32: movw ip, #4120 | 119 ; ARM32: movw ip, #4120 |
120 ; ARM32-NEXT: sub ip, fp, ip | 120 ; ARM32-NEXT: sub ip, fp, ip |
121 ; ARM32: ldr r2, [ip, #-4] | 121 ; ARM32: ldr r2, [ip, #-4] |
122 ; ARM32: bl {{.*}} dummy | 122 ; ARM32: bl {{.*}} dummy |
123 ; The call clobbers ip, so we need to re-create the base register. | 123 ; The call clobbers ip, so we need to re-create the base register. |
124 ; ARM32: movw ip, #4{{.*}} | 124 ; ARM32: movw ip, #4{{.*}} |
125 ; ARM32: b {{[a-f0-9]+}} | 125 ; ARM32: b {{[a-f0-9]+}} |
126 ; ARM32: bl {{.*}} dummy | 126 ; ARM32: bl {{.*}} dummy |
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