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1 ; This tries to be a comprehensive test of i64 operations, in | 1 ; This tries to be a comprehensive test of i64 operations, in |
2 ; particular the patterns for lowering i64 operations into constituent | 2 ; particular the patterns for lowering i64 operations into constituent |
3 ; i32 operations on x86-32. | 3 ; i32 operations on x86-32. |
4 | 4 |
5 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ | 5 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ |
6 ; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \ | 6 ; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \ |
7 ; RUN: | %if --need=target_X8632 --command FileCheck %s | 7 ; RUN: | %if --need=target_X8632 --command FileCheck %s |
8 | 8 |
9 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ | 9 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ |
10 ; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \ | 10 ; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \ |
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1293 ; ARM32-OM1: tst | 1293 ; ARM32-OM1: tst |
1294 ; ARM32: bne | 1294 ; ARM32: bne |
1295 ; ARM32: bl {{.*}} <func> | 1295 ; ARM32: bl {{.*}} <func> |
1296 ; ARM32: cmp | 1296 ; ARM32: cmp |
1297 ; ARM32: cmpeq | 1297 ; ARM32: cmpeq |
1298 ; ARM32-OM1: tst | 1298 ; ARM32-OM1: tst |
1299 ; ARM32: bne | 1299 ; ARM32: bne |
1300 ; ARM32: bl {{.*}} <func> | 1300 ; ARM32: bl {{.*}} <func> |
1301 ; ARM32: bx | 1301 ; ARM32: bx |
1302 | 1302 |
1303 ; MIPS32-LABEL: icmpEq64 | |
1304 ; MIPS32: xor [[T1:.*]],{{.*}},{{.*}} | |
1305 ; MIPS32: xor [[T2:.*]],{{.*}},{{.*}} | |
1306 ; MIPS32: or [[T3:.*]],[[T1]],[[T2]] | |
1307 ; MIPS32-O2: bnez [[T3]],{{.*}} | |
1308 ; MIPS32-OM1: sltiu [[T4:.*]],[[T3]],1 | |
1309 ; MIPS32-OM1: sw [[T4]],[[MEM:.*]] | |
Jim Stichnoth
2016/09/29 13:52:20
I am very impressed by the level of detail in thes
| |
1310 ; MIPS32-OM1: lb [[T5:.*]],[[MEM]] | |
1311 ; MIPS32-OM1: beqz [[T5]],{{.*}} | |
1312 ; MIPS32-OM1: b {{.*}} | |
1313 ; MIPS32: jal {{.*}} | |
1314 ; MIPS32-OM1: b {{.*}} | |
1315 ; MIPS32: xor [[T1:.*]],{{.*}},{{.*}} | |
1316 ; MIPS32: xor [[T2:.*]],{{.*}},{{.*}} | |
1317 ; MIPS32: or [[T3:.*]],[[T1]],[[T2]] | |
1318 ; MIPS32-O2: bnez [[T3]],{{.*}} | |
1319 ; MIPS32-OM1: sltiu [[T4:.*]],[[T3]],1 | |
1320 ; MIPS32-OM1: sw [[T4]],[[MEM:.*]] | |
1321 ; MIPS32-OM1: lb [[T5:.*]],[[MEM]] | |
1322 ; MIPS32-OM1: beqz [[T5]],{{.*}} | |
1323 ; MIPS32-OM1: b {{.*}} | |
1324 ; MIPS32: jal {{.*}} | |
1325 ; MIPS32-OM1: b {{.*}} | |
1326 | |
1303 declare void @func() | 1327 declare void @func() |
1304 | 1328 |
1305 define internal void @icmpNe64(i64 %a, i64 %b, i64 %c, i64 %d) { | 1329 define internal void @icmpNe64(i64 %a, i64 %b, i64 %c, i64 %d) { |
1306 entry: | 1330 entry: |
1307 %cmp = icmp ne i64 %a, %b | 1331 %cmp = icmp ne i64 %a, %b |
1308 br i1 %cmp, label %if.then, label %if.end | 1332 br i1 %cmp, label %if.then, label %if.end |
1309 | 1333 |
1310 if.then: ; preds = %entry | 1334 if.then: ; preds = %entry |
1311 call void @func() | 1335 call void @func() |
1312 br label %if.end | 1336 br label %if.end |
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1363 ; ARM32-OM1: bne | 1387 ; ARM32-OM1: bne |
1364 ; ARM32-O2: beq | 1388 ; ARM32-O2: beq |
1365 ; ARM32: bl {{.*}} <func> | 1389 ; ARM32: bl {{.*}} <func> |
1366 ; ARM32: cmp | 1390 ; ARM32: cmp |
1367 ; ARM32: cmpeq | 1391 ; ARM32: cmpeq |
1368 ; ARM32-OM1: tst | 1392 ; ARM32-OM1: tst |
1369 ; ARM32-OM1: bne | 1393 ; ARM32-OM1: bne |
1370 ; ARM32-O2: beq | 1394 ; ARM32-O2: beq |
1371 ; ARM32: bl | 1395 ; ARM32: bl |
1372 | 1396 |
1397 ; MIPS32-LABEL: icmpNe64 | |
1398 ; MIPS32: xor [[T1:.*]],{{.*}},{{.*}} | |
1399 ; MIPS32: xor [[T2:.*]],{{.*}},{{.*}} | |
1400 ; MIPS32: or [[T3:.*]],[[T1]],[[T2]] | |
1401 ; MIPS32-O2: beqz [[T3]],{{.*}} | |
1402 ; MIPS32-OM1: sltu [[T4:.*]],zero,[[T3]] | |
1403 ; MIPS32-OM1: sw [[T4]],[[MEM:.*]] | |
1404 ; MIPS32-OM1: lb [[T5:.*]],[[MEM]] | |
1405 ; MIPS32-OM1: beqz [[T5]],{{.*}} | |
1406 ; MIPS32-OM1: b {{.*}} | |
1407 ; MIPS32: jal {{.*}} | |
1408 ; MIPS32-OM1: b {{.*}} | |
1409 ; MIPS32: xor [[T1:.*]],{{.*}},{{.*}} | |
1410 ; MIPS32: xor [[T2:.*]],{{.*}},{{.*}} | |
1411 ; MIPS32: or [[T3:.*]],[[T1]],[[T2]] | |
1412 ; MIPS32-O2: beqz [[T3]],{{.*}} | |
1413 ; MIPS32-OM1: sltu [[T4:.*]],zero,[[T3]] | |
1414 ; MIPS32-OM1: sw [[T4]],[[MEM:.*]] | |
1415 ; MIPS32-OM1: lb [[T5:.*]],[[MEM]] | |
1416 ; MIPS32-OM1: beqz [[T5]],{{.*}} | |
1417 ; MIPS32-OM1: b {{.*}} | |
1418 ; MIPS32: jal {{.*}} | |
1419 ; MIPS32-OM1: b {{.*}} | |
1420 | |
1373 define internal void @icmpGt64(i64 %a, i64 %b, i64 %c, i64 %d) { | 1421 define internal void @icmpGt64(i64 %a, i64 %b, i64 %c, i64 %d) { |
1374 entry: | 1422 entry: |
1375 %cmp = icmp ugt i64 %a, %b | 1423 %cmp = icmp ugt i64 %a, %b |
1376 br i1 %cmp, label %if.then, label %if.end | 1424 br i1 %cmp, label %if.then, label %if.end |
1377 | 1425 |
1378 if.then: ; preds = %entry | 1426 if.then: ; preds = %entry |
1379 call void @func() | 1427 call void @func() |
1380 br label %if.end | 1428 br label %if.end |
1381 | 1429 |
1382 if.end: ; preds = %if.then, %entry | 1430 if.end: ; preds = %if.then, %entry |
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1417 ; ARM32-OM1: bne | 1465 ; ARM32-OM1: bne |
1418 ; ARM32-O2: bls | 1466 ; ARM32-O2: bls |
1419 ; ARM32: bl | 1467 ; ARM32: bl |
1420 ; ARM32: cmp | 1468 ; ARM32: cmp |
1421 ; ARM32: sbcs | 1469 ; ARM32: sbcs |
1422 ; ARM32-OM1: tst | 1470 ; ARM32-OM1: tst |
1423 ; ARM32-OM1: bne | 1471 ; ARM32-OM1: bne |
1424 ; ARM32-O2: bge | 1472 ; ARM32-O2: bge |
1425 ; ARM32: bl | 1473 ; ARM32: bl |
1426 | 1474 |
1475 ; MIPS32-LABEL: icmpGt64 | |
1476 ; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]] | |
1477 ; MIPS32-O2: sltu [[T2:.*]],[[B_HI]],[[A_HI]] | |
1478 ; MIPS32-O2: xori [[T3:.*]],[[T2]],0x1 | |
1479 ; MIPS32-O2: sltu [[T4:.*]],{{.*}},{{.*}} | |
1480 ; MIPS32-O2: xori [[T5:.*]],[[T4]],0x1 | |
1481 ; MIPS32-OM1: sltu [[T3:.*]],[[B_HI]],[[A_HI]] | |
1482 ; MIPS32-OM1: sltu [[T5:.*]],{{.*}},{{.*}} | |
1483 ; MIPS32: movz [[T3]],[[T5]],[[T1]] | |
1484 ; MIPS32-O2: bnez [[T3]],{{.*}} | |
1485 ; MIPS32-OM1: sw [[T3]],[[MEM:.*]] | |
1486 ; MIPS32-OM1: lb [[T6:.*]],[[MEM]] | |
1487 ; MIPS32-OM1: beqz [[T6]],{{.*}} | |
1488 ; MIPS32-OM1: b {{.*}} | |
1489 ; MIPS32: jal {{.*}} | |
1490 ; MIPS32-OM1: b {{.*}} | |
1491 ; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]] | |
1492 ; MIPS32-O2: slt [[T2:.*]],[[B_HI]],[[A_HI]] | |
1493 ; MIPS32-O2: xori [[T3:.*]],[[T2]],0x1 | |
1494 ; MIPS32-O2: sltu [[T4:.*]],{{.*}},{{.*}} | |
1495 ; MIPS32-O2: xori [[T5:.*]],[[T4]],0x1 | |
1496 ; MIPS32-OM1: slt [[T3:.*]],[[B_HI]],[[A_HI]] | |
1497 ; MIPS32-OM1: sltu [[T5:.*]],{{.*}},{{.*}} | |
1498 ; MIPS32: movz [[T3]],[[T5]],[[T1]] | |
1499 ; MIPS32-O2: bnez [[T3]],{{.*}} | |
1500 ; MIPS32-OM1: sw [[T3]],[[MEM:.*]] | |
1501 ; MIPS32-OM1: lb [[T6:.*]],[[MEM]] | |
1502 ; MIPS32-OM1: beqz [[T6]],{{.*}} | |
1503 ; MIPS32-OM1: b {{.*}} | |
1504 ; MIPS32: jal {{.*}} | |
1505 ; MIPS32-OM1: b {{.*}} | |
1506 | |
1427 define internal void @icmpGe64(i64 %a, i64 %b, i64 %c, i64 %d) { | 1507 define internal void @icmpGe64(i64 %a, i64 %b, i64 %c, i64 %d) { |
1428 entry: | 1508 entry: |
1429 %cmp = icmp uge i64 %a, %b | 1509 %cmp = icmp uge i64 %a, %b |
1430 br i1 %cmp, label %if.then, label %if.end | 1510 br i1 %cmp, label %if.then, label %if.end |
1431 | 1511 |
1432 if.then: ; preds = %entry | 1512 if.then: ; preds = %entry |
1433 call void @func() | 1513 call void @func() |
1434 br label %if.end | 1514 br label %if.end |
1435 | 1515 |
1436 if.end: ; preds = %if.then, %entry | 1516 if.end: ; preds = %if.then, %entry |
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1471 ; ARM32-OM1: bne | 1551 ; ARM32-OM1: bne |
1472 ; ARM32-O2: bcc | 1552 ; ARM32-O2: bcc |
1473 ; ARM32: bl | 1553 ; ARM32: bl |
1474 ; ARM32: cmp | 1554 ; ARM32: cmp |
1475 ; ARM32: sbcs | 1555 ; ARM32: sbcs |
1476 ; ARM32-OM1: tst | 1556 ; ARM32-OM1: tst |
1477 ; ARM32-OM1: bne | 1557 ; ARM32-OM1: bne |
1478 ; ARM32-O2: blt | 1558 ; ARM32-O2: blt |
1479 ; ARM32: bl | 1559 ; ARM32: bl |
1480 | 1560 |
1561 ; MIPS32-LABEL: icmpGe64 | |
1562 ; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]] | |
1563 ; MIPS32-OM1: sltu [[T2:.*]],[[A_HI]],[[B_HI]] | |
1564 ; MIPS32-OM1: xori [[T3:.*]],[[T2]],0x1 | |
1565 ; MIPS32-OM1: sltu [[T4:.*]],{{.*}},{{.*}} | |
1566 ; MIPS32-OM1: xori [[T5:.*]],[[T4]],0x1 | |
1567 ; MIPS32-O2: sltu [[T3:.*]],[[A_HI]],[[B_HI]] | |
1568 ; MIPS32-O2: sltu [[T5:.*]],{{.*}},{{.*}} | |
1569 ; MIPS32: movz [[T3]],[[T5]],[[T1]] | |
1570 ; MIPS32-O2: bnez [[T3]],{{.*}} | |
1571 ; MIPS32-OM1: sw [[T3]],[[MEM:.*]] | |
1572 ; MIPS32-OM1: lb [[T6:.*]],[[MEM]] | |
1573 ; MIPS32-OM1: beqz [[T6]],{{.*}} | |
1574 ; MIPS32-OM1: b {{.*}} | |
1575 ; MIPS32: jal {{.*}} | |
1576 ; MIPS32-OM1: b {{.*}} | |
1577 ; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]] | |
1578 ; MIPS32-OM1: slt [[T2:.*]],[[A_HI]],[[B_HI]] | |
1579 ; MIPS32-OM1: xori [[T3:.*]],[[T2]],0x1 | |
1580 ; MIPS32-OM1: sltu [[T4:.*]],{{.*}},{{.*}} | |
1581 ; MIPS32-OM1: xori [[T5:.*]],[[T4]],0x1 | |
1582 ; MIPS32-O2: slt [[T3:.*]],[[A_HI]],[[B_HI]] | |
1583 ; MIPS32-O2: sltu [[T5:.*]],{{.*}},{{.*}} | |
1584 ; MIPS32: movz [[T3]],[[T5]],[[T1]] | |
1585 ; MIPS32-O2: bnez [[T3]],{{.*}} | |
1586 ; MIPS32-OM1: sw [[T3]],[[MEM:.*]] | |
1587 ; MIPS32-OM1: lb [[T6:.*]],[[MEM]] | |
1588 ; MIPS32-OM1: beqz [[T6]],{{.*}} | |
1589 ; MIPS32-OM1: b {{.*}} | |
1590 ; MIPS32: jal {{.*}} | |
1591 ; MIPS32-OM1: b {{.*}} | |
1592 | |
1481 define internal void @icmpLt64(i64 %a, i64 %b, i64 %c, i64 %d) { | 1593 define internal void @icmpLt64(i64 %a, i64 %b, i64 %c, i64 %d) { |
1482 entry: | 1594 entry: |
1483 %cmp = icmp ult i64 %a, %b | 1595 %cmp = icmp ult i64 %a, %b |
1484 br i1 %cmp, label %if.then, label %if.end | 1596 br i1 %cmp, label %if.then, label %if.end |
1485 | 1597 |
1486 if.then: ; preds = %entry | 1598 if.then: ; preds = %entry |
1487 call void @func() | 1599 call void @func() |
1488 br label %if.end | 1600 br label %if.end |
1489 | 1601 |
1490 if.end: ; preds = %if.then, %entry | 1602 if.end: ; preds = %if.then, %entry |
(...skipping 34 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
1525 ; ARM32-OM1: bne | 1637 ; ARM32-OM1: bne |
1526 ; ARM32-O2: bcs | 1638 ; ARM32-O2: bcs |
1527 ; ARM32: bl | 1639 ; ARM32: bl |
1528 ; ARM32: cmp | 1640 ; ARM32: cmp |
1529 ; ARM32: sbcs | 1641 ; ARM32: sbcs |
1530 ; ARM32-OM1: tst | 1642 ; ARM32-OM1: tst |
1531 ; ARM32-OM1: bne | 1643 ; ARM32-OM1: bne |
1532 ; ARM32-O2: bge | 1644 ; ARM32-O2: bge |
1533 ; ARM32: bl | 1645 ; ARM32: bl |
1534 | 1646 |
1647 ; MIPS32-LABEL: icmpLt64 | |
1648 ; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]] | |
1649 ; MIPS32-O2: sltu [[T2:.*]],[[A_HI]],[[B_HI]] | |
1650 ; MIPS32-O2: xori [[T3:.*]],[[T2]],0x1 | |
1651 ; MIPS32-O2: sltu [[T4:.*]],{{.*}},{{.*}} | |
1652 ; MIPS32-O2: xori [[T5:.*]],[[T4]],0x1 | |
1653 ; MIPS32-OM1: sltu [[T3:.*]],[[A_HI]],[[B_HI]] | |
1654 ; MIPS32-OM1: sltu [[T5:.*]],{{.*}},{{.*}} | |
1655 ; MIPS32: movz [[T3]],[[T5]],[[T1]] | |
1656 ; MIPS32-O2: bnez [[T3]],{{.*}} | |
1657 ; MIPS32-OM1: sw [[T3]],[[MEM:.*]] | |
1658 ; MIPS32-OM1: lb [[T6:.*]],[[MEM]] | |
1659 ; MIPS32-OM1: beqz [[T6]],{{.*}} | |
1660 ; MIPS32-OM1: b {{.*}} | |
1661 ; MIPS32: jal {{.*}} | |
1662 ; MIPS32-OM1: b {{.*}} | |
1663 ; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]] | |
1664 ; MIPS32-O2: slt [[T2:.*]],[[A_HI]],[[B_HI]] | |
1665 ; MIPS32-O2: xori [[T3:.*]],[[T2]],0x1 | |
1666 ; MIPS32-O2: sltu [[T4:.*]],{{.*}},{{.*}} | |
1667 ; MIPS32-O2: xori [[T5:.*]],[[T4]],0x1 | |
1668 ; MIPS32-OM1: slt [[T3:.*]],[[A_HI]],[[B_HI]] | |
1669 ; MIPS32-OM1: sltu [[T5:.*]],{{.*}},{{.*}} | |
1670 ; MIPS32: movz [[T3]],[[T5]],[[T1]] | |
1671 ; MIPS32-O2: bnez [[T3]],{{.*}} | |
1672 ; MIPS32-OM1: sw [[T3]],[[MEM:.*]] | |
1673 ; MIPS32-OM1: lb [[T6:.*]],[[MEM]] | |
1674 ; MIPS32-OM1: beqz [[T6]],{{.*}} | |
1675 ; MIPS32-OM1: b {{.*}} | |
1676 ; MIPS32: jal {{.*}} | |
1677 ; MIPS32-OM1: b {{.*}} | |
1678 | |
1535 define internal void @icmpLe64(i64 %a, i64 %b, i64 %c, i64 %d) { | 1679 define internal void @icmpLe64(i64 %a, i64 %b, i64 %c, i64 %d) { |
1536 entry: | 1680 entry: |
1537 %cmp = icmp ule i64 %a, %b | 1681 %cmp = icmp ule i64 %a, %b |
1538 br i1 %cmp, label %if.then, label %if.end | 1682 br i1 %cmp, label %if.then, label %if.end |
1539 | 1683 |
1540 if.then: ; preds = %entry | 1684 if.then: ; preds = %entry |
1541 call void @func() | 1685 call void @func() |
1542 br label %if.end | 1686 br label %if.end |
1543 | 1687 |
1544 if.end: ; preds = %if.then, %entry | 1688 if.end: ; preds = %if.then, %entry |
(...skipping 34 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
1579 ; ARM32-OM1: bne | 1723 ; ARM32-OM1: bne |
1580 ; ARM32-O2: bhi | 1724 ; ARM32-O2: bhi |
1581 ; ARM32: bl | 1725 ; ARM32: bl |
1582 ; ARM32: cmp | 1726 ; ARM32: cmp |
1583 ; ARM32: sbcs | 1727 ; ARM32: sbcs |
1584 ; ARM32-OM1: tst | 1728 ; ARM32-OM1: tst |
1585 ; ARM32-OM1: bne | 1729 ; ARM32-OM1: bne |
1586 ; ARM32-O2: blt | 1730 ; ARM32-O2: blt |
1587 ; ARM32: bl | 1731 ; ARM32: bl |
1588 | 1732 |
1733 ; MIPS32-LABEL: icmpLe64 | |
1734 ; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]] | |
1735 ; MIPS32-OM1: sltu [[T2:.*]],[[B_HI]],[[A_HI]] | |
1736 ; MIPS32-OM1: xori [[T3:.*]],[[T2]],0x1 | |
1737 ; MIPS32-OM1: sltu [[T4:.*]],{{.*}},{{.*}} | |
1738 ; MIPS32-OM1: xori [[T5:.*]],[[T4]],0x1 | |
1739 ; MIPS32-O2: sltu [[T3:.*]],[[B_HI]],[[A_HI]] | |
1740 ; MIPS32-O2: sltu [[T5:.*]],{{.*}},{{.*}} | |
1741 ; MIPS32: movz [[T3]],[[T5]],[[T1]] | |
1742 ; MIPS32-O2: bnez [[T3]],{{.*}} | |
1743 ; MIPS32-OM1: sw [[T3]],[[MEM:.*]] | |
1744 ; MIPS32-OM1: lb [[T6:.*]],[[MEM]] | |
1745 ; MIPS32-OM1: beqz [[T6]],{{.*}} | |
1746 ; MIPS32-OM1: b {{.*}} | |
1747 ; MIPS32: jal {{.*}} | |
1748 ; MIPS32-OM1: b {{.*}} | |
1749 ; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]] | |
1750 ; MIPS32-OM1: slt [[T2:.*]],[[B_HI]],[[A_HI]] | |
1751 ; MIPS32-OM1: xori [[T3:.*]],[[T2]],0x1 | |
1752 ; MIPS32-OM1: sltu [[T4:.*]],{{.*}},{{.*}} | |
1753 ; MIPS32-OM1: xori [[T5:.*]],[[T4]],0x1 | |
1754 ; MIPS32-O2: slt [[T3:.*]],[[B_HI]],[[A_HI]] | |
1755 ; MIPS32-O2: sltu [[T5:.*]],{{.*}},{{.*}} | |
1756 ; MIPS32: movz [[T3]],[[T5]],[[T1]] | |
1757 ; MIPS32-O2: bnez [[T3]],{{.*}} | |
1758 ; MIPS32-OM1: sw [[T3]],[[MEM:.*]] | |
1759 ; MIPS32-OM1: lb [[T6:.*]],[[MEM]] | |
1760 ; MIPS32-OM1: beqz [[T6]],{{.*}} | |
1761 ; MIPS32-OM1: b {{.*}} | |
1762 ; MIPS32: jal {{.*}} | |
1763 ; MIPS32-OM1: b {{.*}} | |
1764 | |
1589 define internal i32 @icmpEq64Bool(i64 %a, i64 %b) { | 1765 define internal i32 @icmpEq64Bool(i64 %a, i64 %b) { |
1590 entry: | 1766 entry: |
1591 %cmp = icmp eq i64 %a, %b | 1767 %cmp = icmp eq i64 %a, %b |
1592 %cmp.ret_ext = zext i1 %cmp to i32 | 1768 %cmp.ret_ext = zext i1 %cmp to i32 |
1593 ret i32 %cmp.ret_ext | 1769 ret i32 %cmp.ret_ext |
1594 } | 1770 } |
1595 ; CHECK-LABEL: icmpEq64Bool | 1771 ; CHECK-LABEL: icmpEq64Bool |
1596 ; CHECK: jne | 1772 ; CHECK: jne |
1597 ; CHECK: je | 1773 ; CHECK: je |
1598 ; | 1774 ; |
(...skipping 630 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
2229 %s = lshr i64 %a, 40 | 2405 %s = lshr i64 %a, 40 |
2230 %t = trunc i64 %s to i32 | 2406 %t = trunc i64 %s to i32 |
2231 %r = sub i32 %t, 1 | 2407 %r = sub i32 %t, 1 |
2232 ret i32 %r | 2408 ret i32 %r |
2233 ; ARM32-LABEL: subOneToUpperAfterShift | 2409 ; ARM32-LABEL: subOneToUpperAfterShift |
2234 ; ARM32: subs | 2410 ; ARM32: subs |
2235 ; ARM32: sbc | 2411 ; ARM32: sbc |
2236 ; ARM32: lsr | 2412 ; ARM32: lsr |
2237 ; ARM32: sub | 2413 ; ARM32: sub |
2238 } | 2414 } |
OLD | NEW |