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1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// | 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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53 | 53 |
54 void initNodeForLowering(CfgNode *Node) override { | 54 void initNodeForLowering(CfgNode *Node) override { |
55 Computations.forgetProducers(); | 55 Computations.forgetProducers(); |
56 Computations.recordProducers(Node); | 56 Computations.recordProducers(Node); |
57 Computations.dump(Func); | 57 Computations.dump(Func); |
58 } | 58 } |
59 | 59 |
60 void translateOm1() override; | 60 void translateOm1() override; |
61 void translateO2() override; | 61 void translateO2() override; |
62 bool doBranchOpt(Inst *Instr, const CfgNode *NextNode) override; | 62 bool doBranchOpt(Inst *Instr, const CfgNode *NextNode) override; |
63 | 63 void setImplicitRet(Variable *Ret) { ImplicitRet = Ret; } |
64 Variable *getImplicitRet() const { return ImplicitRet; } | |
64 SizeT getNumRegisters() const override { return RegMIPS32::Reg_NUM; } | 65 SizeT getNumRegisters() const override { return RegMIPS32::Reg_NUM; } |
65 Variable *getPhysicalRegister(RegNumT RegNum, | 66 Variable *getPhysicalRegister(RegNumT RegNum, |
66 Type Ty = IceType_void) override; | 67 Type Ty = IceType_void) override; |
67 const char *getRegName(RegNumT RegNum, Type Ty) const override; | 68 const char *getRegName(RegNumT RegNum, Type Ty) const override; |
68 SmallBitVector getRegisterSet(RegSetMask Include, | 69 SmallBitVector getRegisterSet(RegSetMask Include, |
69 RegSetMask Exclude) const override; | 70 RegSetMask Exclude) const override; |
70 const SmallBitVector & | 71 const SmallBitVector & |
71 getRegistersForVariable(const Variable *Var) const override { | 72 getRegistersForVariable(const Variable *Var) const override { |
72 RegClass RC = Var->getRegClass(); | 73 RegClass RC = Var->getRegClass(); |
73 assert(RC < RC_Target); | 74 assert(RC < RC_Target); |
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104 int32_t getFrameFixedAllocaOffset() const override { | 105 int32_t getFrameFixedAllocaOffset() const override { |
105 return FixedAllocaSizeBytes - (SpillAreaSizeBytes - MaxOutArgsSizeBytes); | 106 return FixedAllocaSizeBytes - (SpillAreaSizeBytes - MaxOutArgsSizeBytes); |
106 } | 107 } |
107 | 108 |
108 uint32_t maxOutArgsSizeBytes() const override { return MaxOutArgsSizeBytes; } | 109 uint32_t maxOutArgsSizeBytes() const override { return MaxOutArgsSizeBytes; } |
109 | 110 |
110 bool shouldSplitToVariable64On32(Type Ty) const override { | 111 bool shouldSplitToVariable64On32(Type Ty) const override { |
111 return Ty == IceType_i64; | 112 return Ty == IceType_i64; |
112 } | 113 } |
113 | 114 |
115 bool shouldSplitToVariableVecOn32(Type Ty) const override { | |
116 return isVectorType(Ty); | |
117 } | |
118 | |
114 // TODO(ascull): what is the best size of MIPS? | 119 // TODO(ascull): what is the best size of MIPS? |
115 SizeT getMinJumpTableSize() const override { return 3; } | 120 SizeT getMinJumpTableSize() const override { return 3; } |
116 void emitJumpTable(const Cfg *Func, | 121 void emitJumpTable(const Cfg *Func, |
117 const InstJumpTable *JumpTable) const override; | 122 const InstJumpTable *JumpTable) const override; |
118 | 123 |
119 void emitVariable(const Variable *Var) const override; | 124 void emitVariable(const Variable *Var) const override; |
120 | 125 |
121 void emit(const ConstantInteger32 *C) const final { | 126 void emit(const ConstantInteger32 *C) const final { |
122 if (!BuildDefs::dump()) | 127 if (!BuildDefs::dump()) |
123 return; | 128 return; |
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602 | 607 |
603 void addProlog(CfgNode *Node) override; | 608 void addProlog(CfgNode *Node) override; |
604 void addEpilog(CfgNode *Node) override; | 609 void addEpilog(CfgNode *Node) override; |
605 | 610 |
606 // Ensure that a 64-bit Variable has been split into 2 32-bit | 611 // Ensure that a 64-bit Variable has been split into 2 32-bit |
607 // Variables, creating them if necessary. This is needed for all | 612 // Variables, creating them if necessary. This is needed for all |
608 // I64 operations. | 613 // I64 operations. |
609 void split64(Variable *Var); | 614 void split64(Variable *Var); |
610 Operand *loOperand(Operand *Operand); | 615 Operand *loOperand(Operand *Operand); |
611 Operand *hiOperand(Operand *Operand); | 616 Operand *hiOperand(Operand *Operand); |
617 Operand *getOperandAtIndex(Operand *Operand, Type BaseType, uint32_t Index); | |
612 | 618 |
613 void finishArgumentLowering(Variable *Arg, Variable *FramePtr, | 619 void finishArgumentLowering(Variable *Arg, bool PartialOnStack, |
614 size_t BasicFrameOffset, size_t *InArgsSizeBytes); | 620 Variable *FramePtr, size_t BasicFrameOffset, |
621 size_t *InArgsSizeBytes); | |
615 | 622 |
616 Operand *legalizeUndef(Operand *From, RegNumT RegNum = RegNumT()); | 623 Operand *legalizeUndef(Operand *From, RegNumT RegNum = RegNumT()); |
617 | 624 |
618 /// Helper class that understands the Calling Convention and register | 625 /// Helper class that understands the Calling Convention and register |
619 /// assignments as per MIPS O32 abi. | 626 /// assignments as per MIPS O32 abi. |
620 class CallingConv { | 627 class CallingConv { |
621 CallingConv(const CallingConv &) = delete; | 628 CallingConv(const CallingConv &) = delete; |
622 CallingConv &operator=(const CallingConv &) = delete; | 629 CallingConv &operator=(const CallingConv &) = delete; |
623 | 630 |
624 public: | 631 public: |
625 CallingConv(); | 632 CallingConv(); |
626 ~CallingConv() = default; | 633 ~CallingConv() = default; |
627 | 634 |
628 /// argInReg returns true if there is a Register available for the requested | 635 /// argInReg returns true if there is a Register available for the requested |
629 /// type, and false otherwise. If it returns true, Reg is set to the | 636 /// type, and false otherwise. If it returns true, Reg is set to the |
630 /// appropriate register number. Note that, when Ty == IceType_i64, Reg will | 637 /// appropriate register number. Note that, when Ty == IceType_i64, Reg will |
631 /// be an I64 register pair. | 638 /// be an I64 register pair. |
632 bool argInReg(Type Ty, uint32_t ArgNo, RegNumT *Reg); | 639 bool argInReg(Type Ty, uint32_t ArgNo, RegNumT *Reg); |
640 void discardReg(RegNumT Reg) { GPRegsUsed |= RegisterAliases[Reg]; } | |
633 | 641 |
634 private: | 642 private: |
635 // argInGPR is used to find if any GPR register is available for argument of | 643 // argInGPR is used to find if any GPR register is available for argument of |
636 // type Ty | 644 // type Ty |
637 bool argInGPR(Type Ty, RegNumT *Reg); | 645 bool argInGPR(Type Ty, RegNumT *Reg); |
638 /// argInVFP is to floating-point/vector types what argInGPR is for integer | 646 /// argInVFP is to floating-point/vector types what argInGPR is for integer |
639 /// types. | 647 /// types. |
640 bool argInVFP(Type Ty, RegNumT *Reg); | 648 bool argInVFP(Type Ty, RegNumT *Reg); |
641 inline void discardNextGPRAndItsAliases(CfgVector<RegNumT> *Regs); | 649 inline void discardNextGPRAndItsAliases(CfgVector<RegNumT> *Regs); |
642 inline void alignGPR(CfgVector<RegNumT> *Regs); | 650 inline void alignGPR(CfgVector<RegNumT> *Regs); |
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736 static SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM]; | 744 static SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM]; |
737 SmallBitVector RegsUsed; | 745 SmallBitVector RegsUsed; |
738 VarList PhysicalRegisters[IceType_NUM]; | 746 VarList PhysicalRegisters[IceType_NUM]; |
739 VarList PreservedGPRs; | 747 VarList PreservedGPRs; |
740 static constexpr uint32_t CHAR_BITS = 8; | 748 static constexpr uint32_t CHAR_BITS = 8; |
741 static constexpr uint32_t INT32_BITS = 32; | 749 static constexpr uint32_t INT32_BITS = 32; |
742 size_t SpillAreaSizeBytes = 0; | 750 size_t SpillAreaSizeBytes = 0; |
743 size_t FixedAllocaSizeBytes = 0; | 751 size_t FixedAllocaSizeBytes = 0; |
744 size_t FixedAllocaAlignBytes = 0; | 752 size_t FixedAllocaAlignBytes = 0; |
745 size_t PreservedRegsSizeBytes = 0; | 753 size_t PreservedRegsSizeBytes = 0; |
754 Variable *ImplicitRet; /// Implicit return | |
Jim Stichnoth
2016/10/03 14:52:23
Variable *ImplicitRet = nullptr;
| |
746 | 755 |
747 private: | 756 private: |
748 ENABLE_MAKE_UNIQUE; | 757 ENABLE_MAKE_UNIQUE; |
749 | 758 |
750 OperandMIPS32Mem *formAddressingMode(Type Ty, Cfg *Func, const Inst *LdSt, | 759 OperandMIPS32Mem *formAddressingMode(Type Ty, Cfg *Func, const Inst *LdSt, |
751 Operand *Base); | 760 Operand *Base); |
752 | 761 |
753 class ComputationTracker { | 762 class ComputationTracker { |
754 public: | 763 public: |
755 ComputationTracker() = default; | 764 ComputationTracker() = default; |
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849 explicit TargetHeaderMIPS32(GlobalContext *Ctx); | 858 explicit TargetHeaderMIPS32(GlobalContext *Ctx); |
850 | 859 |
851 private: | 860 private: |
852 ~TargetHeaderMIPS32() = default; | 861 ~TargetHeaderMIPS32() = default; |
853 }; | 862 }; |
854 | 863 |
855 } // end of namespace MIPS32 | 864 } // end of namespace MIPS32 |
856 } // end of namespace Ice | 865 } // end of namespace Ice |
857 | 866 |
858 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H | 867 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H |
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