[SubZero] Vector types support for MIPS

src/IceTargetLoweringMIPS32.h

 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 42 matching lines @@
 
   void initNodeForLowering(CfgNode *Node) override {
     Computations.forgetProducers();
     Computations.recordProducers(Node);
     Computations.dump(Func);
   }
 
   void translateOm1() override;
   void translateO2() override;
   bool doBranchOpt(Inst *Instr, const CfgNode *NextNode) override;
-
+  void setImplicitRet(Variable *Ret) { ImplicitRet = Ret; }
+  Variable *getImplicitRet() const { return ImplicitRet; }
   SizeT getNumRegisters() const override { return RegMIPS32::Reg_NUM; }
   Variable *getPhysicalRegister(RegNumT RegNum,
                                 Type Ty = IceType_void) override;
   const char *getRegName(RegNumT RegNum, Type Ty) const override;
   SmallBitVector getRegisterSet(RegSetMask Include,
                                 RegSetMask Exclude) const override;
   const SmallBitVector &
   getRegistersForVariable(const Variable *Var) const override {
     RegClass RC = Var->getRegClass();
     assert(RC < RC_Target);
@@ skipping 30 matching lines @@
   int32_t getFrameFixedAllocaOffset() const override {
     return FixedAllocaSizeBytes - (SpillAreaSizeBytes - MaxOutArgsSizeBytes);
   }
 
   uint32_t maxOutArgsSizeBytes() const override { return MaxOutArgsSizeBytes; }
 
   bool shouldSplitToVariable64On32(Type Ty) const override {
     return Ty == IceType_i64;
   }
 
+  bool shouldSplitToVariableVecOn32(Type Ty) const override {
+    return isVectorType(Ty);
+  }
+
   // TODO(ascull): what is the best size of MIPS?
   SizeT getMinJumpTableSize() const override { return 3; }
   void emitJumpTable(const Cfg *Func,
                      const InstJumpTable *JumpTable) const override;
 
   void emitVariable(const Variable *Var) const override;
 
   void emit(const ConstantInteger32 *C) const final {
     if (!BuildDefs::dump())
       return;
@@ skipping 478 matching lines @@
 
   void addProlog(CfgNode *Node) override;
   void addEpilog(CfgNode *Node) override;
 
   // Ensure that a 64-bit Variable has been split into 2 32-bit
   // Variables, creating them if necessary.  This is needed for all
   // I64 operations.
   void split64(Variable *Var);
   Operand *loOperand(Operand *Operand);
   Operand *hiOperand(Operand *Operand);
+  Operand *getOperandAtIndex(Operand *Operand, Type BaseType, uint32_t Index);
 
-  void finishArgumentLowering(Variable *Arg, Variable *FramePtr,
-                              size_t BasicFrameOffset, size_t *InArgsSizeBytes);
+  void finishArgumentLowering(Variable *Arg, bool PartialOnStack,
+                              Variable *FramePtr, size_t BasicFrameOffset,
+                              size_t *InArgsSizeBytes);
 
   Operand *legalizeUndef(Operand *From, RegNumT RegNum = RegNumT());
 
   /// Helper class that understands the Calling Convention and register
   /// assignments as per MIPS O32 abi.
   class CallingConv {
     CallingConv(const CallingConv &) = delete;
     CallingConv &operator=(const CallingConv &) = delete;
 
   public:
     CallingConv();
     ~CallingConv() = default;
 
     /// argInReg returns true if there is a Register available for the requested
     /// type, and false otherwise. If it returns true, Reg is set to the
     /// appropriate register number. Note that, when Ty == IceType_i64, Reg will
     /// be an I64 register pair.
     bool argInReg(Type Ty, uint32_t ArgNo, RegNumT *Reg);
+    void discardReg(RegNumT Reg) { GPRegsUsed |= RegisterAliases[Reg]; }
 
   private:
     // argInGPR is used to find if any GPR register is available for argument of
     // type Ty
     bool argInGPR(Type Ty, RegNumT *Reg);
     /// argInVFP is to floating-point/vector types what argInGPR is for integer
     /// types.
     bool argInVFP(Type Ty, RegNumT *Reg);
     inline void discardNextGPRAndItsAliases(CfgVector<RegNumT> *Regs);
     inline void alignGPR(CfgVector<RegNumT> *Regs);
@@ skipping 93 matching lines @@
   static SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM];
   SmallBitVector RegsUsed;
   VarList PhysicalRegisters[IceType_NUM];
   VarList PreservedGPRs;
   static constexpr uint32_t CHAR_BITS = 8;
   static constexpr uint32_t INT32_BITS = 32;
   size_t SpillAreaSizeBytes = 0;
   size_t FixedAllocaSizeBytes = 0;
   size_t FixedAllocaAlignBytes = 0;
   size_t PreservedRegsSizeBytes = 0;
+  Variable *ImplicitRet; /// Implicit return

[Jim Stichnoth, 2016/10/03 14:52:23]

Variable *ImplicitRet = nullptr;

 
 private:
   ENABLE_MAKE_UNIQUE;
 
   OperandMIPS32Mem *formAddressingMode(Type Ty, Cfg *Func, const Inst *LdSt,
                                        Operand *Base);
 
   class ComputationTracker {
   public:
     ComputationTracker() = default;
@@ skipping 93 matching lines @@
   explicit TargetHeaderMIPS32(GlobalContext *Ctx);
 
 private:
   ~TargetHeaderMIPS32() = default;
 };
 
 } // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H