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1 /* | 1 /* |
2 * Copyright 2016 The LibYuv Project Authors. All rights reserved. | 2 * Copyright 2016 The LibYuv Project Authors. All rights reserved. |
3 * | 3 * |
4 * Use of this source code is governed by a BSD-style license | 4 * Use of this source code is governed by a BSD-style license |
5 * that can be found in the LICENSE file in the root of the source | 5 * that can be found in the LICENSE file in the root of the source |
6 * tree. An additional intellectual property rights grant can be found | 6 * tree. An additional intellectual property rights grant can be found |
7 * in the file PATENTS. All contributing project authors may | 7 * in the file PATENTS. All contributing project authors may |
8 * be found in the AUTHORS file in the root of the source tree. | 8 * be found in the AUTHORS file in the root of the source tree. |
9 */ | 9 */ |
10 | 10 |
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64 Return Type - as per RTYPE | 64 Return Type - as per RTYPE |
65 Details : Byte elements from 'in0' & 'in1' are copied selectively to | 65 Details : Byte elements from 'in0' & 'in1' are copied selectively to |
66 'out0' as per control vector 'mask0' | 66 'out0' as per control vector 'mask0' |
67 */ | 67 */ |
68 #define VSHF_B2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1) { \ | 68 #define VSHF_B2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1) { \ |
69 out0 = (RTYPE) __msa_vshf_b((v16i8) mask0, (v16i8) in1, (v16i8) in0); \ | 69 out0 = (RTYPE) __msa_vshf_b((v16i8) mask0, (v16i8) in1, (v16i8) in0); \ |
70 out1 = (RTYPE) __msa_vshf_b((v16i8) mask1, (v16i8) in3, (v16i8) in2); \ | 70 out1 = (RTYPE) __msa_vshf_b((v16i8) mask1, (v16i8) in3, (v16i8) in2); \ |
71 } | 71 } |
72 #define VSHF_B2_UB(...) VSHF_B2(v16u8, __VA_ARGS__) | 72 #define VSHF_B2_UB(...) VSHF_B2(v16u8, __VA_ARGS__) |
73 | 73 |
| 74 /* Description : Interleave both left and right half of input vectors |
| 75 Arguments : Inputs - in0, in1 |
| 76 Outputs - out0, out1 |
| 77 Return Type - as per RTYPE |
| 78 Details : Right half of byte elements from 'in0' and 'in1' are |
| 79 interleaved and written to 'out0' |
| 80 */ |
| 81 #define ILVRL_B2(RTYPE, in0, in1, out0, out1) { \ |
| 82 out0 = (RTYPE) __msa_ilvr_b((v16i8) in0, (v16i8) in1); \ |
| 83 out1 = (RTYPE) __msa_ilvl_b((v16i8) in0, (v16i8) in1); \ |
| 84 } |
| 85 #define ILVRL_B2_UB(...) ILVRL_B2(v16u8, __VA_ARGS__) |
| 86 |
74 #endif /* !defined(LIBYUV_DISABLE_MSA) && defined(__mips_msa) */ | 87 #endif /* !defined(LIBYUV_DISABLE_MSA) && defined(__mips_msa) */ |
75 | 88 |
76 #endif // INCLUDE_LIBYUV_MACROS_MSA_H_ | 89 #endif // INCLUDE_LIBYUV_MACROS_MSA_H_ |
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