Subzero, MIPS32: DIVU instruction encoding

src/IceAssemblerMIPS32.h

 //===- subzero/src/IceAssemblerMIPS32.h - Assembler for MIPS ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 145 matching lines @@
   void cvt_s_l(const Operand *OpFd, const Operand *OpFs);
 
   void cvt_s_w(const Operand *OpFd, const Operand *OpFs);
 
   void div(const Operand *OpRs, const Operand *OpRt);
 
   void div_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
 
   void div_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
 
+  void divu(const Operand *OpRs, const Operand *OpRt);
+
   void lui(const Operand *OpRt, const uint16_t Imm);
 
   void lw(const Operand *OpRt, const Operand *OpBase, const uint32_t Offset);
 
   void mfc1(const Operand *OpRt, const Operand *OpFs);
 
   void mfhi(const Operand *OpRd);
 
   void mflo(const Operand *OpRd);
 
@@ skipping 161 matching lines @@
   void emitInst(IValueT Value) {
     AssemblerBuffer::EnsureCapacity _(&Buffer);
     Buffer.emit<IValueT>(Value);
   }
 };
 
 } // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERMIPS32_H