[Subzero][MIPS] Add RUN command line with -Om1 in test 64bit.pnacl.ll

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
@@ skipping 18 matching lines @@
 ; TODO(rkotler): Stop skipping unimplemented parts (via --skip-unimplemented)
 ; once enough infrastructure is in. Also, switch to --filetype=obj
 ; when possible.
 ; RUN: %if --need=target_MIPS32 --need=allow_dump \
 ; RUN:   --command %p2i --filetype=asm --assemble \
 ; RUN:   --disassemble --target mips32 -i %s --args -O2 --skip-unimplemented \
 ; RUN:   -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_MIPS32 --need=allow_dump \
 ; RUN:   --command FileCheck --check-prefix MIPS32 --check-prefix MIPS32-O2 %s
 
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN:   --command %p2i --filetype=asm --assemble \
+; RUN:   --disassemble --target mips32 -i %s --args -Om1 --skip-unimplemented \
+; RUN:   -allow-externally-defined-symbols \
+; RUN:   | %if --need=target_MIPS32 --need=allow_dump \
+; RUN:   --command FileCheck --check-prefix MIPS32 --check-prefix MIPS32-OM1 %s
+
 @__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
 @__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
 @__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8
 @__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4
 
 define internal i32 @ignore64BitArg(i64 %a, i32 %b, i64 %c) {
 entry:
   ret i32 %b
 }
 
 ; MIPS32-LABEL: ignore64BitArg
-; MIPS32: move v0,a2
+; MIPS32-O2: move v0,a2
+; MIPS32-OM1: sw a2,[[MEM:.*]]
+; MIPS32-OM1: lw v0,[[MEM]]
 
 define internal i32 @pass64BitArg(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f) {
 entry:
   %call = call i32 @ignore64BitArgNoInline(i64 %a, i32 123, i64 %b)
   %call1 = call i32 @ignore64BitArgNoInline(i64 %c, i32 123, i64 %d)
   %call2 = call i32 @ignore64BitArgNoInline(i64 %e, i32 123, i64 %f)
   %add = add i32 %call1, %call
   %add3 = add i32 %add, %call2
   ret i32 %add3
 }
@@ skipping 135 matching lines @@
 ; OPTM1-LABEL: return64BitArg
 ; OPTM1: mov     {{.*}},DWORD PTR [esp+0xc]
 ; OPTM1: mov     {{.*}},DWORD PTR [esp+0x10]
 
 ; ARM32-LABEL: return64BitArg
 ; ARM32: mov {{.*}}, r2
 ; ARM32: mov {{.*}}, r3
 ; ARM32: bx lr
 
 ; MIPS32-LABEL; return64BitArg
-; MIPS32: move v0,a2
-; MIPS32: move v1,a3
+; MIPS32-O2: move v0,a2
+; MIPS32-O2: move v1,a3
+; MIPS32-OM1: move [[T1:.*]],a2
+; MIPS32-OM1: sw [[T1]],[[MEM1:.*]]
+; MIPS32-OM1: move [[T2:.*]],a3
+; MIPS32-OM1: sw [[T2]],[[MEM2:.*]]
+; MIPS32-OM1: lw v0,[[MEM1]]
+; MIPS32-OM1: lw v1,[[MEM2]]
 ; MIPS32: jr ra
 
 define internal i64 @return64BitConst() {
 entry:
   ret i64 -2401053092306725256
 }
 ; CHECK-LABEL: return64BitConst
 ; CHECK: mov     eax,0x12345678
 ; CHECK: mov     edx,0xdeadbeef
 ;
@@ skipping 306 matching lines @@
 ; MIPS32: sllv  [[T1:.*]],[[A_HI:.*]],[[B_LO:.*]]
 ; MIPS32: nor   [[T2:.*]],[[B_LO]],zero
 ; MIPS32: srl   [[T3:.*]],[[A_LO:.*]],0x1
 ; MIPS32: srlv  [[T4:.*]],[[T3]],[[T2]]
 ; MIPS32: or    [[T_HI:.*]],[[T1]],[[T4]]
 ; MIPS32: sllv  [[T_LO:.*]],[[A_LO]],[[B_LO]]
 ; MIPS32: move  [[T1_LO:.*]],[[T_LO]]
 ; MIPS32: andi  [[T5:.*]],[[B_LO]],0x20
 ; MIPS32: movn  [[T_HI]],[[T_LO]],[[T5]]
 ; MIPS32: movn  [[T1_LO]],zero,[[T5]]
-; MIPS32: move  v1,[[T_HI]]
+; MIPS32-O2: move       v1,[[T_HI]]
+; MIPS32-OM1: sw        [[T_HI]],[[MEM:.*]]
+; MIPS32-OM1: lw        v1,[[MEM]]
 
 define internal i32 @shl64BitSignedTrunc(i64 %a, i64 %b) {
 entry:
   %shl = shl i64 %a, %b
   %result = trunc i64 %shl to i32
   ret i32 %result
 }
 ; CHECK-LABEL: shl64BitSignedTrunc
 ; CHECK: mov
 ; CHECK: shl e
@@ skipping 39 matching lines @@
 ; MIPS32: sllv  [[T1:.*]],[[A_HI:.*]],[[B_LO:.*]]
 ; MIPS32: nor   [[T2:.*]],[[B_LO]],zero
 ; MIPS32: srl   [[T3:.*]],[[A_LO:.*]],0x1
 ; MIPS32: srlv  [[T4:.*]],[[T3]],[[T2]]
 ; MIPS32: or    [[T_HI:.*]],[[T1]],[[T4]]
 ; MIPS32: sllv  [[T_LO:.*]],[[A_LO]],[[B_LO]]
 ; MIPS32: move  [[T1_LO:.*]],[[T_LO]]
 ; MIPS32: andi  [[T5:.*]],[[B_LO]],0x20
 ; MIPS32: movn  [[T_HI]],[[T_LO]],[[T5]]
 ; MIPS32: movn  [[T1_LO]],zero,[[T5]]
-; MIPS32: move  v1,[[T_HI]]
+; MIPS32-O2: move       v1,[[T_HI]]
+; MIPS32-OM1: sw        [[T_HI]],[[MEM:.*]]
+; MIPS32-OM1: lw        v1,[[MEM]]
 
 define internal i64 @shr64BitSigned(i64 %a, i64 %b) {
 entry:
   %shr = ashr i64 %a, %b
   ret i64 %shr
 }
 ; CHECK-LABEL: shr64BitSigned
 ; CHECK: shrd
 ; CHECK: sar
 ; CHECK: test {{.*}},0x20
@@ skipping 274 matching lines @@
 ; CHECK-NEXT: movsx  eax,ax
 ;
 ; OPTM1-LABEL: trunc64To16Signed
 ; OPTM1:      mov     ax,WORD PTR [esp+
 ; OPTM1: movsx  eax,
 
 ; ARM32-LABEL: trunc64To16Signed
 ; ARM32: sxth r0, r0
 
 ; MIPS32-LABEL: trunc64To16Signed
-; MIPS32: sll a0,a0,0x10
-; MIPS32: sra a0,a0,0x10
-; MIPS32: move v0,a0
+; MIPS32-O2: sll [[T1:.*]],a0,0x10
+; MIPS32-O2: sra [[T2:.*]],[[T1]],0x10
+; MIPS32-O2: move v0,[[T2]]
+; MIPS32-OM1: sll [[T1:.*]],{{.*}},0x10
+; MIPS32-OM1: sra [[T2:.*]],[[T1]],0x10
+; MIPS32-OM1: sw [[T2]],[[MEM:.*]]
+; MIPS32-OM1: lw v0,[[MEM]]
 
 define internal i32 @trunc64To8Signed(i64 %a) {
 entry:
   %conv = trunc i64 %a to i8
   %conv.ret_ext = sext i8 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To8Signed
 ; CHECK:      mov     eax,DWORD PTR [esp+0x4]
 ; CHECK-NEXT: movsx  eax,al
 ;
 ; OPTM1-LABEL: trunc64To8Signed
 ; OPTM1:      mov     eax,DWORD PTR [esp+
 ; OPTM1: movsx  eax,
 
 ; ARM32-LABEL: trunc64To8Signed
 ; ARM32: sxtb r0, r0
 
 ; MIPS32-LABEL: trunc64To8Signed
-; MIPS32: sll a0,a0,0x18
-; MIPS32: sra a0,a0,0x18
-; MIPS32: move v0,a0
+; MIPS32-O2: sll [[T1:.*]],a0,0x18
+; MIPS32-O2: sra [[T2:.*]],[[T1]],0x18
+; MIPS32-O2: move v0,[[T2]]
+; MIPS32-OM1: sll [[T1:.*]],{{.*}},0x18
+; MIPS32-OM1: sra [[T2:.*]],[[T1]],0x18
+; MIPS32-OM1: sw [[T2]],[[MEM:.*]]
+; MIPS32-OM1: lw v0,[[MEM]]
 
 define internal i32 @trunc64To32SignedConst() {
 entry:
   %conv = trunc i64 12345678901234 to i32
   ret i32 %conv
 }
 ; CHECK-LABEL: trunc64To32SignedConst
 ; CHECK: mov eax,0x73ce2ff2
 ;
 ; OPTM1-LABEL: trunc64To32SignedConst
@@ skipping 60 matching lines @@
 ; CHECK-NEXT: movzx  eax,ax
 ;
 ; OPTM1-LABEL: trunc64To16Unsigned
 ; OPTM1:      mov     ax,WORD PTR [esp+
 ; OPTM1: movzx  eax,
 
 ; ARM32-LABEL: trunc64To16Unsigned
 ; ARM32: uxth
 
 ; MIPS32-LABEL: trunc64To16Unsigned
-; MIPS32: andi a0,a0,0xffff
-; MIPS32: move v0,a0
+; MIPS32-O2: andi [[T1:.*]],a0,0xffff
+; MIPS32-O2: move v0,[[T1]]
+; MIPS32-OM1: andi [[T1:.*]],{{.*}},0xffff
+; MIPS32-OM1: sw [[T1]],[[MEM:.*]]
+; MIPS32-OM1: lw v0,[[MEM]]
 
 define internal i32 @trunc64To8Unsigned(i64 %a) {
 entry:
   %conv = trunc i64 %a to i8
   %conv.ret_ext = zext i8 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To8Unsigned
 ; CHECK:      mov     eax,DWORD PTR [esp+0x4]
 ; CHECK-NEXT: movzx  eax,al
 ;
 ; OPTM1-LABEL: trunc64To8Unsigned
 ; OPTM1: mov    eax,DWORD PTR [esp+
 ; OPTM1: movzx  eax,
 
 ; ARM32-LABEL: trunc64To8Unsigned
 ; ARM32: uxtb
 
 ; MIPS32-LABEL: trunc64To8Unsigned
-; MIPS32: andi a0,a0,0xff
-; MIPS32: move v0,a0
+; MIPS32-O2: andi [[T1:.*]],a0,0xff
+; MIPS32-O2: move v0,[[T1]]
+; MIPS32-OM1: andi [[T1:.*]],{{.*}},0xff
+; MIPS32-OM1: sw [[T1]],[[MEM:.*]]
+; MIPS32-OM1: lw v0,[[MEM]]
 
 define internal i32 @trunc64To1(i64 %a) {
 entry:
 ;  %tobool = icmp ne i64 %a, 0
   %tobool = trunc i64 %a to i1
   %tobool.ret_ext = zext i1 %tobool to i32
   ret i32 %tobool.ret_ext
 }
 ; CHECK-LABEL: trunc64To1
 ; CHECK:      mov     eax,DWORD PTR [esp+0x4]
 ; CHECK:      and     al,0x1
 ; CHECK-NOT:  and     eax,0x1
 ;
 ; OPTM1-LABEL: trunc64To1
 ; OPTM1:      mov     eax,DWORD PTR [esp+
 ; OPTM1:      and     al,0x1
 ; OPTM1-NOT:  and     eax,0x1
 
 ; ARM32-LABEL: trunc64To1
 ; ARM32-OM1: and r0, r0, #1
 ; ARM32-O2: and r0, r0, #1
 
 ; MIPS32-LABEL: trunc64To1
-; MIPS32: andi {{.*}},a0,0x1
-; MIPS32: move v0,a0
+; MIPS32-O2: andi [[T1:.*]],a0,0x1
+; MIPS32-O2: move v0,[[T1]]
+; MIPS32-OM1: andi [[T1:.*]],{{.*}},0x1
+; MIPS32-OM1: sw [[T1]],[[MEM:.*]]
+; MIPS32-OM1: lw v0,[[MEM]]
 
 define internal i64 @sext32To64(i32 %a) {
 entry:
   %conv = sext i32 %a to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: sext32To64
 ; CHECK: mov
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: sext32To64
 ; OPTM1: mov
 ; OPTM1: sar {{.*}},0x1f
 
 ; ARM32-LABEL: sext32To64
 ; ARM32: asr {{.*}}, #31
 
 ; MIPS32-LABEL: sext32To64
-; MIPS32-LABEL: sra {{.*}},a0,0x1f
-; MIPS32-LABEL: move v1,v0
-; MIPS32-LABEL: move v0,a0
+; MIPS32: sra [[T_HI:.*]],[[T_LO:.*]],0x1f
+; MIPS32-O2: move v1,[[T_HI]]
+; MIPS32-O2: move v0,[[T_LO]]
+; MIPS32-OM1: sw [[T_HI]],[[MEM_HI:.*]]
+; MIPS32-OM1: sw [[T_LO]],[[MEM_LO:.*]]
+; MIPS32-OM1: lw v0,[[MEM_LO]]
+; MIPS32-OM1: lw v1,[[MEM_HI]]
 
 define internal i64 @sext16To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i16
   %conv = sext i16 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: sext16To64
 ; CHECK: movsx
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: sext16To64
 ; OPTM1: movsx
 ; OPTM1: sar {{.*}},0x1f
 
 ; ARM32-LABEL: sext16To64
 ; ARM32: sxth
 ; ARM32: asr {{.*}}, #31
 
 ; MIPS32-LABEL: sext16To64
-; MIPS32: sll {{.*}},{{.*}},0x10
-; MIPS32: sra {{.*}},{{.*}},0x10
-; MIPS32: sra {{.*}},{{.*}},0x1f
-; MIPS32: move v1,v0
-; MIPS32: move v0,a0
+; MIPS32: sll [[T1_LO:.*]],{{.*}},0x10
+; MIPS32: sra [[T2_LO:.*]],[[T1_LO]],0x10
+; MIPS32: sra [[T_HI:.*]],[[T2_LO]],0x1f
+; MIPS32-O2: move v1,[[T_HI]]
+; MIPS32-O2: move v0,[[T2_LO]]
+; MIPS32-OM1: sw [[T_HI]],[[MEM_HI:.*]]
+; MIPS32-OM1: sw [[T2_LO]],[[MEM_LO:.*]]
+; MIPS32-OM1: lw v0,[[MEM_LO]]
+; MIPS32-OM1: lw v1,[[MEM_HI]]
+
 
 define internal i64 @sext8To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i8
   %conv = sext i8 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: sext8To64
 ; CHECK: movsx
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: sext8To64
 ; OPTM1: movsx
 ; OPTM1: sar {{.*}},0x1f
 
 ; ARM32-LABEL: sext8To64
 ; ARM32: sxtb
 ; ARM32: asr {{.*}}, #31
 
 ; MIPS32-LABEL: sext8To64
-; MIPS32: sll {{.*}},a0,0x18
-; MIPS32: sra {{.*}},{{.*}},0x18
-; MIPS32: sra {{.*}},{{.*}},0x1f
-; MIPS32: move v1,v0
-; MIPS32: move v0,a0
+; MIPS32: sll [[T1_LO:.*]],{{.*}},0x18
+; MIPS32: sra [[T2_LO:.*]],[[T1_LO]],0x18
+; MIPS32: sra [[T_HI:.*]],[[T2_LO]],0x1f
+; MIPS32-O2: move v1,[[T_HI]]
+; MIPS32-O2: move v0,[[T2_LO]]
+; MIPS32-OM1: sw [[T_HI]],[[MEM_HI:.*]]
+; MIPS32-OM1: sw [[T2_LO]],[[MEM_LO:.*]]
+; MIPS32-OM1: lw v0,[[MEM_LO]]
+; MIPS32-OM1: lw v1,[[MEM_HI]]
 
 define internal i64 @sext1To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i1
   %conv = sext i1 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: sext1To64
 ; CHECK: mov
 ; CHECK: shl {{.*}},0x1f
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: sext1To64
 ; OPTM1: mov
 ; OPTM1: shl {{.*}},0x1f
 ; OPTM1: sar {{.*}},0x1f
 
 ; ARM32-LABEL: sext1To64
 ; ARM32: mov {{.*}}, #0
 ; ARM32: tst {{.*}}, #1
 ; ARM32: mvn {{.*}}, #0
 ; ARM32: movne
 
 ; MIPS32-LABEL: sext1To64
-; MIPS32: sll {{.*}},a0,0x1f
-; MIPS32: sra {{.*}},{{.*}},0x1f
-; MIPS32: move v1,a0
-; MIPS32: move v0,a0
+; MIPS32: sll [[T1:.*]],{{.*}},0x1f
+; MIPS32: sra [[T2:.*]],[[T1]],0x1f
+; MIPS32-O2: move v1,[[T2]]
+; MIPS32-O2: move v0,[[T2]]
+; MIPS32-OM1: sw [[T2]],[[MEM_HI:.*]]
+; MIPS32-OM1: sw [[T2]],[[MEM_LO:.*]]
+; MIPS32-OM1: lw v0,[[MEM_LO]]
+; MIPS32-OM1: lw v1,[[MEM_HI]]
 
 define internal i64 @zext32To64(i32 %a) {
 entry:
   %conv = zext i32 %a to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext32To64
 ; CHECK: mov
 ; CHECK: mov {{.*}},0x0
 ;
 ; OPTM1-LABEL: zext32To64
 ; OPTM1: mov
 ; OPTM1: mov {{.*}},0x0
 
 ; ARM32-LABEL: zext32To64
 ; ARM32: mov {{.*}}, #0
 
 ; MIPS32-LABEL: zext32To64
-; MIPS32: li {{.*}},0
-; MIPS32: move v1,v0
-; MIPS32: move v0,a0
+; MIPS32: li [[T1:.*]],0
+; MIPS32-O2: move v1,[[T1]]
+; MIPS32-O2: move v0,a0
+; MIPS32-OM1: sw [[T1]],[[MEM_HI:.*]]
+; MIPS32-OM1: lw v1,[[MEM_HI]]
 
 define internal i64 @zext16To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i16
   %conv = zext i16 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext16To64
 ; CHECK: movzx
 ; CHECK: mov {{.*}},0x0
 ;
 ; OPTM1-LABEL: zext16To64
 ; OPTM1: movzx
 ; OPTM1: mov {{.*}},0x0
 
 ; ARM32-LABEL: zext16To64
 ; ARM32: uxth
 ; ARM32: mov {{.*}}, #0
 
 ; MIPS32-LABEL: zext16To64
-; MIPS32: andi {{.*}},a0,0xffff
-; MIPS32: li {{.*}},0
-; MIPS32: move v1,v0
-; MIPS32: move v0,a0
+; MIPS32: andi [[T_LO:.*]],{{.*}},0xffff
+; MIPS32: li [[T_HI:.*]],0
+; MIPS32-O2: move v1,[[T_HI]]
+; MIPS32-O2: move v0,[[T_LO]]
+; MIPS32-OM1: sw [[T_HI]],[[MEM_HI:.*]]
+; MIPS32-OM1: lw v1,[[MEM_HI]]
 
 define internal i64 @zext8To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i8
   %conv = zext i8 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext8To64
 ; CHECK: movzx
 ; CHECK: mov {{.*}},0x0
 ;
 ; OPTM1-LABEL: zext8To64
 ; OPTM1: movzx
 ; OPTM1: mov {{.*}},0x0
 
 ; ARM32-LABEL: zext8To64
 ; ARM32: uxtb
 ; ARM32: mov {{.*}}, #0
 
 ; MIPS32-LABEL: zext8To64
-; MIPS32: andi {{.*}},a0,0xff
-; MIPS32: li {{.*}},0
-; MIPS32: move v1,v0
-; MIPS32: move v0,a0
+; MIPS32: andi [[T_LO:.*]],{{.*}},0xff
+; MIPS32: li [[T_HI:.*]],0
+; MIPS32-O2: move v1,[[T_HI]]
+; MIPS32-O2: move v0,[[T_LO]]
+; MIPS32-OM1: sw [[T_HI]],[[MEM_HI:.*]]
+; MIPS32-OM1: lw v1,[[MEM_HI]]
 
 define internal i64 @zext1To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i1
   %conv = zext i1 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext1To64
 ; CHECK: and {{.*}},0x1
 ; CHECK: mov {{.*}},0x0
 ;
 ; OPTM1-LABEL: zext1To64
 ; OPTM1: and {{.*}},0x1
 ; OPTM1: mov {{.*}},0x0
 
 ; ARM32-LABEL: zext1To64
 ; ARM32: and {{.*}}, #1
 ; ARM32: mov {{.*}}, #0
 ; ARM32: bx
 
 ; MIPS32-LABEL: zext1To64
-; MIPS32: andi {{.*}},a0,0x1
-; MIPS32: li {{.*}},0
-; MIPS32: move v1,v0
-; MIPS32: move v0,a0
+; MIPS32: andi [[T_LO:.*]],{{.*}},0x1
+; MIPS32: li [[T_HI:.*]],0
+; MIPS32-O2: move v1,[[T_HI]]
+; MIPS32-O2: move v0,[[T_LO]]
+; MIPS32-OM1: sw [[T_HI]],[[MEM_HI:.*]]
+; MIPS32-OM1: lw v1,[[MEM_HI]]
 
 define internal void @icmpEq64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp eq i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
 
@@ skipping 984 matching lines @@
   %s = lshr i64 %a, 40
   %t = trunc i64 %s to i32
   %r = sub i32 %t, 1
   ret i32 %r
 ; ARM32-LABEL: subOneToUpperAfterShift
 ; ARM32: subs
 ; ARM32: sbc
 ; ARM32: lsr
 ; ARM32: sub
 }