Subzero, MIPS32: SRAV instruction encoding

src/IceAssemblerMIPS32.h

 //===- subzero/src/IceAssemblerMIPS32.h - Assembler for MIPS ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 219 matching lines @@
   void sltiu(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
 
   void sltu(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
 
   void sqrt_d(const Operand *OpFd, const Operand *OpFs);
 
   void sqrt_s(const Operand *OpFd, const Operand *OpFs);
 
   void sra(const Operand *OpRd, const Operand *OpRt, const uint32_t Sa);
 
+  void srav(const Operand *OpRd, const Operand *OpRt, const Operand *OpRs);
+
   void srl(const Operand *OpRd, const Operand *OpRt, const uint32_t Sa);
 
   void srlv(const Operand *OpRd, const Operand *OpRt, const Operand *OpRs);
 
   void sub_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
 
   void sub_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
 
   void subu(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
 
@@ skipping 91 matching lines @@
   void emitInst(IValueT Value) {
     AssemblerBuffer::EnsureCapacity _(&Buffer);
     Buffer.emit<IValueT>(Value);
   }
 };
 
 } // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERMIPS32_H