OLD | NEW |
1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 | 5 |
6 // Declares a Simulator for MIPS instructions if we are not generating a native | 6 // Declares a Simulator for MIPS instructions if we are not generating a native |
7 // MIPS binary. This Simulator allows us to run and debug MIPS code generation | 7 // MIPS binary. This Simulator allows us to run and debug MIPS code generation |
8 // on regular desktop machines. | 8 // on regular desktop machines. |
9 // V8 calls into generated code by "calling" the CALL_GENERATED_CODE macro, | 9 // V8 calls into generated code by "calling" the CALL_GENERATED_CODE macro, |
10 // which will start execution in the Simulator or forwards to the real entry | 10 // which will start execution in the Simulator or forwards to the real entry |
(...skipping 104 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
115 char* CachedData(int offset) { | 115 char* CachedData(int offset) { |
116 return &data_[offset]; | 116 return &data_[offset]; |
117 } | 117 } |
118 | 118 |
119 private: | 119 private: |
120 char data_[kPageSize]; // The cached data. | 120 char data_[kPageSize]; // The cached data. |
121 static const int kValidityMapSize = kPageSize >> kLineShift; | 121 static const int kValidityMapSize = kPageSize >> kLineShift; |
122 char validity_map_[kValidityMapSize]; // One byte per line. | 122 char validity_map_[kValidityMapSize]; // One byte per line. |
123 }; | 123 }; |
124 | 124 |
| 125 class SimInstructionBase : public InstructionBase { |
| 126 public: |
| 127 Type InstructionType() const { return type_; } |
| 128 inline Instruction* instr() const { return instr_; } |
| 129 inline int32_t operand() const { return operand_; } |
| 130 |
| 131 protected: |
| 132 SimInstructionBase() : operand_(-1), instr_(nullptr), type_(kUnsupported) {} |
| 133 explicit SimInstructionBase(Instruction* instr) {} |
| 134 |
| 135 int32_t operand_; |
| 136 Instruction* instr_; |
| 137 Type type_; |
| 138 |
| 139 private: |
| 140 DISALLOW_ASSIGN(SimInstructionBase); |
| 141 }; |
| 142 |
| 143 class SimInstruction : public InstructionGetters<SimInstructionBase> { |
| 144 public: |
| 145 SimInstruction() {} |
| 146 |
| 147 explicit SimInstruction(Instruction* instr) { *this = instr; } |
| 148 |
| 149 SimInstruction& operator=(Instruction* instr) { |
| 150 operand_ = *reinterpret_cast<const int32_t*>(instr); |
| 151 instr_ = instr; |
| 152 type_ = InstructionBase::InstructionType(EXTRA); |
| 153 DCHECK(reinterpret_cast<void*>(&operand_) == this); |
| 154 return *this; |
| 155 } |
| 156 }; |
| 157 |
125 class Simulator { | 158 class Simulator { |
126 public: | 159 public: |
127 friend class MipsDebugger; | 160 friend class MipsDebugger; |
128 | 161 |
129 // Registers are declared in order. See SMRL chapter 2. | 162 // Registers are declared in order. See SMRL chapter 2. |
130 enum Register { | 163 enum Register { |
131 no_reg = -1, | 164 no_reg = -1, |
132 zero_reg = 0, | 165 zero_reg = 0, |
133 at, | 166 at, |
134 v0, v1, | 167 v0, v1, |
(...skipping 172 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
307 void TraceMemRd(int64_t addr, int64_t value); | 340 void TraceMemRd(int64_t addr, int64_t value); |
308 | 341 |
309 // Operations depending on endianness. | 342 // Operations depending on endianness. |
310 // Get Double Higher / Lower word. | 343 // Get Double Higher / Lower word. |
311 inline int32_t GetDoubleHIW(double* addr); | 344 inline int32_t GetDoubleHIW(double* addr); |
312 inline int32_t GetDoubleLOW(double* addr); | 345 inline int32_t GetDoubleLOW(double* addr); |
313 // Set Double Higher / Lower word. | 346 // Set Double Higher / Lower word. |
314 inline int32_t SetDoubleHIW(double* addr); | 347 inline int32_t SetDoubleHIW(double* addr); |
315 inline int32_t SetDoubleLOW(double* addr); | 348 inline int32_t SetDoubleLOW(double* addr); |
316 | 349 |
| 350 SimInstruction instr_; |
| 351 |
317 // functions called from DecodeTypeRegister. | 352 // functions called from DecodeTypeRegister. |
318 void DecodeTypeRegisterCOP1(); | 353 void DecodeTypeRegisterCOP1(); |
319 | 354 |
320 void DecodeTypeRegisterCOP1X(); | 355 void DecodeTypeRegisterCOP1X(); |
321 | 356 |
322 void DecodeTypeRegisterSPECIAL(); | 357 void DecodeTypeRegisterSPECIAL(); |
323 | 358 |
324 | 359 |
325 void DecodeTypeRegisterSPECIAL2(); | 360 void DecodeTypeRegisterSPECIAL2(); |
326 | 361 |
327 void DecodeTypeRegisterSPECIAL3(); | 362 void DecodeTypeRegisterSPECIAL3(); |
328 | 363 |
329 void DecodeTypeRegisterSRsType(); | 364 void DecodeTypeRegisterSRsType(); |
330 | 365 |
331 void DecodeTypeRegisterDRsType(); | 366 void DecodeTypeRegisterDRsType(); |
332 | 367 |
333 void DecodeTypeRegisterWRsType(); | 368 void DecodeTypeRegisterWRsType(); |
334 | 369 |
335 void DecodeTypeRegisterLRsType(); | 370 void DecodeTypeRegisterLRsType(); |
336 | 371 |
337 // Executing is handled based on the instruction type. | 372 // Executing is handled based on the instruction type. |
338 void DecodeTypeRegister(Instruction* instr); | 373 void DecodeTypeRegister(); |
339 | 374 |
340 Instruction* currentInstr_; | 375 inline int32_t rs_reg() const { return instr_.RsValue(); } |
341 inline Instruction* get_instr() const { return currentInstr_; } | |
342 inline void set_instr(Instruction* instr) { currentInstr_ = instr; } | |
343 | |
344 inline int32_t rs_reg() const { return currentInstr_->RsValue(); } | |
345 inline int64_t rs() const { return get_register(rs_reg()); } | 376 inline int64_t rs() const { return get_register(rs_reg()); } |
346 inline uint64_t rs_u() const { | 377 inline uint64_t rs_u() const { |
347 return static_cast<uint64_t>(get_register(rs_reg())); | 378 return static_cast<uint64_t>(get_register(rs_reg())); |
348 } | 379 } |
349 inline int32_t rt_reg() const { return currentInstr_->RtValue(); } | 380 inline int32_t rt_reg() const { return instr_.RtValue(); } |
350 inline int64_t rt() const { return get_register(rt_reg()); } | 381 inline int64_t rt() const { return get_register(rt_reg()); } |
351 inline uint64_t rt_u() const { | 382 inline uint64_t rt_u() const { |
352 return static_cast<uint64_t>(get_register(rt_reg())); | 383 return static_cast<uint64_t>(get_register(rt_reg())); |
353 } | 384 } |
354 inline int32_t rd_reg() const { return currentInstr_->RdValue(); } | 385 inline int32_t rd_reg() const { return instr_.RdValue(); } |
355 inline int32_t fr_reg() const { return currentInstr_->FrValue(); } | 386 inline int32_t fr_reg() const { return instr_.FrValue(); } |
356 inline int32_t fs_reg() const { return currentInstr_->FsValue(); } | 387 inline int32_t fs_reg() const { return instr_.FsValue(); } |
357 inline int32_t ft_reg() const { return currentInstr_->FtValue(); } | 388 inline int32_t ft_reg() const { return instr_.FtValue(); } |
358 inline int32_t fd_reg() const { return currentInstr_->FdValue(); } | 389 inline int32_t fd_reg() const { return instr_.FdValue(); } |
359 inline int32_t sa() const { return currentInstr_->SaValue(); } | 390 inline int32_t sa() const { return instr_.SaValue(); } |
360 inline int32_t lsa_sa() const { return currentInstr_->LsaSaValue(); } | 391 inline int32_t lsa_sa() const { return instr_.LsaSaValue(); } |
361 | 392 |
362 inline void SetResult(const int32_t rd_reg, const int64_t alu_out) { | 393 inline void SetResult(const int32_t rd_reg, const int64_t alu_out) { |
363 set_register(rd_reg, alu_out); | 394 set_register(rd_reg, alu_out); |
364 TraceRegWr(alu_out); | 395 TraceRegWr(alu_out); |
365 } | 396 } |
366 | 397 |
367 void DecodeTypeImmediate(Instruction* instr); | 398 void DecodeTypeImmediate(); |
368 void DecodeTypeJump(Instruction* instr); | 399 void DecodeTypeJump(); |
369 | 400 |
370 // Used for breakpoints and traps. | 401 // Used for breakpoints and traps. |
371 void SoftwareInterrupt(Instruction* instr); | 402 void SoftwareInterrupt(); |
372 | 403 |
373 // Compact branch guard. | 404 // Compact branch guard. |
374 void CheckForbiddenSlot(int64_t current_pc) { | 405 void CheckForbiddenSlot(int64_t current_pc) { |
375 Instruction* instr_after_compact_branch = | 406 Instruction* instr_after_compact_branch = |
376 reinterpret_cast<Instruction*>(current_pc + Instruction::kInstrSize); | 407 reinterpret_cast<Instruction*>(current_pc + Instruction::kInstrSize); |
377 if (instr_after_compact_branch->IsForbiddenAfterBranch()) { | 408 if (instr_after_compact_branch->IsForbiddenAfterBranch()) { |
378 V8_Fatal(__FILE__, __LINE__, | 409 V8_Fatal(__FILE__, __LINE__, |
379 "Error: Unexpected instruction 0x%08x immediately after a " | 410 "Error: Unexpected instruction 0x%08x immediately after a " |
380 "compact branch instruction.", | 411 "compact branch instruction.", |
381 *reinterpret_cast<uint32_t*>(instr_after_compact_branch)); | 412 *reinterpret_cast<uint32_t*>(instr_after_compact_branch)); |
(...skipping 138 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
520 static inline void UnregisterCTryCatch(Isolate* isolate) { | 551 static inline void UnregisterCTryCatch(Isolate* isolate) { |
521 Simulator::current(isolate)->PopAddress(); | 552 Simulator::current(isolate)->PopAddress(); |
522 } | 553 } |
523 }; | 554 }; |
524 | 555 |
525 } // namespace internal | 556 } // namespace internal |
526 } // namespace v8 | 557 } // namespace v8 |
527 | 558 |
528 #endif // !defined(USE_SIMULATOR) | 559 #endif // !defined(USE_SIMULATOR) |
529 #endif // V8_MIPS_SIMULATOR_MIPS_H_ | 560 #endif // V8_MIPS_SIMULATOR_MIPS_H_ |
OLD | NEW |