[Subzero][MIPS] Implement 64-bit integer compare operations

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 2882 matching lines @@
     Context.insert<InstFakeUse>(Src0R);
     Context.insert<InstFakeUse>(Src1R);
     _addiu(DestR, Zero, 1);
     _mov(Dest, DestR);
     break;
   }
   }
 }
 
 void TargetMIPS32::lower64Icmp(const InstIcmp *Instr) {
-  UnimplementedLoweringError(this, Instr);
-  return;
+  Operand *Src0 = legalize(Instr->getSrc(0));
+  Operand *Src1 = legalize(Instr->getSrc(1));
+  Variable *Dest = Instr->getDest();
+  InstIcmp::ICond Condition = Instr->getCondition();
+
+  Variable *Src0LoR = legalizeToReg(loOperand(Src0));
+  Variable *Src0HiR = legalizeToReg(hiOperand(Src0));
+  Variable *Src1LoR = legalizeToReg(loOperand(Src1));
+  Variable *Src1HiR = legalizeToReg(hiOperand(Src1));
+
+  switch (Condition) {
+  default:
+    llvm_unreachable("unexpected condition");
+    break;
+  case InstIcmp::Eq: {
+    auto *T1 = I32Reg();
+    auto *T2 = I32Reg();
+    auto *T3 = I32Reg();
+    _xor(T1, Src0HiR, Src1HiR);
+    _xor(T2, Src0LoR, Src1LoR);
+    _or(T3, T1, T2);
+    _sltiu(Dest, T3, 1);

[Jim Stichnoth, 2016/09/27 13:45:35]

Dest isn't necessarily a physical register (and probably won't be in Om1 mode),
so I think you need to go through another temporary:

  _sltiu(T4, T3, 1);
  _mov(Dest, T4);

Same for the InstIcmp::Ne case.

[sagar.thakur, 2016/09/28 08:23:23]

Done.

+    return;
+  }
+  case InstIcmp::Ne: {
+    auto *T1 = I32Reg();
+    auto *T2 = I32Reg();
+    auto *T3 = I32Reg();
+    _xor(T1, Src0HiR, Src1HiR);
+    _xor(T2, Src0LoR, Src1LoR);
+    _or(T3, T1, T2);
+    _sltu(Dest, getZero(), T3);
+    return;
+  }
+  case InstIcmp::Sgt: {
+    auto *T1 = I32Reg();
+    auto *T2 = I32Reg();
+    auto *T3 = I32Reg();
+    _xor(T1, Src0HiR, Src1HiR);
+    _slt(T2, Src1HiR, Src0HiR);
+    _sltu(T3, Src1LoR, Src0LoR);
+    _movz(T2, T3, T1);
+    _mov(Dest, T2);
+    return;
+  }
+  case InstIcmp::Ugt: {
+    auto *T1 = I32Reg();
+    auto *T2 = I32Reg();
+    auto *T3 = I32Reg();
+    _xor(T1, Src0HiR, Src1HiR);
+    _sltu(T2, Src1HiR, Src0HiR);
+    _sltu(T3, Src1LoR, Src0LoR);
+    _movz(T2, T3, T1);
+    _mov(Dest, T2);
+    return;
+  }
+  case InstIcmp::Sge: {
+    auto *T1 = I32Reg();
+    auto *T2 = I32Reg();
+    auto *T3 = I32Reg();
+    auto *T4 = I32Reg();
+    auto *T5 = I32Reg();
+    _xor(T1, Src0HiR, Src1HiR);
+    _slt(T2, Src0HiR, Src1HiR);
+    _xori(T3, T2, 1);
+    _sltu(T4, Src0LoR, Src1LoR);
+    _xori(T5, T4, 1);
+    _movz(T3, T5, T1);
+    _mov(Dest, T3);
+    return;
+  }
+  case InstIcmp::Uge: {
+    auto *T1 = I32Reg();
+    auto *T2 = I32Reg();
+    auto *T3 = I32Reg();
+    auto *T4 = I32Reg();
+    auto *T5 = I32Reg();
+    _xor(T1, Src0HiR, Src1HiR);
+    _sltu(T2, Src0HiR, Src1HiR);
+    _xori(T3, T2, 1);
+    _sltu(T4, Src0LoR, Src1LoR);
+    _xori(T5, T4, 1);
+    _movz(T3, T5, T1);
+    _mov(Dest, T3);
+    return;
+  }
+  case InstIcmp::Slt: {
+    auto *T1 = I32Reg();
+    auto *T2 = I32Reg();
+    auto *T3 = I32Reg();
+    _xor(T1, Src0HiR, Src1HiR);
+    _slt(T2, Src0HiR, Src1HiR);
+    _sltu(T3, Src0LoR, Src1LoR);
+    _movz(T2, T3, T1);
+    _mov(Dest, T2);
+    return;
+  }
+  case InstIcmp::Ult: {
+    auto *T1 = I32Reg();
+    auto *T2 = I32Reg();
+    auto *T3 = I32Reg();
+    _xor(T1, Src0HiR, Src1HiR);
+    _sltu(T2, Src0HiR, Src1HiR);
+    _sltu(T3, Src0LoR, Src1LoR);
+    _movz(T2, T3, T1);
+    _mov(Dest, T2);
+    return;
+  }
+  case InstIcmp::Sle: {
+    auto *T1 = I32Reg();
+    auto *T2 = I32Reg();
+    auto *T3 = I32Reg();
+    auto *T4 = I32Reg();
+    auto *T5 = I32Reg();
+    _xor(T1, Src0HiR, Src1HiR);
+    _slt(T2, Src1HiR, Src0HiR);
+    _xori(T3, T2, 1);
+    _sltu(T4, Src1LoR, Src0LoR);
+    _xori(T5, T4, 1);
+    _movz(T3, T5, T1);
+    _mov(Dest, T3);
+    return;
+  }
+  case InstIcmp::Ule: {
+    auto *T1 = I32Reg();
+    auto *T2 = I32Reg();
+    auto *T3 = I32Reg();
+    auto *T4 = I32Reg();
+    auto *T5 = I32Reg();
+    _xor(T1, Src0HiR, Src1HiR);
+    _sltu(T2, Src1HiR, Src0HiR);
+    _xori(T3, T2, 1);
+    _sltu(T4, Src1LoR, Src0LoR);
+    _xori(T5, T4, 1);
+    _movz(T3, T5, T1);
+    _mov(Dest, T3);
+    return;
+  }
+  }
 }
 
 void TargetMIPS32::lowerIcmp(const InstIcmp *Instr) {
   auto *Src0 = Instr->getSrc(0);
   auto *Src1 = Instr->getSrc(1);
   if (Src0->getType() == IceType_i64) {
     lower64Icmp(Instr);
     return;
   }
   Variable *Dest = Instr->getDest();
@@ skipping 1144 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice