Subzero, MIPS32: Intrinsic call Bswap for i16, i32 and i64

tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll

 ; This tests the NaCl intrinsics not related to atomic operations.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 --sandbox -i %s --args -O2 \
 ; RUN:   -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 --sandbox -i %s --args -Om1 \
 ; RUN:   -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
@@ skipping 335 matching lines @@
   %r_zext = zext i16 %r to i32
   ret i32 %r_zext
 }
 ; CHECK-LABEL: test_bswap_16
 ; Make sure this is the right operand size so that the most significant bit
 ; to least significant bit rotation happens at the right boundary.
 ; CHECK: rol {{[abcd]x|si|di|bp|word ptr}},0x8
 ; ARM32-LABEL: test_bswap_16
 ; ARM32: rev
 ; ARM32: lsr {{.*}} #16
+; MIPS32-LABEL: test_bswap_16
+; MIPS32: sll {{.*}},0x8
+; MIPS32: lui {{.*}},0xff
+; MIPS32: and
+; MIPS32: sll {{.*}},0x18
+; MIPS32: or
+; MIPS32: srl {{.*}},0x10
+; MIPS32: andi {{.*}},0xffff
 
 define internal i32 @test_bswap_32(i32 %x) {
 entry:
   %r = call i32 @llvm.bswap.i32(i32 %x)
   ret i32 %r
 }
 ; CHECK-LABEL: test_bswap_32
 ; CHECK: bswap e{{.*}}
 ; ARM32-LABEL: test_bswap_32
 ; ARM32: rev
+; MIPS32-LABEL: test_bswap_32
+; MIPS32: srl {{.*}},0x18
+; MIPS32: srl {{.*}},0x8
+; MIPS32: andi {{.*}},0xff00
+; MIPS32: or
+; MIPS32: sll {{.*}},0x8
+; MIPS32: lui {{.*}},0xff
+; MIPS32: and
+; MIPS32: sll {{.*}},0x18
+; MIPS32: or
+; MIPS32: or
 
 define internal i64 @test_bswap_64(i64 %x) {
 entry:
   %r = call i64 @llvm.bswap.i64(i64 %x)
   ret i64 %r
 }
 ; CHECK-LABEL: test_bswap_64
 ; CHECK: bswap e{{.*}}
 ; CHECK: bswap e{{.*}}
 ; ARM32-LABEL: test_bswap_64
 ; ARM32: rev
 ; ARM32: rev
+; MIPS32-LABEL: test_bswap_64
+; MIPS32: sll {{.*}},0x8
+; MIPS32: srl {{.*}},0x18
+; MIPS32: srl {{.*}},0x8
+; MIPS32: andi {{.*}},0xff00
+; MIPS32: lui {{.*}},0xff
+; MIPS32: or
+; MIPS32: and
+; MIPS32: sll {{.*}},0x18
+; MIPS32: or
+; MIPS32: srl {{.*}},0x18
+; MIPS32: srl {{.*}},0x8
+; MIPS32: andi {{.*}},0xff00
+; MIPS32: or
+; MIPS32: or
+; MIPS32: sll {{.*}},0x8
+; MIPS32: and
+; MIPS32: sll {{.*}},0x18
+; MIPS32: or
+; MIPS32: or
 
 define internal i64 @test_bswap_64_undef() {
 entry:
   %r = call i64 @llvm.bswap.i64(i64 undef)
   ret i64 %r
 }
 ; CHECK-LABEL: test_bswap_64_undef
 ; CHECK: bswap e{{.*}}
 ; CHECK: bswap e{{.*}}
 ; ARM32-LABEL: test_bswap_64
 ; ARM32: rev
 ; ARM32: rev
+; MIPS32-LABEL: test_bswap_64_undef
+; MIPS32: sll {{.*}},0x8
+; MIPS32: srl {{.*}},0x18
+; MIPS32: srl {{.*}},0x8
+; MIPS32: andi {{.*}},0xff00
+; MIPS32: lui {{.*}},0xff
+; MIPS32: or
+; MIPS32: and
+; MIPS32: sll {{.*}},0x18
+; MIPS32: or
+; MIPS32: srl {{.*}},0x18
+; MIPS32: srl {{.*}},0x8
+; MIPS32: andi {{.*}},0xff00
+; MIPS32: or
+; MIPS32: or
+; MIPS32: sll {{.*}},0x8
+; MIPS32: and
+; MIPS32: sll {{.*}},0x18
+; MIPS32: or
+; MIPS32: or
 
 define internal i32 @test_ctlz_32(i32 %x) {
 entry:
   %r = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
   ret i32 %r
 }
 ; CHECK-LABEL: test_ctlz_32
 ; TODO(jvoung): If we detect that LZCNT is supported, then use that
 ; and avoid the need to do the cmovne and xor stuff to guarantee that
 ; the result is well-defined w/ input == 0.
@@ skipping 209 matching lines @@
 ; CHECK: lea {{.*}},[esp+0x10]
 ; CHECK: lea {{.*}},[esp+0x10]
 ; CHECK: call
 ; CHECK: mov esp,{{.*}}
 ; CHECK: mov esp,ebp
 ; ARM32-LABEL: test_stacksave_multiple
 ; ARM32: mov {{.*}}, sp
 ; ARM32: mov {{.*}}, sp
 ; ARM32: mov {{.*}}, sp
 ; ARM32: mov sp, {{.*}}