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Side by Side Diff: include/libyuv/macros_msa.h

Issue 2368313003: Add MIPS SIMD Arch (MSA) optimized ARGBMirrorRow function (Closed)
Patch Set: Created 4 years, 2 months ago
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1 /* 1 /*
2 * Copyright 2016 The LibYuv Project Authors. All rights reserved. 2 * Copyright 2016 The LibYuv Project Authors. All rights reserved.
3 * 3 *
4 * Use of this source code is governed by a BSD-style license 4 * Use of this source code is governed by a BSD-style license
5 * that can be found in the LICENSE file in the root of the source 5 * that can be found in the LICENSE file in the root of the source
6 * tree. An additional intellectual property rights grant can be found 6 * tree. An additional intellectual property rights grant can be found
7 * in the file PATENTS. All contributing project authors may 7 * in the file PATENTS. All contributing project authors may
8 * be found in the AUTHORS file in the root of the source tree. 8 * be found in the AUTHORS file in the root of the source tree.
9 */ 9 */
10 10
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67 Outputs - out0, out1 67 Outputs - out0, out1
68 Return Type - as per RTYPE 68 Return Type - as per RTYPE
69 Details : Byte elements from 'in0' & 'in1' are copied selectively to 69 Details : Byte elements from 'in0' & 'in1' are copied selectively to
70 'out0' as per control vector 'mask0' 70 'out0' as per control vector 'mask0'
71 */ 71 */
72 #define VSHF_B2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1) { \ 72 #define VSHF_B2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1) { \
73 out0 = (RTYPE) __msa_vshf_b((v16i8) mask0, (v16i8) in1, (v16i8) in0); \ 73 out0 = (RTYPE) __msa_vshf_b((v16i8) mask0, (v16i8) in1, (v16i8) in0); \
74 out1 = (RTYPE) __msa_vshf_b((v16i8) mask1, (v16i8) in3, (v16i8) in2); \ 74 out1 = (RTYPE) __msa_vshf_b((v16i8) mask1, (v16i8) in3, (v16i8) in2); \
75 } 75 }
76 #define VSHF_B2_UB(...) VSHF_B2(v16u8, __VA_ARGS__) 76 #define VSHF_B2_UB(...) VSHF_B2(v16u8, __VA_ARGS__)
77
78 #define VSHF_W2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1) { \
79 out0 = (RTYPE) __msa_vshf_w((v4i32) mask0, (v4i32) in1, (v4i32) in0); \
fbarchard1 2016/09/26 18:04:34 style nit - I'd prefer we dont end up with macros
80 out1 = (RTYPE) __msa_vshf_w((v4i32) mask1, (v4i32) in3, (v4i32) in2); \
81 }
82 #define VSHF_W2_UB(...) VSHF_W2(v16u8, __VA_ARGS__)
83 #define VSHF_W2_SB(...) VSHF_W2(v16i8, __VA_ARGS__)
84 #define VSHF_W4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
85 mask0, mask1, mask2, mask3, \
86 out0, out1, out2, out3) { \
87 VSHF_W2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1) \
88 VSHF_W2(RTYPE, in4, in5, in6, in7, mask2, mask3, out2, out3) \
89 }
90 #define VSHF_W4_UB(...) VSHF_W4(v16u8, __VA_ARGS__)
91
77 #endif /* !defined(LIBYUV_DISABLE_MSA) && defined(__mips_msa) */ 92 #endif /* !defined(LIBYUV_DISABLE_MSA) && defined(__mips_msa) */
78 #endif /* __MACROS_MSA_H__ */ 93 #endif /* __MACROS_MSA_H__ */
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