Subzero, MIPS32: lowerSelect for i64

tests_lit/llvm2ice_tests/select-opt.ll

 ; Simple test of the select instruction.  The CHECK lines are only
 ; checking for basic instruction patterns that should be present
 ; regardless of the optimization level, so there are no special OPTM1
 ; match lines.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
@@ skipping 60 matching lines @@
 ; ARM32: tst
 ; ARM32-Om1: movne {{.*}}, #10
 ; ARM32-O2: movne [[REG]], #10
 ; ARM32: bl {{.*}} useInt
 ; ARM32: bl {{.*}} useInt
 ; ARM32: bl {{.*}} useInt
 ; ARM32: bx lr
 ; MIPS32-LABEL: testSelect
 ; MIPS32: slt {{.*}}
 ; MIPS32: movn {{.*}}
-; MIPS32: move {{.*}}
 
 ; Check for valid addressing mode in the cmp instruction when the
 ; operand is an immediate.
 define internal i32 @testSelectImm32(i32 %a, i32 %b) {
 entry:
   %cond = select i1 false, i32 %a, i32 %b
   ret i32 %cond
 }
 ; CHECK-LABEL: testSelectImm32
 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
 ; ARM32-LABEL: testSelectImm32
 ; ARM32-NOT: cmp #{{.*}},
 ; MIPS32-LABEL: testSelectImm32
 ; MIPS32: movn {{.*}}
-; MIPS32: move {{.*}}
 
 ; Check for valid addressing mode in the cmp instruction when the
 ; operand is an immediate.  There is a different x86-32 lowering
 ; sequence for 64-bit operands.
 define internal i64 @testSelectImm64(i64 %a, i64 %b) {
 entry:
   %cond = select i1 true, i64 %a, i64 %b
   ret i64 %cond
 }
 ; CHECK-LABEL: testSelectImm64
 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
 ; ARM32-LABEL: testSelectImm64
 ; ARM32-NOT: cmp #{{.*}},
 ; MIPS32-LABEL: testSelectImm64
+; MIPS32: movn
+; MIPS32: movn