Subzero, MIPS32: lowerSelect for i64

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 3427 matching lines @@
       UnimplementedLoweringError(this, Instr);
     }
   }
   _ret(getPhysicalRegister(RegMIPS32::Reg_RA), Reg);
 }
 
 void TargetMIPS32::lowerSelect(const InstSelect *Instr) {
   Variable *Dest = Instr->getDest();
   const Type DestTy = Dest->getType();
 
-  if (DestTy == IceType_i64 || isVectorType(DestTy)) {
+  if (isVectorType(DestTy)) {
     UnimplementedLoweringError(this, Instr);
     return;
   }
 
-  Variable *DestR = legalizeToReg(Dest);
-  Variable *SrcTR = legalizeToReg(Instr->getTrueOperand());
-  Variable *SrcFR = legalizeToReg(Instr->getFalseOperand());
+  Variable *DestR = nullptr;
+  Variable *DestHiR = nullptr;
+  Variable *SrcTR = nullptr;
+  Variable *SrcTHiR = nullptr;
+  Variable *SrcFR = nullptr;
+  Variable *SrcFHiR = nullptr;
+
+  if (DestTy == IceType_i64) {
+    DestR = llvm::cast<Variable>(loOperand(Dest));
+    DestHiR = llvm::cast<Variable>(hiOperand(Dest));
+    SrcTR = legalizeToReg(loOperand(Instr->getTrueOperand()));
+    SrcTHiR = legalizeToReg(hiOperand(Instr->getTrueOperand()));
+    SrcFR = legalizeToReg(loOperand(Instr->getFalseOperand()));
+    SrcFHiR = legalizeToReg(hiOperand(Instr->getFalseOperand()));
+  } else {
+    SrcTR = legalizeToReg(Instr->getTrueOperand());
+    SrcFR = legalizeToReg(Instr->getFalseOperand());
+  }
 
   Variable *ConditionR = legalizeToReg(Instr->getCondition());
 
   assert(Instr->getCondition()->getType() == IceType_i1);
 
   switch (DestTy) {
   case IceType_i1:
   case IceType_i8:
   case IceType_i16:
   case IceType_i32:
     _movn(SrcFR, SrcTR, ConditionR);
+    _mov(Dest, SrcFR);
+    break;
+  case IceType_i64:
+    _movn(SrcFR, SrcTR, ConditionR);
+    _movn(SrcFHiR, SrcTHiR, ConditionR);
     _mov(DestR, SrcFR);
-    _mov(Dest, DestR);
+    _mov(DestHiR, SrcFHiR);
     break;
   case IceType_f32:
     _movn_s(SrcFR, SrcTR, ConditionR);
-    _mov(DestR, SrcFR);
-    _mov(Dest, DestR);
+    _mov(Dest, SrcFR);
     break;
   case IceType_f64:
     _movn_d(SrcFR, SrcTR, ConditionR);
-    _mov(DestR, SrcFR);
-    _mov(Dest, DestR);
+    _mov(Dest, SrcFR);
     break;
   default:
     UnimplementedLoweringError(this, Instr);
   }
 }
 
 void TargetMIPS32::lowerShuffleVector(const InstShuffleVector *Instr) {
   UnimplementedLoweringError(this, Instr);
 }
 
@@ skipping 473 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice