Subzero, MIPS32: Intrinsic calls Ctlz and Cttz for i64

src/IceAssemblerMIPS32.cpp

Index: src/IceAssemblerMIPS32.cpp
diff --git a/src/IceAssemblerMIPS32.cpp b/src/IceAssemblerMIPS32.cpp
index aede16c0ecfd926b29929a272ec06ebc44aeb4d5..236abeb0db25478c3fc712205b230d3b2db31629 100644
--- a/src/IceAssemblerMIPS32.cpp
+++ b/src/IceAssemblerMIPS32.cpp
@@ -521,6 +521,14 @@ void AssemblerMIPS32::div_s(const Operand *OpFd, const Operand *OpFs,
   emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "div.s");
 }
 
+void AssemblerMIPS32::lui(const Operand *OpRt, const uint16_t Imm) {
+  IValueT Opcode = 0x3C000000;
+  const IValueT Rt = encodeGPRegister(OpRt, "Rt", "lui");
+  Opcode |= Rt << 16;
+  Opcode |= Imm;
+  emitInst(Opcode);
+}
+
 void AssemblerMIPS32::lw(const Operand *OpRt, const Operand *OpBase,
                          const uint32_t Offset) {
   switch (OpRt->getType()) {
@@ -627,7 +635,7 @@ void AssemblerMIPS32::movf(const Operand *OpRd, const Operand *OpRs,
 
 void AssemblerMIPS32::movn(const Operand *OpRd, const Operand *OpRs,
                            const Operand *OpRt) {
-  static constexpr IValueT Opcode = 0x44000013;
+  static constexpr IValueT Opcode = 0x0000000B;
   emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "movn");
 }