Subzero, MIPS32: Intrinsic calls Ctlz and Cttz for i64

tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll

 ; This tests the NaCl intrinsics not related to atomic operations.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 --sandbox -i %s --args -O2 \
 ; RUN:   -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 --sandbox -i %s --args -Om1 \
 ; RUN:   -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
@@ skipping 400 matching lines @@
   %r = call i32 @llvm.ctlz.i32(i32 123456, i1 false)
   ret i32 %r
 }
 ; Could potentially constant fold this, but the front-end should have done that.
 ; The dest operand must be a register and the source operand must be a register
 ; or memory.
 ; CHECK-LABEL: test_ctlz_32_const
 ; CHECK: bsr e{{.*}},{{.*}}e{{.*}}
 ; ARM32-LABEL: test_ctlz_32_const
 ; ARM32: clz
+; MIPS32-LABEL: test_ctlz_32_const
+; MIPS32: clz
 
 define internal i32 @test_ctlz_32_ignored(i32 %x) {
 entry:
   %ignored = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
   ret i32 1
 }
 ; CHECKO2REM-LABEL: test_ctlz_32_ignored
 ; CHECKO2REM-NOT: bsr
 
 define internal i64 @test_ctlz_64(i64 %x) {
@@ skipping 12 matching lines @@
 ; CHECK: xor [[REG_RES2]],0x1f
 ; CHECK: test [[REG_UPPER:.*]],[[REG_UPPER]]
 ; CHECK: cmove [[REG_RES2]],[[REG_RES1]]
 ; CHECK: mov {{.*}},0x0
 ; ARM32-LABEL: test_ctlz_64
 ; ARM32: clz
 ; ARM32: cmp {{.*}}, #0
 ; ARM32: add {{.*}}, #32
 ; ARM32: clzne
 ; ARM32: mov {{.*}}, #0
+; MIPS32-LABEL: test_ctlz_64
+; MIPS32: clz
+; MIPS32: clz
+; MIPS32: addiu
+; MIPS32: movn
+; MIPS32: addiu
 
 define internal i32 @test_ctlz_64_const(i64 %x) {
 entry:
   %r = call i64 @llvm.ctlz.i64(i64 123456789012, i1 false)
   %r2 = trunc i64 %r to i32
   ret i32 %r2
 }
 ; CHECK-LABEL: test_ctlz_64_const
 ; CHECK: bsr e{{.*}},{{.*}}e{{.*}}
 ; CHECK: bsr e{{.*}},{{.*}}e{{.*}}
 ; ARM32-LABEL: test_ctlz_64
 ; ARM32: clz
 ; ARM32: clzne
+; MIPS32-LABEL: test_ctlz_64_const
+; MIPS32: clz
+; MIPS32: clz
+; MIPS32: addiu
+; MIPS32: movn
+; MIPS32: addiu
 
 define internal i32 @test_ctlz_64_ignored(i64 %x) {
 entry:
   %ignored = call i64 @llvm.ctlz.i64(i64 1234567890, i1 false)
   ret i32 2
 }
 ; CHECKO2REM-LABEL: test_ctlz_64_ignored
 ; CHECKO2REM-NOT: bsr
 
 define internal i32 @test_cttz_32(i32 %x) {
@@ skipping 31 matching lines @@
 ; CHECK: cmove [[REG_RES2]],[[REG_RES1]]
 ; CHECK: mov {{.*}},0x0
 ; ARM32-LABEL: test_cttz_64
 ; ARM32: rbit
 ; ARM32: rbit
 ; ARM32: clz
 ; ARM32: cmp {{.*}}, #0
 ; ARM32: add {{.*}}, #32
 ; ARM32: clzne
 ; ARM32: mov {{.*}}, #0
+; MIPS32-LABEL: test_cttz_64
+; MIPS32: addiu
+; MIPS32: nor
+; MIPS32: and
+; MIPS32: clz
+; MIPS32: li
+; MIPS32: subu
+; MIPS32: addiu
+; MIPS32: nor
+; MIPS32: and
+; MIPS32: clz
+; MIPS32: li
+; MIPS32: subu
 
 define internal i32 @test_popcount_32(i32 %x) {
 entry:
   %r = call i32 @llvm.ctpop.i32(i32 %x)
   ret i32 %r
 }
 ; CHECK-LABEL: test_popcount_32
 ; CHECK: call {{.*}} R_{{.*}} __popcountsi2
 ; ARM32-LABEL: test_popcount_32
 ; ARM32: bl {{.*}} __popcountsi2
@@ skipping 82 matching lines @@
 ; CHECK: lea {{.*}},[esp+0x10]
 ; CHECK: lea {{.*}},[esp+0x10]
 ; CHECK: call
 ; CHECK: mov esp,{{.*}}
 ; CHECK: mov esp,ebp
 ; ARM32-LABEL: test_stacksave_multiple
 ; ARM32: mov {{.*}}, sp
 ; ARM32: mov {{.*}}, sp
 ; ARM32: mov {{.*}}, sp
 ; ARM32: mov sp, {{.*}}