Subzero, MIPS32: Intrinsic calls Ctlz and Cttz for i64

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 2614 matching lines @@
   }
   case InstCast::Uitofp: {
     if (llvm::isa<Variable64On32>(Dest)) {
       llvm::report_fatal_error("i64-to-fp should have been prelowered.");
       return;
     }
     UnimplementedLoweringError(this, Instr);
     break;
   }
   case InstCast::Bitcast: {
+    Operand *Src0 = Instr->getSrc(0);
+    if (DestTy == Src0->getType()) {
+      auto *Assign = InstAssign::create(Func, Dest, Src0);
+      lowerAssign(Assign);
+      return;
+    }
     switch (DestTy) {
     case IceType_NUM:
     case IceType_void:
       llvm::report_fatal_error("Unexpected bitcast.");
     case IceType_i1:
       UnimplementedLoweringError(this, Instr);
       break;
     case IceType_i8:
       assert(Src0->getType() == IceType_v8i1);
       llvm::report_fatal_error(
@@ skipping 384 matching lines @@
     assert(SrcTy == IceType_i32 || SrcTy == IceType_i64);
     switch (SrcTy) {
     case IceType_i32: {
       auto *T = I32Reg();
       auto *SrcR = legalizeToReg(Src);
       _clz(T, SrcR);
       _mov(Dest, T);
       break;
     }
     case IceType_i64: {
-      UnimplementedLoweringError(this, Instr);
+      auto *T1 = I32Reg();
+      auto *T2 = I32Reg();
+      auto *T3 = I32Reg();
+      auto *T4 = I32Reg();
+      auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
+      auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+      Variable *SrcHiR = legalizeToReg(hiOperand(Src));
+      Variable *SrcLoR = legalizeToReg(loOperand(Src));
+      _clz(T1, SrcHiR);
+      _clz(T2, SrcLoR);
+      _addiu(T3, T2, 32);
+      _movn(T3, T1, SrcHiR);
+      _addiu(T4, getZero(), 0);
+      _mov(DestHi, T4);
+      _mov(DestLo, T3);
       break;
     }
     default:
       llvm::report_fatal_error("Control flow should never have reached here.");
     }
     break;
   }
   case Intrinsics::Cttz: {
     auto *Src = Instr->getArg(0);
     const Type SrcTy = Src->getType();
@@ skipping 10 matching lines @@
       _addiu(T1, SrcR, -1);
       _not(T2, SrcR);
       _and(T3, T2, T1);
       _clz(T4, T3);
       _addiu(T5, getZero(), 32);
       _subu(T6, T5, T4);
       _mov(Dest, T6);
       break;
     }
     case IceType_i64: {
-      UnimplementedLoweringError(this, Instr);
+      auto *THi1 = I32Reg();
+      auto *THi2 = I32Reg();
+      auto *THi3 = I32Reg();
+      auto *THi4 = I32Reg();
+      auto *THi5 = I32Reg();
+      auto *THi6 = I32Reg();
+      auto *TLo1 = I32Reg();
+      auto *TLo2 = I32Reg();
+      auto *TLo3 = I32Reg();
+      auto *TLo4 = I32Reg();
+      auto *TLo5 = I32Reg();
+      auto *TLo6 = I32Reg();
+      auto *TResHi = I32Reg();
+      auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
+      auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+      Variable *SrcHiR = legalizeToReg(hiOperand(Src));
+      Variable *SrcLoR = legalizeToReg(loOperand(Src));
+      _addiu(THi1, SrcHiR, -1);
+      _not(THi2, SrcHiR);
+      _and(THi3, THi2, THi1);
+      _clz(THi4, THi3);
+      _addiu(THi5, getZero(), 64);
+      _subu(THi6, THi5, THi4);
+      _addiu(TLo1, SrcLoR, -1);
+      _not(TLo2, SrcLoR);
+      _and(TLo3, TLo2, TLo1);
+      _clz(TLo4, TLo3);
+      _addiu(TLo5, getZero(), 32);
+      _subu(TLo6, TLo5, TLo4);
+      _movn(THi6, TLo6, SrcLoR);
+      _addiu(TResHi, getZero(), 0);
+      _mov(DestHi, TResHi);
+      _mov(DestLo, THi6);
       break;
     }
     default:
       llvm::report_fatal_error("Control flow should never have reached here.");
     }
     return;
   }
   case Intrinsics::Fabs: {
     if (isScalarFloatingType(DestTy)) {
       Variable *T = makeReg(DestTy);
@@ skipping 899 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice