| OLD | NEW |
| 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #ifndef VM_CONSTANTS_ARM64_H_ | 5 #ifndef VM_CONSTANTS_ARM64_H_ |
| 6 #define VM_CONSTANTS_ARM64_H_ | 6 #define VM_CONSTANTS_ARM64_H_ |
| 7 | 7 |
| 8 #include "platform/assert.h" | 8 #include "platform/assert.h" |
| 9 | 9 |
| 10 namespace dart { | 10 namespace dart { |
| (...skipping 347 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 358 }; | 358 }; |
| 359 | 359 |
| 360 // C3.5.1 | 360 // C3.5.1 |
| 361 enum AddSubShiftExtOp { | 361 enum AddSubShiftExtOp { |
| 362 AddSubShiftExtMask = 0x1f000000, | 362 AddSubShiftExtMask = 0x1f000000, |
| 363 AddSubShiftExtFixed = DPRegisterFixed | B24, | 363 AddSubShiftExtFixed = DPRegisterFixed | B24, |
| 364 ADD = AddSubShiftExtFixed, | 364 ADD = AddSubShiftExtFixed, |
| 365 SUB = AddSubShiftExtFixed | B30, | 365 SUB = AddSubShiftExtFixed | B30, |
| 366 }; | 366 }; |
| 367 | 367 |
| 368 // C3.5.8 |
| 369 enum MiscDP2SourceOp { |
| 370 MiscDP2SourceMask = 0x5fe00000, |
| 371 MiscDP2SourceFixed = DPRegisterFixed | B28 | B23 | B22, |
| 372 UDIV = MiscDP2SourceFixed | B11, |
| 373 SDIV = MiscDP2SourceFixed | B11 | B10, |
| 374 LSLV = MiscDP2SourceFixed | B13, |
| 375 LSRV = MiscDP2SourceFixed | B13 | B10, |
| 376 ASRV = MiscDP2SourceFixed | B13 | B11, |
| 377 }; |
| 378 |
| 379 // C3.5.9 |
| 380 enum MiscDP3SourceOp { |
| 381 MiscDP3SourceMask = 0x1f000000, |
| 382 MiscDP3SourceFixed = DPRegisterFixed | B28 | B24, |
| 383 MADD = MiscDP3SourceFixed, |
| 384 }; |
| 385 |
| 386 // C3.5.10 |
| 368 enum LogicalShiftOp { | 387 enum LogicalShiftOp { |
| 369 LogicalShiftMask = 0x1f000000, | 388 LogicalShiftMask = 0x1f000000, |
| 370 LogicalShiftFixed = DPRegisterFixed, | 389 LogicalShiftFixed = DPRegisterFixed, |
| 371 AND = LogicalShiftFixed, | 390 AND = LogicalShiftFixed, |
| 372 BIC = LogicalShiftFixed | B21, | 391 BIC = LogicalShiftFixed | B21, |
| 373 ORR = LogicalShiftFixed | B29, | 392 ORR = LogicalShiftFixed | B29, |
| 374 ORN = LogicalShiftFixed | B29 | B21, | 393 ORN = LogicalShiftFixed | B29 | B21, |
| 375 EOR = LogicalShiftFixed | B30, | 394 EOR = LogicalShiftFixed | B30, |
| 376 EON = LogicalShiftFixed | B30 | B21, | 395 EON = LogicalShiftFixed | B30 | B21, |
| 377 ANDS = LogicalShiftFixed | B30 | B29, | 396 ANDS = LogicalShiftFixed | B30 | B29, |
| (...skipping 13 matching lines...) Expand all Loading... |
| 391 _V(System) \ | 410 _V(System) \ |
| 392 _V(TestAndBranch) \ | 411 _V(TestAndBranch) \ |
| 393 _V(UnconditionalBranch) \ | 412 _V(UnconditionalBranch) \ |
| 394 _V(UnconditionalBranchReg) \ | 413 _V(UnconditionalBranchReg) \ |
| 395 _V(LoadStoreReg) \ | 414 _V(LoadStoreReg) \ |
| 396 _V(AddSubImm) \ | 415 _V(AddSubImm) \ |
| 397 _V(LogicalImm) \ | 416 _V(LogicalImm) \ |
| 398 _V(MoveWide) \ | 417 _V(MoveWide) \ |
| 399 _V(PCRel) \ | 418 _V(PCRel) \ |
| 400 _V(AddSubShiftExt) \ | 419 _V(AddSubShiftExt) \ |
| 420 _V(MiscDP2Source) \ |
| 421 _V(MiscDP3Source) \ |
| 401 _V(LogicalShift) \ | 422 _V(LogicalShift) \ |
| 402 | 423 |
| 403 | 424 |
| 404 enum Shift { | 425 enum Shift { |
| 405 kNoShift = -1, | 426 kNoShift = -1, |
| 406 LSL = 0, // Logical shift left | 427 LSL = 0, // Logical shift left |
| 407 LSR = 1, // Logical shift right | 428 LSR = 1, // Logical shift right |
| 408 ASR = 2, // Arithmetic shift right | 429 ASR = 2, // Arithmetic shift right |
| 409 ROR = 3, // Rotate right | 430 ROR = 3, // Rotate right |
| 410 kMaxShift = 4, | 431 kMaxShift = 4, |
| (...skipping 332 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 743 static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); } | 764 static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); } |
| 744 | 765 |
| 745 private: | 766 private: |
| 746 DISALLOW_ALLOCATION(); | 767 DISALLOW_ALLOCATION(); |
| 747 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); | 768 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); |
| 748 }; | 769 }; |
| 749 | 770 |
| 750 } // namespace dart | 771 } // namespace dart |
| 751 | 772 |
| 752 #endif // VM_CONSTANTS_ARM64_H_ | 773 #endif // VM_CONSTANTS_ARM64_H_ |
| OLD | NEW |