Thumb2 Backend: Arithmetic instruction encoding methods

src/arm/assembler-thumb32.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 312 matching lines @@
 
 Instr Assembler::thumb32_3reg_lsl(Register rd,
                                   const MemOperand& x) {
   ASSERT(x.rn_.is_valid() && x.rm_.is_valid());  // is Register, both valid
   uint8_t imm2 = 0;
   if (x.shift_op_ == LSL && is_uint2(x.shift_imm_)) {
     imm2 = x.shift_imm_ & 3;
     return (x.rn_.code()*BH0 | rd.code()*B12 | imm2*B4 | x.rm_.code());
   }
   switch (x.shift_op_) {
-    case LSL:  // TODO(rkrithiv): call method to encode lsl instruction
-    case LSR:  // TODO(rkrithiv): call method to encode lsr instruction
-    case ASR:  // TODO(rkrithiv): call method to encode asr instruction
+    case LSL: lsl_thumb(ip, Operand(x.rm_, LSL, x.shift_imm_), LeaveCC, al);
+              break;
+    case LSR: lsr_thumb(ip, Operand(x.rm_, LSR, x.shift_imm_), LeaveCC, al);
+              break;
+    case ASR: asr_thumb(ip, Operand(x.rm_, ASR, x.shift_imm_), LeaveCC, al);
+              break;
     default:  return (x.rn_.code()*BH0 | rd.code()*B12 | x.rm_.code());
   }
   return (x.rn_.code()*BH0 | rd.code()*B12 | ip.code());
 }
 
 
 Instr Assembler::thumb32_4reg(Register dst, Register src1, Register src2,
                               Register srcA) {
   return (src1.code()*BH0 | srcA.code()*B12 | dst.code()*B8 | src2.code());
 }
@@ skipping 459 matching lines @@
 void Assembler::strd_imm_t1(Register src1, Register src2,
                      const MemOperand& dst) {
     emit32(thumb32_mode6(STRD_32_IMM2, STRD_32_IMM2_OP2) |
            thumb32_3reg_zero_extend_imm8(src1, src2, dst));
 }
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM