Thumb2 Backend: Arithmetic instruction encoding methods

src/arm/assembler-arm.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 828 matching lines @@
   void blx(Label* L)  { blx(branch_offset(L, false)); }  // v5 and above
 
   // Data-processing instructions
 
   void and_(Register dst, Register src1, const Operand& src2,
             SBit s = LeaveCC, Condition cond = al);
   void and_imm_t1(Register dst, Register src1, SBit s, Condition cond,
                   uint32_t i, uint32_t imm3, uint32_t imm8);
   void and_reg_t2(Register dst, Register src1, const Operand& src2,
                   SBit s, Condition cond);
+  void and_thumb(Register dst, Register src1, const Operand& src2,
+                 SBit s, Condition cond);
 
   void eor(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
   void eor_imm_t1(Register dst, Register src1, SBit s, Condition cond,
                   uint32_t i, uint32_t imm3, uint32_t imm8);
   void eor_reg_t2(Register dst, Register src1, const Operand& src2,
                   SBit s, Condition cond);
+  void eor_thumb(Register dst, Register src1, const Operand& src2,
+                 SBit s, Condition cond);
 
   void sub(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
   void sub(Register dst, Register src1, Register src2,
            SBit s = LeaveCC, Condition cond = al) {
     sub(dst, src1, Operand(src2), s, cond);
   }
   void sub_imm_t3(Register dst, Register src1, SBit s, Condition cond,
                   uint32_t i, uint32_t imm3, uint32_t imm8);
   void sub_imm_t4(Register dst, Register src1, const Operand& src2,
                   SBit s, Condition cond);
   void sub_reg_t3(Register dst, Register src1, const Operand& src2,
                   SBit s, Condition cond);
+  void sub_thumb(Register dst, Register src1, const Operand& src2,
+                 SBit s, Condition cond);
 
   void rsb(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
   void rsb_imm_t2(Register dst, Register src1, SBit s, Condition cond,
                   uint32_t i, uint32_t imm3, uint32_t imm8);
   void rsb_reg_t1(Register dst, Register src1, const Operand& src2,
                   SBit s, Condition cond);
+  void rsb_thumb(Register dst, Register src1, const Operand& src2,
+                 SBit s, Condition cond);
 
   void add(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
   void add(Register dst, Register src1, Register src2,
            SBit s = LeaveCC, Condition cond = al) {
     add(dst, src1, Operand(src2), s, cond);
   }
   void add_imm_t3(Register dst, Register src1, SBit s, Condition cond,
                   uint32_t i, uint32_t imm3, uint32_t imm8);
   void add_imm_t4(Register dst, Register src1, const Operand& src2,
                   SBit s, Condition cond);
   void add_reg_t3(Register dst, Register src1, const Operand& src2,
                   SBit s, Condition cond);
+  void add_thumb(Register dst, Register src1, const Operand& src2,
+                 SBit s, Condition cond);
 
   void adc(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
   void adc_imm_t1(Register dst, Register src1, SBit s, Condition cond,
                   uint32_t i, uint32_t imm3, uint32_t imm8);
   void adc_reg_t2(Register dst, Register src1, const Operand& src2,
                   SBit s, Condition cond);
+  void adc_thumb(Register dst, Register src1, const Operand& src2,
+                 SBit s, Condition cond);
 
   void sbc(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
   void sbc_imm_t1(Register dst, Register src1, SBit s, Condition cond,
                   uint32_t i, uint32_t imm3, uint32_t imm8);
   void sbc_reg_t2(Register dst, Register src1, const Operand& src2,
                   SBit s, Condition cond);
+  void sbc_thumb(Register dst, Register src1, const Operand& src2,
+                 SBit s, Condition cond);
 
   void rsc(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
 
   void tst(Register src1, const Operand& src2, Condition cond = al);
   void tst(Register src1, Register src2, Condition cond = al) {
     tst(src1, Operand(src2), cond);
   }
   void tst_imm_t1(Register src1, Condition cond,
                   uint32_t i, uint32_t imm3, uint32_t imm8);
   void tst_reg_t2(Register src1, const Operand& src2, Condition cond);
+  void tst_thumb(Register src1, const Operand& src2, Condition cond);
 
   void teq(Register src1, const Operand& src2, Condition cond = al);
   void teq_imm_t1(Register src1, Condition cond,
                   uint32_t i, uint32_t imm3, uint32_t imm8);
   void teq_reg_t1(Register src1, const Operand& src2, Condition cond);
+  void teq_thumb(Register src1, const Operand& src2, Condition cond);
 
   void cmp(Register src1, const Operand& src2, Condition cond = al);
   void cmp(Register src1, Register src2, Condition cond = al) {
     cmp(src1, Operand(src2), cond);
   }
   void cmp_imm_t2(Register src1, Condition cond,
                   uint32_t i, uint32_t imm3, uint32_t imm8);
   void cmp_reg_t3(Register src1, const Operand& src2, Condition cond);
+  void cmp_thumb(Register src1, const Operand& src2, Condition cond);
   void cmp_raw_immediate(Register src1, int raw_immediate, Condition cond = al);
 
   void cmn(Register src1, const Operand& src2, Condition cond = al);
   void cmn_imm_t1(Register src1, Condition cond,
                   uint32_t i, uint32_t imm3, uint32_t imm8);
   void cmn_reg_t2(Register src1, const Operand& src2, Condition cond);
+  void cmn_thumb(Register src1, const Operand& src2, Condition cond);
 
   void orr(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
   void orr(Register dst, Register src1, Register src2,
            SBit s = LeaveCC, Condition cond = al) {
     orr(dst, src1, Operand(src2), s, cond);
   }
   void orr_imm_t1(Register dst, Register src1, SBit s, Condition cond,
                   uint32_t i, uint32_t imm3, uint32_t imm8);
   void orr_reg_t2(Register dst, Register src1, const Operand& src2,
                   SBit s, Condition cond);
+  void orr_thumb(Register dst, Register src1, const Operand& src2,
+                 SBit s, Condition cond);
 
   void mov(Register dst, const Operand& src,
            SBit s = LeaveCC, Condition cond = al);
   void mov(Register dst, Register src, SBit s = LeaveCC, Condition cond = al) {
     mov(dst, Operand(src), s, cond);
   }
   void mov_imm_t2(Register dst, SBit s, Condition cond,
                   uint32_t i, uint32_t imm3, uint32_t imm8);
   void mov_imm_t3(Register dst, const Operand& src,
                   SBit s, Condition cond);
   void mov_reg_t3(Register dst, const Operand& src,
                   SBit s, Condition cond);
+  void mov_thumb(Register dst, const Operand& src,
+                 SBit s, Condition cond);
 
   void lsl_imm_t2(Register dst, const Operand& src, SBit s, Condition cond);
   void lsl_reg_t2(Register dst, const Operand& src, SBit s, Condition cond);
+  void lsl_thumb(Register dst, const Operand& src, SBit s, Condition cond);
   void lsr_imm_t2(Register dst, const Operand& src, SBit s, Condition cond);
   void lsr_reg_t2(Register dst, const Operand& src, SBit s, Condition cond);
+  void lsr_thumb(Register dst, const Operand& src, SBit s, Condition cond);
   void asr_imm_t2(Register dst, const Operand& src, SBit s, Condition cond);
   void asr_reg_t2(Register dst, const Operand& src, SBit s, Condition cond);
+  void asr_thumb(Register dst, const Operand& src, SBit s, Condition cond);
   void ror_imm_t2(Register dst, const Operand& src, SBit s, Condition cond);
   void ror_reg_t2(Register dst, const Operand& src, SBit s, Condition cond);
+  void ror_thumb(Register dst, const Operand& src, SBit s, Condition cond);
 
   // Load the position of the label relative to the generated code object
   // pointer in a register.
   void mov_label_offset(Register dst, Label* label);
 
   // ARMv7 instructions for loading a 32 bit immediate in two instructions.
   // This may actually emit a different mov instruction, but on an ARMv7 it
   // is guaranteed to only emit one instruction.
   void movw(Register reg, uint32_t immediate, Condition cond = al);
   // The constant for movt should be in the range 0-0xffff.
   void movt(Register reg, uint32_t immediate, Condition cond = al);
+  void movt_thumb(Register reg, uint32_t immediate, Condition cond = al);
 
   void bic(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
   void bic_imm_t1(Register dst, Register src1, SBit s, Condition cond,
                   uint32_t i, uint32_t imm3, uint32_t imm8);
   void bic_reg_t2(Register dst, Register src1, const Operand& src2,
                   SBit s, Condition cond);
+  void bic_thumb(Register dst, Register src1, const Operand& src2,
+                 SBit s, Condition cond);
 
   void mvn(Register dst, const Operand& src,
            SBit s = LeaveCC, Condition cond = al);
   void mvn_imm_t1(Register dst, SBit s, Condition cond,
                   uint32_t i, uint32_t imm3, uint32_t imm8);
   void mvn_reg_t2(Register dst, const Operand& src,
                   SBit s, Condition cond);
+  void mvn_thumb(Register dst, const Operand& src,
+                 SBit s, Condition cond);
 
   // Multiply instructions
 
   void mla(Register dst, Register src1, Register src2, Register srcA,
            SBit s = LeaveCC, Condition cond = al);
 
   void mls(Register dst, Register src1, Register src2, Register srcA,
            Condition cond = al);
 
   void sdiv(Register dst, Register src1, Register src2,
             Condition cond = al);
 
   void mul(Register dst, Register src1, Register src2,
            SBit s = LeaveCC, Condition cond = al);
   void mul_t2(Register dst, Register src1, Register src2,
               SBit s, Condition cond);
+  void mul_thumb(Register dst, Register src1, Register src2,
+                 SBit s, Condition cond);
 
   void smlal(Register dstL, Register dstH, Register src1, Register src2,
              SBit s = LeaveCC, Condition cond = al);
 
   void smull(Register dstL, Register dstH, Register src1, Register src2,
              SBit s = LeaveCC, Condition cond = al);
 
   void umlal(Register dstL, Register dstH, Register src1, Register src2,
              SBit s = LeaveCC, Condition cond = al);
 
@@ skipping 330 matching lines @@
     ldr(dst, MemOperand(sp, 4, PostIndex), cond);
   }
 
   void pop() {
     add(sp, sp, Operand(kPointerSize));
   }
 
   // Jump unconditionally to given label.
   void jmp(Label* L) { b(L, al); }
 
+  void it_thumb(Condition cond, int num_instr, bool cond2 = false,
+                bool cond3 = false, bool cond4 = false);
+  inline void emit_it(Condition cond);
+
   static bool use_immediate_embedded_pointer_loads(
       const Assembler* assembler) {
     return CpuFeatures::IsSupported(MOVW_MOVT_IMMEDIATE_LOADS) &&
         (assembler == NULL || !assembler->predictable_code_size());
   }
 
   // Check the code size generated from label to here.
   int SizeOfCodeGeneratedSince(Label* label) {
     return pc_offset() - label->pos();
   }
@@ skipping 400 matching lines @@
  public:
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBuffer();
   }
 };
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_ARM_ASSEMBLER_ARM_H_