[Subzero][MIPS32] Implements 64-bit shl, lshr, ashr for MIPS

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
@@ skipping 502 matching lines @@
 
 ; ARM32-LABEL: shl64BitSigned
 ; ARM32: rsb     [[T0:r[0-9]+]], r2, #32
 ; ARM32: lsr     [[T1:r[0-9]+]], r0, [[T0]]
 ; ARM32: orr     [[T2:r[0-9]+]], [[T1]], r1, lsl r2
 ; ARM32: sub     [[T3:r[0-9]+]], r2, #32
 ; ARM32: cmp     [[T3]], #0
 ; ARM32: lslge   [[T2]], r0, [[T3]]
 ; ARM32: lsl     r{{[0-9]+}}, r0, r2
 
+; MIPS32-LABEL: shl64BitSigned
+; MIPS32: sllv  [[T1:.*]],[[A_HI:.*]],[[B_LO:.*]]
+; MIPS32: nor   [[T2:.*]],[[B_LO]],zero
+; MIPS32: srl   [[T3:.*]],[[A_LO:.*]],0x1
+; MIPS32: srlv  [[T4:.*]],[[T3]],[[T2]]
+; MIPS32: or    [[T_HI:.*]],[[T1]],[[T4]]
+; MIPS32: sllv  [[T_LO:.*]],[[A_LO]],[[B_LO]]
+; MIPS32: move  [[T1_LO:.*]],[[T_LO]]
+; MIPS32: andi  [[T5:.*]],[[B_LO]],0x20
+; MIPS32: movn  [[T_HI]],[[T_LO]],[[T5]]
+; MIPS32: movn  [[T1_LO]],zero,[[T5]]
+; MIPS32: move  v1,[[T_HI]]
+
 define internal i32 @shl64BitSignedTrunc(i64 %a, i64 %b) {
 entry:
   %shl = shl i64 %a, %b
   %result = trunc i64 %shl to i32
   ret i32 %result
 }
 ; CHECK-LABEL: shl64BitSignedTrunc
 ; CHECK: mov
 ; CHECK: shl e
 ; CHECK: test {{.*}},0x20
@@ skipping 27 matching lines @@
 
 ; ARM32-LABEL: shl64BitUnsigned
 ; ARM32: rsb
 ; ARM32: lsr
 ; ARM32: orr
 ; ARM32: sub
 ; ARM32: cmp
 ; ARM32: lslge
 ; ARM32: lsl
 
+; MIPS32-LABEL: shl64BitUnsigned
+; MIPS32: sllv  [[T1:.*]],[[A_HI:.*]],[[B_LO:.*]]
+; MIPS32: nor   [[T2:.*]],[[B_LO]],zero
+; MIPS32: srl   [[T3:.*]],[[A_LO:.*]],0x1
+; MIPS32: srlv  [[T4:.*]],[[T3]],[[T2]]
+; MIPS32: or    [[T_HI:.*]],[[T1]],[[T4]]
+; MIPS32: sllv  [[T_LO:.*]],[[A_LO]],[[B_LO]]
+; MIPS32: move  [[T1_LO:.*]],[[T_LO]]
+; MIPS32: andi  [[T5:.*]],[[B_LO]],0x20
+; MIPS32: movn  [[T_HI]],[[T_LO]],[[T5]]
+; MIPS32: movn  [[T1_LO]],zero,[[T5]]
+; MIPS32: move  v1,[[T_HI]]
+
 define internal i64 @shr64BitSigned(i64 %a, i64 %b) {
 entry:
   %shr = ashr i64 %a, %b
   ret i64 %shr
 }
 ; CHECK-LABEL: shr64BitSigned
 ; CHECK: shrd
 ; CHECK: sar
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: shr64BitSigned
 ; OPTM1: shrd
 ; OPTM1: sar
 ; OPTM1: test {{.*}},0x20
 ; OPTM1: je
 ; OPTM1: sar {{.*}},0x1f
 
 ; ARM32-LABEL: shr64BitSigned
 ; ARM32: lsr     [[T0:r[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}}
 ; ARM32: rsb     [[T1:r[0-9]+]], r{{[0-9]+}}, #32
 ; ARM32: orr     r{{[0-9]+}}, [[T0]], r{{[0-9]+}}, lsl [[T1]]
 ; ARM32: sub     [[T2:r[0-9]+]], r{{[0-9]+}}, #32
 ; ARM32: cmp     [[T2]], #0
 ; ARM32: asrge   r{{[0-9]+}}, r{{[0-9]+}}, [[T2]]
 ; ARM32: asr     r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
 
+; MIPS32-LABEL: shr64BitSigned
+; MIPS32: srlv  [[T1:.*]],[[A_LO:.*]],[[B_LO:.*]]
+; MIPS32: nor   [[T2:.*]],[[B_LO]],zero
+; MIPS32: sll   [[T3:.*]],[[A_HI:.*]],0x1
+; MIPS32: sllv  [[T4:.*]],[[T3]],[[T2]]
+; MIPS32: or    [[T_LO:.*]],[[T1]],[[T4]]
+; MIPS32: srav  [[T_HI:.*]],[[A_HI]],[[B_LO]]
+; MIPS32: move  [[T_HI1:.*]],[[T_HI]]
+; MIPS32: andi  [[T5:.*]],[[B_LO]],0x20
+; MIPS32: movn  [[T_LO1:.*]],[[T_HI]],[[T5]]
+; MIPS32: sra   [[T6:.*]],[[A_HI]],0x1f
+; MIPS32: movn  [[T_HI1]],[[T6]],[[T5]]
+
 define internal i32 @shr64BitSignedTrunc(i64 %a, i64 %b) {
 entry:
   %shr = ashr i64 %a, %b
   %result = trunc i64 %shr to i32
   ret i32 %result
 }
 ; CHECK-LABEL: shr64BitSignedTrunc
 ; CHECK: shrd
 ; CHECK: sar
 ; CHECK: test {{.*}},0x20
@@ skipping 33 matching lines @@
 
 ; ARM32-LABEL: shr64BitUnsigned
 ; ARM32: lsr
 ; ARM32: rsb
 ; ARM32: orr
 ; ARM32: sub
 ; ARM32: cmp
 ; ARM32: lsrge
 ; ARM32: lsr
 
+; MIPS32-LABEL: shr64BitUnsigned
+; MIPS32: srlv  [[T1:.*]],[[A_LO:.*]],[[B_LO:.*]]
+; MIPS32: nor   [[T2:.*]],[[B_LO]],zero
+; MIPS32: sll   [[T3:.*]],[[A_HI:.*]],0x1
+; MIPS32: sllv  [[T4:.*]],[[T3]],[[T2]]
+; MIPS32: or    [[T_LO:.*]],[[T1]],[[T4]]
+; MIPS32: srlv  [[T_HI:.*]],[[A_HI]],[[B_LO]]
+; MIPS32: move  [[T_HI1:.*]],[[T_HI]]
+; MIPS32: andi  [[T5:.*]],[[B_LO]],0x20
+; MIPS32: movn  [[T_LO1:.*]],[[T_HI]],[[T5]]
+; MIPS32: movn  [[T_HI1]],zero,[[T5]]
+
 define internal i32 @shr64BitUnsignedTrunc(i64 %a, i64 %b) {
 entry:
   %shr = lshr i64 %a, %b
   %result = trunc i64 %shr to i32
   ret i32 %result
 }
 ; CHECK-LABEL: shr64BitUnsignedTrunc
 ; CHECK: shrd
 ; CHECK: shr
 ; CHECK: test {{.*}},0x20
@@ skipping 1413 matching lines @@
   %s = lshr i64 %a, 40
   %t = trunc i64 %s to i32
   %r = sub i32 %t, 1
   ret i32 %r
 ; ARM32-LABEL: subOneToUpperAfterShift
 ; ARM32: subs
 ; ARM32: sbc
 ; ARM32: lsr
 ; ARM32: sub
 }