Subzero, MIPS32: Intrinsic call Cttz for i32

src/IceTargetLoweringMIPS32.cpp

Index: src/IceTargetLoweringMIPS32.cpp
diff --git a/src/IceTargetLoweringMIPS32.cpp b/src/IceTargetLoweringMIPS32.cpp
index 32656ce4ee9ba008bee7b1f7482b627942c6a49c..2c48554284854be4cd0de08f6bff9fa8cbf63182 100644
--- a/src/IceTargetLoweringMIPS32.cpp
+++ b/src/IceTargetLoweringMIPS32.cpp
@@ -2847,10 +2847,33 @@ void TargetMIPS32::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
   }
   case Intrinsics::Ctlz: {
     UnimplementedLoweringError(this, Instr);
-    return;
   }
   case Intrinsics::Cttz: {
-    UnimplementedLoweringError(this, Instr);
+    auto *Src = Instr->getArg(0);
+    const Type SrcTy = Src->getType();
+    assert(SrcTy == IceType_i32 || SrcTy == IceType_i64);
+    switch (SrcTy) {
+    case IceType_i32: {
+      auto *T1 = I32Reg();
+      auto *T2 = I32Reg();
+      auto *SrcR = legalizeToReg(Src);
+      _addiu(T1, SrcR, -1);
+      _not(T2, SrcR);
+      Context.insert<InstFakeUse>(SrcR);

[Jim Stichnoth, 2016/09/23 06:13:47]

This FakeUse doesn't seem necessary?

[obucinac, 2016/09/23 11:37:32]

Done.

+      _and(T1, T2, T1);
+      _clz(T1, T1);
+      _addiu(T2, getZero(), 32);
+      _subu(T2, T2, T1);
+      _mov(Dest, T2);
+      break;
+    }
+    case IceType_i64: {
+      UnimplementedLoweringError(this, Instr);
+      break;
+    }
+    default:
+      llvm::report_fatal_error("Control flow should never have reached here.");
+    }
     return;
   }
   case Intrinsics::Fabs: {
@@ -3350,7 +3373,8 @@ void TargetMIPS32::postLower() {
     return;
   // TODO(rkotler): Find two-address non-SSA instructions where Dest==Src0,
   // and set the IsDestRedefined flag to keep liveness analysis consistent.
-  UnimplementedError(getFlags());
+  markRedefinitions();
+  Context.availabilityUpdate();
 }
 
 void TargetMIPS32::makeRandomRegisterPermutation(