Subzero, MIPS32: Intrinsic call Cttz for i32

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 2829 matching lines @@
   case Intrinsics::Bswap: {
     UnimplementedLoweringError(this, Instr);
     return;
   }
   case Intrinsics::Ctpop: {
     llvm::report_fatal_error("Ctpop should have been prelowered.");
     return;
   }
   case Intrinsics::Ctlz: {
     UnimplementedLoweringError(this, Instr);
-    return;
   }
   case Intrinsics::Cttz: {
-    UnimplementedLoweringError(this, Instr);
+    auto *Src = Instr->getArg(0);
+    const Type SrcTy = Src->getType();
+    assert(SrcTy == IceType_i32 || SrcTy == IceType_i64);
+    switch (SrcTy) {
+    case IceType_i32: {
+      auto *T1 = I32Reg();
+      auto *T2 = I32Reg();
+      auto *SrcR = legalizeToReg(Src);
+      _addiu(T1, SrcR, -1);
+      _not(T2, SrcR);
+      Context.insert<InstFakeUse>(SrcR);

[Jim Stichnoth, 2016/09/23 06:13:47]

This FakeUse doesn't seem necessary?

[obucinac, 2016/09/23 11:37:32]

Done.

+      _and(T1, T2, T1);
+      _clz(T1, T1);
+      _addiu(T2, getZero(), 32);
+      _subu(T2, T2, T1);
+      _mov(Dest, T2);
+      break;
+    }
+    case IceType_i64: {
+      UnimplementedLoweringError(this, Instr);
+      break;
+    }
+    default:
+      llvm::report_fatal_error("Control flow should never have reached here.");
+    }
     return;
   }
   case Intrinsics::Fabs: {
     if (isScalarFloatingType(DestTy)) {
       Variable *T = makeReg(DestTy);
       if (DestTy == IceType_f32) {
         _abs_s(T, legalizeToReg(Instr->getArg(0)));
       } else {
         _abs_d(T, legalizeToReg(Instr->getArg(0)));
       }
@@ skipping 479 matching lines @@
 // since loOperand() and hiOperand() don't expect Undef input.
 void TargetMIPS32::prelowerPhis() {
   PhiLowering::prelowerPhis32Bit<TargetMIPS32>(this, Context.getNode(), Func);
 }
 
 void TargetMIPS32::postLower() {
   if (Func->getOptLevel() == Opt_m1)
     return;
   // TODO(rkotler): Find two-address non-SSA instructions where Dest==Src0,
   // and set the IsDestRedefined flag to keep liveness analysis consistent.
-  UnimplementedError(getFlags());
+  markRedefinitions();
+  Context.availabilityUpdate();
 }
 
 void TargetMIPS32::makeRandomRegisterPermutation(
     llvm::SmallVectorImpl<RegNumT> &Permutation,
     const SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
   (void)Permutation;
   (void)ExcludeRegisters;
   (void)Salt;
   UnimplementedError(getFlags());
 }
@@ skipping 377 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice