| OLD | NEW |
| 1 // | 1 // |
| 2 // The Subzero Code Generator | 2 // The Subzero Code Generator |
| 3 // | 3 // |
| 4 // This file is distributed under the University of Illinois Open Source | 4 // This file is distributed under the University of Illinois Open Source |
| 5 // License. See LICENSE.TXT for details. | 5 // License. See LICENSE.TXT for details. |
| 6 // | 6 // |
| 7 //===----------------------------------------------------------------------===// | 7 //===----------------------------------------------------------------------===// |
| 8 /// | 8 /// |
| 9 /// \file | 9 /// \file |
| 10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost | 10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost |
| (...skipping 3319 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 3330 // Turn an i64 Phi instruction into a pair of i32 Phi instructions, to preserve | 3330 // Turn an i64 Phi instruction into a pair of i32 Phi instructions, to preserve |
| 3331 // integrity of liveness analysis. Undef values are also turned into zeroes, | 3331 // integrity of liveness analysis. Undef values are also turned into zeroes, |
| 3332 // since loOperand() and hiOperand() don't expect Undef input. | 3332 // since loOperand() and hiOperand() don't expect Undef input. |
| 3333 void TargetMIPS32::prelowerPhis() { | 3333 void TargetMIPS32::prelowerPhis() { |
| 3334 PhiLowering::prelowerPhis32Bit<TargetMIPS32>(this, Context.getNode(), Func); | 3334 PhiLowering::prelowerPhis32Bit<TargetMIPS32>(this, Context.getNode(), Func); |
| 3335 } | 3335 } |
| 3336 | 3336 |
| 3337 void TargetMIPS32::postLower() { | 3337 void TargetMIPS32::postLower() { |
| 3338 if (Func->getOptLevel() == Opt_m1) | 3338 if (Func->getOptLevel() == Opt_m1) |
| 3339 return; | 3339 return; |
| 3340 // TODO(rkotler): Find two-address non-SSA instructions where Dest==Src0, | 3340 markRedefinitions(); |
| 3341 // and set the IsDestRedefined flag to keep liveness analysis consistent. | 3341 Context.availabilityUpdate(); |
| 3342 UnimplementedError(getFlags()); | |
| 3343 } | 3342 } |
| 3344 | 3343 |
| 3345 void TargetMIPS32::makeRandomRegisterPermutation( | 3344 void TargetMIPS32::makeRandomRegisterPermutation( |
| 3346 llvm::SmallVectorImpl<RegNumT> &Permutation, | 3345 llvm::SmallVectorImpl<RegNumT> &Permutation, |
| 3347 const SmallBitVector &ExcludeRegisters, uint64_t Salt) const { | 3346 const SmallBitVector &ExcludeRegisters, uint64_t Salt) const { |
| 3348 (void)Permutation; | 3347 (void)Permutation; |
| 3349 (void)ExcludeRegisters; | 3348 (void)ExcludeRegisters; |
| 3350 (void)Salt; | 3349 (void)Salt; |
| 3351 UnimplementedError(getFlags()); | 3350 UnimplementedError(getFlags()); |
| 3352 } | 3351 } |
| (...skipping 377 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 3730 Str << "\t.set\t" | 3729 Str << "\t.set\t" |
| 3731 << "nomips16\n"; | 3730 << "nomips16\n"; |
| 3732 } | 3731 } |
| 3733 | 3732 |
| 3734 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; | 3733 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; |
| 3735 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; | 3734 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; |
| 3736 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; | 3735 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; |
| 3737 | 3736 |
| 3738 } // end of namespace MIPS32 | 3737 } // end of namespace MIPS32 |
| 3739 } // end of namespace Ice | 3738 } // end of namespace Ice |
| OLD | NEW |