Subzero, MIPS32: Instruction NOR, pseudoinstruction NOT

src/IceAssemblerMIPS32.cpp

 //===- subzero/src/IceAssemblerMIPS32.cpp - MIPS32 Assembler --------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 652 matching lines @@
   static constexpr IValueT Opcode = 0x44000002;
   emitCOP1FmtFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "mul.d");
 }
 
 void AssemblerMIPS32::mul_s(const Operand *OpFd, const Operand *OpFs,
                             const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000002;
   emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "mul.s");
 }
 
+void AssemblerMIPS32::nor(const Operand *OpRd, const Operand *OpRs,
+                          const Operand *OpRt) {
+  static constexpr IValueT Opcode = 0x00000027;
+  emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "nor");
+}
+
 void AssemblerMIPS32::or_(const Operand *OpRd, const Operand *OpRs,
                           const Operand *OpRt) {
   static constexpr IValueT Opcode = 0x00000025;
   emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "or");
 }
 
 void AssemblerMIPS32::ori(const Operand *OpRt, const Operand *OpRs,
                           const uint32_t Imm) {
   static constexpr IValueT Opcode = 0x34000000;
   emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "ori");
@@ skipping 214 matching lines @@
     emitBr(Cond, OpRs, OpRtNone, Dest);
     return;
   }
   const IOffsetT Position = Buffer.size();
   emitBr(Cond, OpRs, OpRtNone, TargetLabel->getEncodedPosition());
   TargetLabel->linkTo(*this, Position);
 }
 
 } // end of namespace MIPS32
 } // end of namespace Ice