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1 //===- subzero/src/IceAssemblerMIPS32.cpp - MIPS32 Assembler --------------===// | 1 //===- subzero/src/IceAssemblerMIPS32.cpp - MIPS32 Assembler --------------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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663 static constexpr IValueT Opcode = 0x44000002; | 663 static constexpr IValueT Opcode = 0x44000002; |
664 emitCOP1FmtFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "mul.d"); | 664 emitCOP1FmtFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "mul.d"); |
665 } | 665 } |
666 | 666 |
667 void AssemblerMIPS32::mul_s(const Operand *OpFd, const Operand *OpFs, | 667 void AssemblerMIPS32::mul_s(const Operand *OpFd, const Operand *OpFs, |
668 const Operand *OpFt) { | 668 const Operand *OpFt) { |
669 static constexpr IValueT Opcode = 0x44000002; | 669 static constexpr IValueT Opcode = 0x44000002; |
670 emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "mul.s"); | 670 emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "mul.s"); |
671 } | 671 } |
672 | 672 |
| 673 void AssemblerMIPS32::nor(const Operand *OpRd, const Operand *OpRs, |
| 674 const Operand *OpRt) { |
| 675 static constexpr IValueT Opcode = 0x00000027; |
| 676 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "nor"); |
| 677 } |
| 678 |
673 void AssemblerMIPS32::or_(const Operand *OpRd, const Operand *OpRs, | 679 void AssemblerMIPS32::or_(const Operand *OpRd, const Operand *OpRs, |
674 const Operand *OpRt) { | 680 const Operand *OpRt) { |
675 static constexpr IValueT Opcode = 0x00000025; | 681 static constexpr IValueT Opcode = 0x00000025; |
676 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "or"); | 682 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "or"); |
677 } | 683 } |
678 | 684 |
679 void AssemblerMIPS32::ori(const Operand *OpRt, const Operand *OpRs, | 685 void AssemblerMIPS32::ori(const Operand *OpRt, const Operand *OpRs, |
680 const uint32_t Imm) { | 686 const uint32_t Imm) { |
681 static constexpr IValueT Opcode = 0x34000000; | 687 static constexpr IValueT Opcode = 0x34000000; |
682 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "ori"); | 688 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "ori"); |
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897 emitBr(Cond, OpRs, OpRtNone, Dest); | 903 emitBr(Cond, OpRs, OpRtNone, Dest); |
898 return; | 904 return; |
899 } | 905 } |
900 const IOffsetT Position = Buffer.size(); | 906 const IOffsetT Position = Buffer.size(); |
901 emitBr(Cond, OpRs, OpRtNone, TargetLabel->getEncodedPosition()); | 907 emitBr(Cond, OpRs, OpRtNone, TargetLabel->getEncodedPosition()); |
902 TargetLabel->linkTo(*this, Position); | 908 TargetLabel->linkTo(*this, Position); |
903 } | 909 } |
904 | 910 |
905 } // end of namespace MIPS32 | 911 } // end of namespace MIPS32 |
906 } // end of namespace Ice | 912 } // end of namespace Ice |
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